Commit c8e68b7e authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter

drm/i915: PSR VLV/CHV: Remove condition checks that only applies to Haswell.

These conditions applies only to Haswell and we were also checking for them
on Valleyview/Cherryview.
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarDurgadoss R <durgadoss.r@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 46c3fce6
...@@ -270,22 +270,19 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp) ...@@ -270,22 +270,19 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
return false; return false;
} }
/* Below limitations aren't valid for Broadwell */ if (IS_HASWELL(dev) &&
if (IS_BROADWELL(dev)) I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
goto out; S3D_ENABLE) {
if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
S3D_ENABLE) {
DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
return false; return false;
} }
if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { if (IS_HASWELL(dev) &&
intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
return false; return false;
} }
out:
dev_priv->psr.source_ok = true; dev_priv->psr.source_ok = true;
return true; return true;
} }
......
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