Commit c99e515a authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Michael Turquette

clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver

Add an LCC driver for IPQ806x that supports the i2s, S/PDIF, and
pcm clocks.
Signed-off-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: default avatarKumar Gala <galak@codeaurora.org>
Signed-off-by: default avatarJosh Cartwright <joshc@codeaurora.org>
[sboyd@codeaurora.org: Reworded commit text, added Kconfig
select, fleshed out Kconfig description a bit more, added pll4
configuration and reworked probe for it, added muxes, split out
dt-binding file]
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Tested-by: default avatarKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
parent 2a5cfec9
...@@ -29,6 +29,15 @@ config IPQ_GCC_806X ...@@ -29,6 +29,15 @@ config IPQ_GCC_806X
Say Y if you want to use peripheral devices such as UART, SPI, Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc. i2c, USB, SD/eMMC, etc.
config IPQ_LCC_806X
tristate "IPQ806x LPASS Clock Controller"
select IPQ_GCC_806X
depends on COMMON_CLK_QCOM
help
Support for the LPASS clock controller on ipq806x devices.
Say Y if you want to use audio devices such as i2s, pcm,
S/PDIF, etc.
config MSM_GCC_8660 config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller" tristate "MSM8660 Global Clock Controller"
depends on COMMON_CLK_QCOM depends on COMMON_CLK_QCOM
......
...@@ -13,6 +13,7 @@ clk-qcom-y += reset.o ...@@ -13,6 +13,7 @@ clk-qcom-y += reset.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
......
...@@ -75,6 +75,17 @@ static struct clk_pll pll3 = { ...@@ -75,6 +75,17 @@ static struct clk_pll pll3 = {
}, },
}; };
static struct clk_regmap pll4_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pll4_vote",
.parent_names = (const char *[]){ "pll4" },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll pll8 = { static struct clk_pll pll8 = {
.l_reg = 0x3144, .l_reg = 0x3144,
.m_reg = 0x3148, .m_reg = 0x3148,
...@@ -2163,6 +2174,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { ...@@ -2163,6 +2174,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL0] = &pll0.clkr, [PLL0] = &pll0.clkr,
[PLL0_VOTE] = &pll0_vote, [PLL0_VOTE] = &pll0_vote,
[PLL3] = &pll3.clkr, [PLL3] = &pll3.clkr,
[PLL4_VOTE] = &pll4_vote,
[PLL8] = &pll8.clkr, [PLL8] = &pll8.clkr,
[PLL8_VOTE] = &pll8_vote, [PLL8_VOTE] = &pll8_vote,
[PLL14] = &pll14.clkr, [PLL14] = &pll14.clkr,
......
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