Commit ca903b6f authored by Vaibhav Bedia's avatar Vaibhav Bedia Committed by Paul Walmsley

ARM: OMAP2+: AM33XX: hwmod: Register OCMC RAM hwmod

OCMC RAM lies in the PER power domain and this memory
support retention.
Signed-off-by: default avatarVaibhav Bedia <vaibhav.bedia@ti.com>
Acked-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: default avatarPeter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 1a7cb4d9
...@@ -414,7 +414,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = { ...@@ -414,7 +414,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
* - cEFUSE (doesn't fall under any ocp_if) * - cEFUSE (doesn't fall under any ocp_if)
* - clkdiv32k * - clkdiv32k
* - debugss * - debugss
* - ocmc ram
* - ocp watch point * - ocp watch point
* - aes0 * - aes0
* - sha0 * - sha0
...@@ -481,25 +480,6 @@ static struct omap_hwmod am33xx_debugss_hwmod = { ...@@ -481,25 +480,6 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
}, },
}; };
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
.name = "ocmcram",
};
static struct omap_hwmod am33xx_ocmcram_hwmod = {
.name = "ocmcram",
.class = &am33xx_ocmcram_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* ocpwp */ /* ocpwp */
static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
.name = "ocpwp", .name = "ocpwp",
...@@ -570,6 +550,25 @@ static struct omap_hwmod am33xx_sha0_hwmod = { ...@@ -570,6 +550,25 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
#endif #endif
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
.name = "ocmcram",
};
static struct omap_hwmod am33xx_ocmcram_hwmod = {
.name = "ocmcram",
.class = &am33xx_ocmcram_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* 'smartreflex' class */ /* 'smartreflex' class */
static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
.name = "smartreflex", .name = "smartreflex",
...@@ -3328,6 +3327,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { ...@@ -3328,6 +3327,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
.flags = OCPIF_SWSUP_IDLE, .flags = OCPIF_SWSUP_IDLE,
}; };
/* l3 main -> ocmc */
static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_ocmcram_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_fw__emif_fw, &am33xx_l4_fw__emif_fw,
&am33xx_l3_main__emif, &am33xx_l3_main__emif,
...@@ -3398,6 +3404,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { ...@@ -3398,6 +3404,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__tptc0, &am33xx_l3_main__tptc0,
&am33xx_l3_main__tptc1, &am33xx_l3_main__tptc1,
&am33xx_l3_main__tptc2, &am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc,
&am33xx_l3_s__usbss, &am33xx_l3_s__usbss,
&am33xx_l4_hs__cpgmac0, &am33xx_l4_hs__cpgmac0,
&am33xx_cpgmac0__mdio, &am33xx_cpgmac0__mdio,
......
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