drm/amd/display: update dml to allow sync with DV

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h

@@ -108,4 +108,17 @@ enum output_standard {
 	dm_std_uninitialized = 0, dm_std_cvtr2, dm_std_cvt
 };
 
+enum mpc_combine_affinity {
+	dm_mpc_always_when_possible,
+	dm_mpc_reduce_voltage,
+	dm_mpc_reduce_voltage_and_clocks
+};
+
+enum self_refresh_affinity {
+	dm_try_to_allow_self_refresh_and_mclk_switch,
+	dm_allow_self_refresh_and_mclk_switch,
+	dm_allow_self_refresh,
+	dm_neither_self_refresh_nor_mclk_switch
+};
+
 #endif

drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

@@ -76,8 +76,16 @@ struct	_vcs_dpi_soc_bounding_box_st	{
 	double sr_exit_time_us;
 	double sr_enter_plus_exit_time_us;
 	double urgent_latency_us;
+	double urgent_latency_pixel_data_only_us;
+	double urgent_latency_pixel_mixed_with_vm_data_us;
+	double urgent_latency_vm_data_only_us;
 	double writeback_latency_us;
 	double ideal_dram_bw_after_urgent_percent;
+	double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
+	double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
+	double pct_ideal_dram_sdp_bw_after_urgent_vm_only;
+	double max_avg_sdp_bw_use_normal_percent;
+	double max_avg_dram_bw_use_normal_percent;
 	unsigned int max_request_size_bytes;
 	double downspread_percent;
 	double dram_page_open_time_ns;
@@ -88,6 +96,9 @@ struct	_vcs_dpi_soc_bounding_box_st	{
 	double dcn_downspread_percent;
 	double dispclk_dppclk_vco_speed_mhz;
 	double dfs_vco_period_ps;
+	unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
+	unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
+	unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
 	unsigned int round_trip_ping_latency_dcfclk_cycles;
 	unsigned int urgent_out_of_order_return_per_channel_bytes;
 	unsigned int channel_interleave_bytes;
@@ -100,10 +111,17 @@ struct	_vcs_dpi_soc_bounding_box_st	{
 	unsigned int voltage_override;
 	double xfc_bus_transport_time_us;
 	double xfc_xbuf_latency_tolerance_us;
+	int use_urgent_burst_bw;
 	struct _vcs_dpi_voltage_scaling_st clock_limits[7];
 };
 
 struct _vcs_dpi_ip_params_st {
+	bool gpuvm_enable;
+	bool hostvm_enable;
+	unsigned int gpuvm_max_page_table_levels;
+	unsigned int hostvm_max_page_table_levels;
+	unsigned int hostvm_cached_page_table_levels;
+	unsigned int pte_group_size_bytes;
 	unsigned int max_inter_dcn_tile_repeaters;
 	unsigned int num_dsc;
 	unsigned int odm_capable;
@@ -176,8 +194,12 @@ struct	_vcs_dpi_display_pipe_source_params_st	{
 	unsigned int dcc_rate;
 	unsigned char dcc_use_global;
 	unsigned char vm;
-	unsigned char	vm_levels_force_en;
-	unsigned int	vm_levels_force;
+	bool gpuvm;    // gpuvm enabled
+	bool hostvm;    // hostvm enabled
+	bool gpuvm_levels_force_en;
+	unsigned int gpuvm_levels_force;
+	bool hostvm_levels_force_en;
+	unsigned int hostvm_levels_force;
 	int source_scan;
 	int sw_mode;
 	int macro_tile_size;
@@ -225,7 +247,7 @@ struct	_vcs_dpi_display_output_params_st	{
 	int dsc_enable;
 	int wb_enable;
 	int num_active_wb;
-	int	opp_input_bpc;
+	int output_bpc;
 	int output_type;
 	int output_format;
 	int output_standard;

drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h

@@ -35,6 +35,16 @@ static inline double dml_min(double a, double b)
 	return (double) dcn_bw_min2(a, b);
 }
 
+static inline double dml_min3(double a, double b, double c)
+{
+	return dml_min(dml_min(a, b), c);
+}
+
+static inline double dml_min4(double a, double b, double c, double d)
+{
+	return dml_min(dml_min(a, b), dml_min(c, d));
+}
+
 static inline double dml_max(double a, double b)
 {
 	return (double) dcn_bw_max2(a, b);