Commit cd3cb7c0 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher

drm/amd/pp: Fix build warning in vegam

warning: missing braces around initializer [-Wmissing-braces]
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5326c452
......@@ -320,7 +320,7 @@ int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
pp_atomctrl_memory_clock_param_ai *mpll_param)
{
struct amdgpu_device *adev = hwmgr->adev;
COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {0};
COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {{0}, 0, 0};
int result;
mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
......
......@@ -1366,10 +1366,12 @@ static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
struct SMU75_Discrete_MCArbDramTimingTable arb_regs = {0};
struct SMU75_Discrete_MCArbDramTimingTable arb_regs;
uint32_t i, j;
int result = 0;
memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable));
for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
result = vegam_populate_memory_timing_parameters(hwmgr,
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment