Commit cf2ff877 authored by Levin Du's avatar Levin Du Committed by Linus Walleij

gpio: syscon: rockchip: add GRF GPIO support for rk3328

In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec
mute control, can also be used for general purpose. It is manipulated by
the GRF_SOC_CON10 register in GRF. Aside from the GPIO_MUTE pin, the HDMI
pins can also be set in the same way.

Currently this GRF GPIO controller only supports the mute pin. If needed
in the future, the HDMI pins support can also be added.
Signed-off-by: default avatarLevin Du <djw@t-chip.com.cn>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 442af140
Rockchip RK3328 GRF (General Register Files) GPIO controller.
In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec mute
control, can also be used for general purpose. It is manipulated by the
GRF_SOC_CON10 register in GRF. Aside from the GPIO_MUTE pin, the HDMI pins can
also be set in the same way.
Currently this GPIO controller only supports the mute pin. If needed in the
future, the HDMI pins support can also be added.
Required properties:
- compatible: Should contain "rockchip,rk3328-grf-gpio".
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be 2. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
0 = Active high,
1 = Active low.
Example:
grf: syscon@ff100000 {
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
grf_gpio: grf-gpio {
compatible = "rockchip,rk3328-grf-gpio";
gpio-controller;
#gpio-cells = <2>;
};
};
Note: The grf_gpio node should be declared as the child of the GRF (General
Register File) node. The GPIO_MUTE pin is referred to as <&grf_gpio 0>.
...@@ -135,6 +135,33 @@ static const struct syscon_gpio_data clps711x_mctrl_gpio = { ...@@ -135,6 +135,33 @@ static const struct syscon_gpio_data clps711x_mctrl_gpio = {
.dat_bit_offset = 0x40 * 8 + 8, .dat_bit_offset = 0x40 * 8 + 8,
}; };
static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
int val)
{
struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
unsigned int offs;
u8 bit;
u32 data;
int ret;
offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
bit = offs % SYSCON_REG_BITS;
data = (val ? BIT(bit) : 0) | BIT(bit + 16);
ret = regmap_write(priv->syscon,
(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
data);
if (ret < 0)
dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
}
static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = {
/* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */
.flags = GPIO_SYSCON_FEAT_OUT,
.bit_count = 1,
.dat_bit_offset = 0x0428 * 8 + 1,
.set = rockchip_gpio_set,
};
#define KEYSTONE_LOCK_BIT BIT(0) #define KEYSTONE_LOCK_BIT BIT(0)
static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val) static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
...@@ -175,6 +202,10 @@ static const struct of_device_id syscon_gpio_ids[] = { ...@@ -175,6 +202,10 @@ static const struct of_device_id syscon_gpio_ids[] = {
.compatible = "ti,keystone-dsp-gpio", .compatible = "ti,keystone-dsp-gpio",
.data = &keystone_dsp_gpio, .data = &keystone_dsp_gpio,
}, },
{
.compatible = "rockchip,rk3328-grf-gpio",
.data = &rockchip_rk3328_gpio_mute,
},
{ } { }
}; };
MODULE_DEVICE_TABLE(of, syscon_gpio_ids); MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment