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nexedi
linux
Commits
cf96e46f
Commit
cf96e46f
authored
Jul 25, 2011
by
Keith Packard
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Merge branch 'drm-intel-fixes' into drm-intel-next
parents
887a82ee
e8519464
Changes
2
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2 changed files
with
18 additions
and
6 deletions
+18
-6
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_dp.c
+14
-6
drivers/gpu/drm/i915/intel_panel.c
drivers/gpu/drm/i915/intel_panel.c
+4
-0
No files found.
drivers/gpu/drm/i915/intel_dp.c
View file @
cf96e46f
...
@@ -1335,10 +1335,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
...
@@ -1335,10 +1335,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
u32
reg
;
u32
reg
;
uint32_t
DP
=
intel_dp
->
DP
;
uint32_t
DP
=
intel_dp
->
DP
;
/* Enable output, wait for it to become active */
/*
I915_WRITE
(
intel_dp
->
output_reg
,
intel_dp
->
DP
);
* On CPT we have to enable the port in training pattern 1, which
POSTING_READ
(
intel_dp
->
output_reg
);
* will happen below in intel_dp_set_link_train. Otherwise, enable
intel_wait_for_vblank
(
dev
,
intel_crtc
->
pipe
);
* the port and wait for it to become active.
*/
if
(
!
HAS_PCH_CPT
(
dev
))
{
I915_WRITE
(
intel_dp
->
output_reg
,
intel_dp
->
DP
);
POSTING_READ
(
intel_dp
->
output_reg
);
intel_wait_for_vblank
(
dev
,
intel_crtc
->
pipe
);
}
/* Write the link configuration data */
/* Write the link configuration data */
intel_dp_aux_native_write
(
intel_dp
,
DP_LINK_BW_SET
,
intel_dp_aux_native_write
(
intel_dp
,
DP_LINK_BW_SET
,
...
@@ -1371,7 +1377,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
...
@@ -1371,7 +1377,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
reg
=
DP
|
DP_LINK_TRAIN_PAT_1
;
reg
=
DP
|
DP_LINK_TRAIN_PAT_1
;
if
(
!
intel_dp_set_link_train
(
intel_dp
,
reg
,
if
(
!
intel_dp_set_link_train
(
intel_dp
,
reg
,
DP_TRAINING_PATTERN_1
))
DP_TRAINING_PATTERN_1
|
DP_LINK_SCRAMBLING_DISABLE
))
break
;
break
;
/* Set training pattern 1 */
/* Set training pattern 1 */
...
@@ -1446,7 +1453,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
...
@@ -1446,7 +1453,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
/* channel eq pattern */
/* channel eq pattern */
if
(
!
intel_dp_set_link_train
(
intel_dp
,
reg
,
if
(
!
intel_dp_set_link_train
(
intel_dp
,
reg
,
DP_TRAINING_PATTERN_2
))
DP_TRAINING_PATTERN_2
|
DP_LINK_SCRAMBLING_DISABLE
))
break
;
break
;
udelay
(
400
);
udelay
(
400
);
...
...
drivers/gpu/drm/i915/intel_panel.c
View file @
cf96e46f
...
@@ -83,11 +83,15 @@ intel_pch_panel_fitting(struct drm_device *dev,
...
@@ -83,11 +83,15 @@ intel_pch_panel_fitting(struct drm_device *dev,
u32
scaled_height
=
mode
->
hdisplay
*
adjusted_mode
->
vdisplay
;
u32
scaled_height
=
mode
->
hdisplay
*
adjusted_mode
->
vdisplay
;
if
(
scaled_width
>
scaled_height
)
{
/* pillar */
if
(
scaled_width
>
scaled_height
)
{
/* pillar */
width
=
scaled_height
/
mode
->
vdisplay
;
width
=
scaled_height
/
mode
->
vdisplay
;
if
(
width
&
1
)
width
++
;
x
=
(
adjusted_mode
->
hdisplay
-
width
+
1
)
/
2
;
x
=
(
adjusted_mode
->
hdisplay
-
width
+
1
)
/
2
;
y
=
0
;
y
=
0
;
height
=
adjusted_mode
->
vdisplay
;
height
=
adjusted_mode
->
vdisplay
;
}
else
if
(
scaled_width
<
scaled_height
)
{
/* letter */
}
else
if
(
scaled_width
<
scaled_height
)
{
/* letter */
height
=
scaled_width
/
mode
->
hdisplay
;
height
=
scaled_width
/
mode
->
hdisplay
;
if
(
height
&
1
)
height
++
;
y
=
(
adjusted_mode
->
vdisplay
-
height
+
1
)
/
2
;
y
=
(
adjusted_mode
->
vdisplay
-
height
+
1
)
/
2
;
x
=
0
;
x
=
0
;
width
=
adjusted_mode
->
hdisplay
;
width
=
adjusted_mode
->
hdisplay
;
...
...
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