Commit d01e12dd authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal

Pull thermal management updates from Eduardo Valentin:

 - rework tsens driver to add support for tsens-v2 (Amit Kucheria)

 - rework armada thermal driver to use syscon and multichannel support
   (Miquel Raynal)

 - fixes to TI SoC, IMX, Exynos, RCar, and hwmon drivers

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal: (34 commits)
  thermal: armada: fix copy-paste error in armada_thermal_probe()
  thermal: rcar_thermal: avoid NULL dereference in absence of IRQ resources
  thermal: samsung: Remove Exynos5440 clock handling left-overs
  thermal: tsens: Fix negative temperature reporting
  thermal: tsens: switch from of_iomap() to devm_ioremap_resource()
  thermal: tsens: Rename variable
  thermal: tsens: Add generic support for TSENS v2 IP
  thermal: tsens: Rename tsens-8996 to tsens-v2 for reuse
  thermal: tsens: Add support to split up register address space into two
  dt: thermal: tsens: Document the fallback DT property for v2 of TSENS IP
  thermal: tsens: Get rid of unused fields in structure
  thermal_hwmon: Pass the originating device down to hwmon_device_register_with_info
  thermal_hwmon: Sanitize attribute name passed to hwmon
  dt-bindings: thermal: armada: add reference to new bindings
  dt-bindings: cp110: add the thermal node in the syscon file
  dt-bindings: cp110: update documentation since DT de-duplication
  dt-bindings: ap806: add the thermal node in the syscon file
  dt-bindings: cp110: prepare the syscon file to list other syscons nodes
  dt-bindings: ap806: prepare the syscon file to list other syscons nodes
  dt-bindings: cp110: rename cp110 syscon file
  ...
parents 9502f0d1 84b64de5
No related merge requests found
......@@ -2,15 +2,18 @@ Marvell Armada AP806 System Controller
======================================
The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
SoCs. It contains a system controller, which provides a number
registers giving access to numerous features: clocks, pin-muxing and
many other SoC configuration items. This DT binding allows to describe
this system controller.
SoCs. It contains system controllers, which provide several registers
giving access to numerous features: clocks, pin-muxing and many other
SoC configuration items. This DT binding allows to describe these
system controllers.
For the top level node:
- compatible: must be: "syscon", "simple-mfd";
- reg: register area of the AP806 system controller
SYSTEM CONTROLLER 0
===================
Clocks:
-------
......@@ -98,3 +101,38 @@ ap_syscon: system-controller@6f4000 {
gpio-ranges = <&ap_pinctrl 0 0 19>;
};
};
SYSTEM CONTROLLER 1
===================
Thermal:
--------
For common binding part and usage, refer to
Documentation/devicetree/bindings/thermal/thermal.txt
The thermal IP can probe the temperature all around the processor. It
may feature several channels, each of them wired to one sensor.
Required properties:
- compatible: must be one of:
* marvell,armada-ap806-thermal
- reg: register range associated with the thermal functions.
Optional properties:
- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
to this IP and represents the channel ID. There is one sensor per
channel. O refers to the thermal IP internal channel, while positive
IDs refer to each CPU.
Example:
ap_syscon1: system-controller@6f8000 {
compatible = "syscon", "simple-mfd";
reg = <0x6f8000 0x1000>;
ap_thermal: thermal-sensor@80 {
compatible = "marvell,armada-ap806-thermal";
reg = <0x80 0x10>;
#thermal-sensor-cells = <1>;
};
};
Marvell Armada CP110 System Controller 0
========================================
Marvell Armada CP110 System Controller
======================================
The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
SoCs. It contains two sets of system control registers, System
Controller 0 and System Controller 1. This Device Tree binding allows
to describe the first system controller, which provides registers to
configure various aspects of the SoC.
SoCs. It contains system controllers, which provide several registers
giving access to numerous features: clocks, pin-muxing and many other
SoC configuration items. This DT binding allows to describe these
system controllers.
For the top level node:
- compatible: must be: "syscon", "simple-mfd";
- reg: register area of the CP110 system controller 0
- reg: register area of the CP110 system controller
SYSTEM CONTROLLER 0
===================
Clocks:
-------
......@@ -163,26 +166,60 @@ Required properties:
Example:
cpm_syscon0: system-controller@440000 {
CP110_LABEL(syscon0): system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
cpm_clk: clock {
CP110_LABEL(clk): clock {
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
};
cpm_pinctrl: pinctrl {
CP110_LABEL(pinctrl): pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
};
cpm_gpio1: gpio@100 {
CP110_LABEL(gpio1): gpio@100 {
compatible = "marvell,armada-8k-gpio";
offset = <0x100>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cpm_pinctrl 0 0 32>;
gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
};
};
SYSTEM CONTROLLER 1
===================
Thermal:
--------
The thermal IP can probe the temperature all around the processor. It
may feature several channels, each of them wired to one sensor.
For common binding part and usage, refer to
Documentation/devicetree/bindings/thermal/thermal.txt
Required properties:
- compatible: must be one of:
* marvell,armada-cp110-thermal
- reg: register range associated with the thermal functions.
Optional properties:
- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
to this IP and represents the channel ID. There is one sensor per
channel. O refers to the thermal IP internal channel.
Example:
CP110_LABEL(syscon1): system-controller@6f8000 {
compatible = "syscon", "simple-mfd";
reg = <0x6f8000 0x1000>;
CP110_LABEL(thermal): thermal-sensor@70 {
compatible = "marvell,armada-cp110-thermal";
reg = <0x70 0x10>;
#thermal-sensor-cells = <1>;
};
};
......@@ -10,6 +10,11 @@ Required properties:
* marvell,armada-ap806-thermal
* marvell,armada-cp110-thermal
Note: these bindings are deprecated for AP806/CP110 and should instead
follow the rules described in:
Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
- reg: Device's register space.
Two entries are expected, see the examples below. The first one points
to the status register (4B). The second one points to the control
......
* QCOM SoC Temperature Sensor (TSENS)
Required properties:
- compatible :
- "qcom,msm8916-tsens" : For 8916 Family of SoCs
- "qcom,msm8974-tsens" : For 8974 Family of SoCs
- "qcom,msm8996-tsens" : For 8996 Family of SoCs
- compatible:
Must be one of the following:
- "qcom,msm8916-tsens" (MSM8916)
- "qcom,msm8974-tsens" (MSM8974)
- "qcom,msm8996-tsens" (MSM8996)
- "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998)
- "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845)
The generic "qcom,tsens-v2" property must be used as a fallback for any SoC
with version 2 of the TSENS IP. MSM8996 is the only exception because the
generic property did not exist when support was added.
- reg: Address range of the thermal registers.
New platforms containing v2.x.y of the TSENS IP must specify the SROT and TM
register spaces separately, with order being TM before SROT.
See Example 2, below.
- reg: Address range of the thermal registers
- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
- #qcom,sensors: Number of sensors in tsens block
- Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify
nvmem cells
Example:
Example 1 (legacy support before a fallback tsens-v2 property was introduced):
tsens: thermal-sensor@900000 {
compatible = "qcom,msm8916-tsens";
reg = <0x4a8000 0x2000>;
......@@ -20,3 +30,12 @@ tsens: thermal-sensor@900000 {
nvmem-cell-names = "caldata", "calsel";
#thermal-sensor-cells = <1>;
};
Example 2 (for any platform containing v2 of the TSENS IP):
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
reg = <0xc263000 0x1ff>, /* TM */
<0xc222000 0x1ff>; /* SROT */
#qcom,sensors = <13>;
#thermal-sensor-cells = <1>;
};
This diff is collapsed.
......@@ -605,7 +605,10 @@ static int imx_init_from_nvmem_cells(struct platform_device *pdev)
ret = nvmem_cell_read_u32(&pdev->dev, "calib", &val);
if (ret)
return ret;
imx_init_calib(pdev, val);
ret = imx_init_calib(pdev, val);
if (ret)
return ret;
ret = nvmem_cell_read_u32(&pdev->dev, "temp_grade", &val);
if (ret)
......
obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o
qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-8996.o
qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-v2.o
......@@ -16,6 +16,7 @@
#include <linux/io.h>
#include <linux/nvmem-consumer.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "tsens.h"
......@@ -103,11 +104,11 @@ int get_temp_common(struct tsens_device *tmdev, int id, int *temp)
{
struct tsens_sensor *s = &tmdev->sensor[id];
u32 code;
unsigned int sensor_addr;
unsigned int status_reg;
int last_temp = 0, ret;
sensor_addr = S0_ST_ADDR + s->hw_id * SN_ADDR_OFFSET;
ret = regmap_read(tmdev->map, sensor_addr, &code);
status_reg = S0_ST_ADDR + s->hw_id * SN_ADDR_OFFSET;
ret = regmap_read(tmdev->map, status_reg, &code);
if (ret)
return ret;
last_temp = code & SN_ST_TEMP_MASK;
......@@ -126,16 +127,28 @@ static const struct regmap_config tsens_config = {
int __init init_common(struct tsens_device *tmdev)
{
void __iomem *base;
struct resource *res;
struct platform_device *op = of_find_device_by_node(tmdev->dev->of_node);
base = of_iomap(tmdev->dev->of_node, 0);
if (!base)
if (!op)
return -EINVAL;
/* The driver only uses the TM register address space for now */
if (op->num_resources > 1) {
tmdev->tm_offset = 0;
} else {
/* old DTs where SROT and TM were in a contiguous 2K block */
tmdev->tm_offset = 0x1000;
}
res = platform_get_resource(op, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&op->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
tmdev->map = devm_regmap_init_mmio(tmdev->dev, base, &tsens_config);
if (IS_ERR(tmdev->map)) {
iounmap(base);
if (IS_ERR(tmdev->map))
return PTR_ERR(tmdev->map);
}
return 0;
}
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (c) 2018, Linaro Limited
*/
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/bitops.h>
#include "tsens.h"
#define STATUS_OFFSET 0x10a0
#define STATUS_OFFSET 0xa0
#define LAST_TEMP_MASK 0xfff
#define STATUS_VALID_BIT BIT(21)
#define CODE_SIGN_BIT BIT(11)
static int get_temp_8996(struct tsens_device *tmdev, int id, int *temp)
static int get_temp_tsens_v2(struct tsens_device *tmdev, int id, int *temp)
{
struct tsens_sensor *s = &tmdev->sensor[id];
u32 code;
unsigned int sensor_addr;
int last_temp = 0, last_temp2 = 0, last_temp3 = 0, ret;
unsigned int status_reg;
u32 last_temp = 0, last_temp2 = 0, last_temp3 = 0;
int ret;
sensor_addr = STATUS_OFFSET + s->hw_id * 4;
ret = regmap_read(tmdev->map, sensor_addr, &code);
status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * 4;
ret = regmap_read(tmdev->map, status_reg, &code);
if (ret)
return ret;
last_temp = code & LAST_TEMP_MASK;
......@@ -37,7 +29,7 @@ static int get_temp_8996(struct tsens_device *tmdev, int id, int *temp)
goto done;
/* Try a second time */
ret = regmap_read(tmdev->map, sensor_addr, &code);
ret = regmap_read(tmdev->map, status_reg, &code);
if (ret)
return ret;
if (code & STATUS_VALID_BIT) {
......@@ -48,7 +40,7 @@ static int get_temp_8996(struct tsens_device *tmdev, int id, int *temp)
}
/* Try a third/last time */
ret = regmap_read(tmdev->map, sensor_addr, &code);
ret = regmap_read(tmdev->map, status_reg, &code);
if (ret)
return ret;
if (code & STATUS_VALID_BIT) {
......@@ -63,22 +55,23 @@ static int get_temp_8996(struct tsens_device *tmdev, int id, int *temp)
else if (last_temp2 == last_temp3)
last_temp = last_temp3;
done:
/* Code sign bit is the sign extension for a negative value */
if (last_temp & CODE_SIGN_BIT)
last_temp |= ~CODE_SIGN_BIT;
/* Temperatures are in deciCelicius */
*temp = last_temp * 100;
/* Convert temperature from deciCelsius to milliCelsius */
*temp = sign_extend32(last_temp, fls(LAST_TEMP_MASK) - 1) * 100;
return 0;
}
static const struct tsens_ops ops_8996 = {
static const struct tsens_ops ops_generic_v2 = {
.init = init_common,
.get_temp = get_temp_8996,
.get_temp = get_temp_tsens_v2,
};
const struct tsens_data data_tsens_v2 = {
.ops = &ops_generic_v2,
};
/* Kept around for backward compatibility with old msm8996.dtsi */
const struct tsens_data data_8996 = {
.num_sensors = 13,
.ops = &ops_8996,
.ops = &ops_generic_v2,
};
......@@ -72,6 +72,9 @@ static const struct of_device_id tsens_table[] = {
}, {
.compatible = "qcom,msm8996-tsens",
.data = &data_8996,
}, {
.compatible = "qcom,tsens-v2",
.data = &data_tsens_v2,
},
{}
};
......
......@@ -77,9 +77,8 @@ struct tsens_device {
struct device *dev;
u32 num_sensors;
struct regmap *map;
struct regmap_field *status_field;
u32 tm_offset;
struct tsens_context ctx;
bool trdy;
const struct tsens_ops *ops;
struct tsens_sensor sensor[0];
};
......@@ -89,6 +88,9 @@ void compute_intercept_slope(struct tsens_device *, u32 *, u32 *, u32);
int init_common(struct tsens_device *);
int get_temp_common(struct tsens_device *, int, int *);
extern const struct tsens_data data_8916, data_8974, data_8960, data_8996;
/* TSENS v1 targets */
extern const struct tsens_data data_8916, data_8974, data_8960;
/* TSENS v2 targets */
extern const struct tsens_data data_8996, data_tsens_v2;
#endif /* __QCOM_TSENS_H__ */
......@@ -598,7 +598,7 @@ static int rcar_thermal_probe(struct platform_device *pdev)
enr_bits |= 3 << (i * 8);
}
if (enr_bits)
if (common->base && enr_bits)
rcar_thermal_common_write(common, ENR, enr_bits);
dev_info(dev, "%d sensor probed\n", i);
......
......@@ -789,11 +789,6 @@ static void exynos_tmu_work(struct work_struct *work)
struct exynos_tmu_data *data = container_of(work,
struct exynos_tmu_data, irq_work);
if (!IS_ERR(data->clk_sec))
clk_enable(data->clk_sec);
if (!IS_ERR(data->clk_sec))
clk_disable(data->clk_sec);
thermal_zone_device_update(data->tzd, THERMAL_EVENT_UNSPECIFIED);
mutex_lock(&data->lock);
......
......@@ -142,7 +142,8 @@ int thermal_add_hwmon_sysfs(struct thermal_zone_device *tz)
INIT_LIST_HEAD(&hwmon->tz_list);
strlcpy(hwmon->type, tz->type, THERMAL_NAME_LENGTH);
hwmon->device = hwmon_device_register_with_info(NULL, hwmon->type,
strreplace(hwmon->type, '-', '_');
hwmon->device = hwmon_device_register_with_info(&tz->device, hwmon->type,
hwmon, NULL, NULL);
if (IS_ERR(hwmon->device)) {
result = PTR_ERR(hwmon->device);
......
......@@ -54,56 +54,36 @@
#define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8
#define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154
#define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac
#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET 0x1c4
#define DRA752_DTEMP_CORE_0_OFFSET 0x208
#define DRA752_DTEMP_CORE_1_OFFSET 0x20c
#define DRA752_DTEMP_CORE_2_OFFSET 0x210
#define DRA752_DTEMP_CORE_3_OFFSET 0x214
#define DRA752_DTEMP_CORE_4_OFFSET 0x218
/* DRA752.iva register offsets */
#define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388
#define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398
#define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4
#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET 0x3b4
#define DRA752_DTEMP_IVA_0_OFFSET 0x3d0
#define DRA752_DTEMP_IVA_1_OFFSET 0x3d4
#define DRA752_DTEMP_IVA_2_OFFSET 0x3d8
#define DRA752_DTEMP_IVA_3_OFFSET 0x3dc
#define DRA752_DTEMP_IVA_4_OFFSET 0x3e0
/* DRA752.mpu register offsets */
#define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4
#define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c
#define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4
#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET 0x1bc
#define DRA752_DTEMP_MPU_0_OFFSET 0x1e0
#define DRA752_DTEMP_MPU_1_OFFSET 0x1e4
#define DRA752_DTEMP_MPU_2_OFFSET 0x1e8
#define DRA752_DTEMP_MPU_3_OFFSET 0x1ec
#define DRA752_DTEMP_MPU_4_OFFSET 0x1f0
/* DRA752.dspeve register offsets */
#define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384
#define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394
#define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0
#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET 0x3b0
#define DRA752_DTEMP_DSPEVE_0_OFFSET 0x3bc
#define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0
#define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4
#define DRA752_DTEMP_DSPEVE_3_OFFSET 0x3c8
#define DRA752_DTEMP_DSPEVE_4_OFFSET 0x3cc
/* DRA752.gpu register offsets */
#define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0
#define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150
#define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8
#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET 0x1c0
#define DRA752_DTEMP_GPU_0_OFFSET 0x1f4
#define DRA752_DTEMP_GPU_1_OFFSET 0x1f8
#define DRA752_DTEMP_GPU_2_OFFSET 0x1fc
#define DRA752_DTEMP_GPU_3_OFFSET 0x200
#define DRA752_DTEMP_GPU_4_OFFSET 0x204
/**
* Register bitfields for DRA752
......@@ -114,7 +94,6 @@
*/
/* DRA752.BANDGAP_STATUS_1 */
#define DRA752_BANDGAP_STATUS_1_ALERT_MASK BIT(31)
#define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5)
#define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4)
#define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3)
......@@ -125,10 +104,6 @@
/* DRA752.BANDGAP_CTRL_2 */
#define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22)
#define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21)
#define DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK BIT(19)
#define DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK BIT(18)
#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK BIT(16)
#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK BIT(15)
#define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3)
#define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2)
#define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1)
......@@ -141,17 +116,10 @@
#define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0)
/* DRA752.BANDGAP_CTRL_1 */
#define DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK (0x3 << 30)
#define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27)
#define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23)
#define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22)
#define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21)
#define DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK BIT(20)
#define DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK BIT(19)
#define DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK BIT(18)
#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK BIT(17)
#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK BIT(16)
#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK BIT(15)
#define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5)
#define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4)
#define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3)
......@@ -168,22 +136,6 @@
#define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16)
#define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0)
/* DRA752.BANDGAP_CUMUL_DTEMP_CORE */
#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
/* DRA752.BANDGAP_CUMUL_DTEMP_IVA */
#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_MASK (0xffffffff << 0)
/* DRA752.BANDGAP_CUMUL_DTEMP_MPU */
#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_MASK (0xffffffff << 0)
/* DRA752.BANDGAP_CUMUL_DTEMP_DSPEVE */
#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_MASK (0xffffffff << 0)
/* DRA752.BANDGAP_CUMUL_DTEMP_GPU */
#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_MASK (0xffffffff << 0)
/**
* Temperature limits and thresholds for DRA752
*
......@@ -202,10 +154,6 @@
/* bandgap clock limits */
#define DRA752_GPU_MAX_FREQ 1500000
#define DRA752_GPU_MIN_FREQ 1000000
/* sensor limits */
#define DRA752_GPU_MIN_TEMP -40000
#define DRA752_GPU_MAX_TEMP 125000
#define DRA752_GPU_HYST_VAL 5000
/* interrupts thresholds */
#define DRA752_GPU_T_HOT 800
#define DRA752_GPU_T_COLD 795
......@@ -214,10 +162,6 @@
/* bandgap clock limits */
#define DRA752_MPU_MAX_FREQ 1500000
#define DRA752_MPU_MIN_FREQ 1000000
/* sensor limits */
#define DRA752_MPU_MIN_TEMP -40000
#define DRA752_MPU_MAX_TEMP 125000
#define DRA752_MPU_HYST_VAL 5000
/* interrupts thresholds */
#define DRA752_MPU_T_HOT 800
#define DRA752_MPU_T_COLD 795
......@@ -226,10 +170,6 @@
/* bandgap clock limits */
#define DRA752_CORE_MAX_FREQ 1500000
#define DRA752_CORE_MIN_FREQ 1000000
/* sensor limits */
#define DRA752_CORE_MIN_TEMP -40000
#define DRA752_CORE_MAX_TEMP 125000
#define DRA752_CORE_HYST_VAL 5000
/* interrupts thresholds */
#define DRA752_CORE_T_HOT 800
#define DRA752_CORE_T_COLD 795
......@@ -238,10 +178,6 @@
/* bandgap clock limits */
#define DRA752_DSPEVE_MAX_FREQ 1500000
#define DRA752_DSPEVE_MIN_FREQ 1000000
/* sensor limits */
#define DRA752_DSPEVE_MIN_TEMP -40000
#define DRA752_DSPEVE_MAX_TEMP 125000
#define DRA752_DSPEVE_HYST_VAL 5000
/* interrupts thresholds */
#define DRA752_DSPEVE_T_HOT 800
#define DRA752_DSPEVE_T_COLD 795
......@@ -250,10 +186,6 @@
/* bandgap clock limits */
#define DRA752_IVA_MAX_FREQ 1500000
#define DRA752_IVA_MIN_FREQ 1000000
/* sensor limits */
#define DRA752_IVA_MIN_TEMP -40000
#define DRA752_IVA_MAX_TEMP 125000
#define DRA752_IVA_HYST_VAL 5000
/* interrupts thresholds */
#define DRA752_IVA_T_HOT 800
#define DRA752_IVA_T_COLD 795
......
......@@ -41,24 +41,16 @@ dra752_core_temp_sensor_registers = {
.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK,
.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK,
.bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET,
.ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET,
.ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
.ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
.ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET,
.ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET,
.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
};
......@@ -74,24 +66,16 @@ dra752_iva_temp_sensor_registers = {
.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
.mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
.mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
.mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
.mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK,
.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK,
.bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
.status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET,
.ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET,
.ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
.ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
.ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET,
.ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET,
.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
};
......@@ -107,24 +91,16 @@ dra752_mpu_temp_sensor_registers = {
.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK,
.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK,
.bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET,
.ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET,
.ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
.ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
.ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET,
.ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET,
.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
};
......@@ -140,24 +116,16 @@ dra752_dspeve_temp_sensor_registers = {
.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
.mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
.mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
.mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
.mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK,
.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK,
.bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
.status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET,
.ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET,
.ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
.ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
.ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET,
.ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET,
.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
};
......@@ -173,24 +141,16 @@ dra752_gpu_temp_sensor_registers = {
.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK,
.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK,
.bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK,
.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET,
.ctrl_dtemp_0 = DRA752_DTEMP_GPU_0_OFFSET,
.ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET,
.ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET,
.ctrl_dtemp_3 = DRA752_DTEMP_GPU_3_OFFSET,
.ctrl_dtemp_4 = DRA752_DTEMP_GPU_4_OFFSET,
.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET,
};
......@@ -200,11 +160,6 @@ static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
.t_cold = DRA752_MPU_T_COLD,
.min_freq = DRA752_MPU_MIN_FREQ,
.max_freq = DRA752_MPU_MAX_FREQ,
.max_temp = DRA752_MPU_MAX_TEMP,
.min_temp = DRA752_MPU_MIN_TEMP,
.hyst_val = DRA752_MPU_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/* Thresholds and limits for DRA752 GPU temperature sensor */
......@@ -213,11 +168,6 @@ static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
.t_cold = DRA752_GPU_T_COLD,
.min_freq = DRA752_GPU_MIN_FREQ,
.max_freq = DRA752_GPU_MAX_FREQ,
.max_temp = DRA752_GPU_MAX_TEMP,
.min_temp = DRA752_GPU_MIN_TEMP,
.hyst_val = DRA752_GPU_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/* Thresholds and limits for DRA752 CORE temperature sensor */
......@@ -226,11 +176,6 @@ static struct temp_sensor_data dra752_core_temp_sensor_data = {
.t_cold = DRA752_CORE_T_COLD,
.min_freq = DRA752_CORE_MIN_FREQ,
.max_freq = DRA752_CORE_MAX_FREQ,
.max_temp = DRA752_CORE_MAX_TEMP,
.min_temp = DRA752_CORE_MIN_TEMP,
.hyst_val = DRA752_CORE_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/* Thresholds and limits for DRA752 DSPEVE temperature sensor */
......@@ -239,11 +184,6 @@ static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
.t_cold = DRA752_DSPEVE_T_COLD,
.min_freq = DRA752_DSPEVE_MIN_FREQ,
.max_freq = DRA752_DSPEVE_MAX_FREQ,
.max_temp = DRA752_DSPEVE_MAX_TEMP,
.min_temp = DRA752_DSPEVE_MIN_TEMP,
.hyst_val = DRA752_DSPEVE_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/* Thresholds and limits for DRA752 IVA temperature sensor */
......@@ -252,11 +192,6 @@ static struct temp_sensor_data dra752_iva_temp_sensor_data = {
.t_cold = DRA752_IVA_T_COLD,
.min_freq = DRA752_IVA_MIN_FREQ,
.max_freq = DRA752_IVA_MAX_FREQ,
.max_temp = DRA752_IVA_MAX_TEMP,
.min_temp = DRA752_IVA_MIN_TEMP,
.hyst_val = DRA752_IVA_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/*
......
......@@ -48,9 +48,6 @@ omap34xx_mpu_temp_sensor_registers = {
static struct temp_sensor_data omap34xx_mpu_temp_sensor_data = {
.min_freq = 32768,
.max_freq = 32768,
.max_temp = 125000,
.min_temp = -40000,
.hyst_val = 5000,
};
/*
......@@ -119,9 +116,6 @@ omap36xx_mpu_temp_sensor_registers = {
static struct temp_sensor_data omap36xx_mpu_temp_sensor_data = {
.min_freq = 32768,
.max_freq = 32768,
.max_temp = 125000,
.min_temp = -40000,
.hyst_val = 5000,
};
/*
......
......@@ -42,9 +42,6 @@ omap4430_mpu_temp_sensor_registers = {
static struct temp_sensor_data omap4430_mpu_temp_sensor_data = {
.min_freq = OMAP4430_MIN_FREQ,
.max_freq = OMAP4430_MAX_FREQ,
.max_temp = OMAP4430_MAX_TEMP,
.min_temp = OMAP4430_MIN_TEMP,
.hyst_val = OMAP4430_HYST_VAL,
};
/*
......@@ -121,8 +118,6 @@ omap4460_mpu_temp_sensor_registers = {
.tshut_cold_mask = OMAP4460_TSHUT_COLD_MASK,
.bgap_status = OMAP4460_BGAP_STATUS_OFFSET,
.status_clean_stop_mask = OMAP4460_CLEAN_STOP_MASK,
.status_bgap_alert_mask = OMAP4460_BGAP_ALERT_MASK,
.status_hot_mask = OMAP4460_HOT_FLAG_MASK,
.status_cold_mask = OMAP4460_COLD_FLAG_MASK,
......@@ -137,11 +132,6 @@ static struct temp_sensor_data omap4460_mpu_temp_sensor_data = {
.t_cold = OMAP4460_T_COLD,
.min_freq = OMAP4460_MIN_FREQ,
.max_freq = OMAP4460_MAX_FREQ,
.max_temp = OMAP4460_MAX_TEMP,
.min_temp = OMAP4460_MIN_TEMP,
.hyst_val = OMAP4460_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/*
......
......@@ -73,10 +73,6 @@
/* bandgap clock limits (no control on 4430) */
#define OMAP4430_MAX_FREQ 32768
#define OMAP4430_MIN_FREQ 32768
/* sensor limits */
#define OMAP4430_MIN_TEMP -40000
#define OMAP4430_MAX_TEMP 125000
#define OMAP4430_HYST_VAL 5000
/**
* *** OMAP4460 *** Applicable for OMAP4470
......@@ -143,8 +139,6 @@
#define OMAP4460_TSHUT_COLD_MASK (0x3ff << 0)
/* OMAP4460.BANDGAP_STATUS bits */
#define OMAP4460_CLEAN_STOP_MASK BIT(3)
#define OMAP4460_BGAP_ALERT_MASK BIT(2)
#define OMAP4460_HOT_FLAG_MASK BIT(1)
#define OMAP4460_COLD_FLAG_MASK BIT(0)
......@@ -162,10 +156,6 @@
/* bandgap clock limits */
#define OMAP4460_MAX_FREQ 1500000
#define OMAP4460_MIN_FREQ 1000000
/* sensor limits */
#define OMAP4460_MIN_TEMP -40000
#define OMAP4460_MAX_TEMP 123000
#define OMAP4460_HYST_VAL 5000
/* interrupts thresholds */
#define OMAP4460_TSHUT_HOT 900 /* 122 deg C */
#define OMAP4460_TSHUT_COLD 895 /* 100 deg C */
......
......@@ -38,12 +38,8 @@ omap5430_mpu_temp_sensor_registers = {
.bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET,
.mask_hot_mask = OMAP5430_MASK_HOT_MPU_MASK,
.mask_cold_mask = OMAP5430_MASK_COLD_MPU_MASK,
.mask_sidlemode_mask = OMAP5430_MASK_SIDLEMODE_MASK,
.mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK,
.mask_freeze_mask = OMAP5430_MASK_FREEZE_MPU_MASK,
.mask_clear_mask = OMAP5430_MASK_CLEAR_MPU_MASK,
.mask_clear_accum_mask = OMAP5430_MASK_CLEAR_ACCUM_MPU_MASK,
.bgap_counter = OMAP5430_BGAP_CTRL_OFFSET,
.counter_mask = OMAP5430_COUNTER_MASK,
......@@ -57,17 +53,11 @@ omap5430_mpu_temp_sensor_registers = {
.tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK,
.bgap_status = OMAP5430_BGAP_STATUS_OFFSET,
.status_clean_stop_mask = 0x0,
.status_bgap_alert_mask = OMAP5430_BGAP_ALERT_MASK,
.status_hot_mask = OMAP5430_HOT_MPU_FLAG_MASK,
.status_cold_mask = OMAP5430_COLD_MPU_FLAG_MASK,
.bgap_cumul_dtemp = OMAP5430_BGAP_CUMUL_DTEMP_MPU_OFFSET,
.ctrl_dtemp_0 = OMAP5430_BGAP_DTEMP_MPU_0_OFFSET,
.ctrl_dtemp_1 = OMAP5430_BGAP_DTEMP_MPU_1_OFFSET,
.ctrl_dtemp_2 = OMAP5430_BGAP_DTEMP_MPU_2_OFFSET,
.ctrl_dtemp_3 = OMAP5430_BGAP_DTEMP_MPU_3_OFFSET,
.ctrl_dtemp_4 = OMAP5430_BGAP_DTEMP_MPU_4_OFFSET,
.bgap_efuse = OMAP5430_FUSE_OPP_BGAP_MPU,
};
......@@ -84,11 +74,8 @@ omap5430_gpu_temp_sensor_registers = {
.bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET,
.mask_hot_mask = OMAP5430_MASK_HOT_GPU_MASK,
.mask_cold_mask = OMAP5430_MASK_COLD_GPU_MASK,
.mask_sidlemode_mask = OMAP5430_MASK_SIDLEMODE_MASK,
.mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK,
.mask_freeze_mask = OMAP5430_MASK_FREEZE_GPU_MASK,
.mask_clear_mask = OMAP5430_MASK_CLEAR_GPU_MASK,
.mask_clear_accum_mask = OMAP5430_MASK_CLEAR_ACCUM_GPU_MASK,
.bgap_counter = OMAP5430_BGAP_CTRL_OFFSET,
.counter_mask = OMAP5430_COUNTER_MASK,
......@@ -102,17 +89,11 @@ omap5430_gpu_temp_sensor_registers = {
.tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK,
.bgap_status = OMAP5430_BGAP_STATUS_OFFSET,
.status_clean_stop_mask = 0x0,
.status_bgap_alert_mask = OMAP5430_BGAP_ALERT_MASK,
.status_hot_mask = OMAP5430_HOT_GPU_FLAG_MASK,
.status_cold_mask = OMAP5430_COLD_GPU_FLAG_MASK,
.bgap_cumul_dtemp = OMAP5430_BGAP_CUMUL_DTEMP_GPU_OFFSET,
.ctrl_dtemp_0 = OMAP5430_BGAP_DTEMP_GPU_0_OFFSET,
.ctrl_dtemp_1 = OMAP5430_BGAP_DTEMP_GPU_1_OFFSET,
.ctrl_dtemp_2 = OMAP5430_BGAP_DTEMP_GPU_2_OFFSET,
.ctrl_dtemp_3 = OMAP5430_BGAP_DTEMP_GPU_3_OFFSET,
.ctrl_dtemp_4 = OMAP5430_BGAP_DTEMP_GPU_4_OFFSET,
.bgap_efuse = OMAP5430_FUSE_OPP_BGAP_GPU,
};
......@@ -130,11 +111,8 @@ omap5430_core_temp_sensor_registers = {
.bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET,
.mask_hot_mask = OMAP5430_MASK_HOT_CORE_MASK,
.mask_cold_mask = OMAP5430_MASK_COLD_CORE_MASK,
.mask_sidlemode_mask = OMAP5430_MASK_SIDLEMODE_MASK,
.mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK,
.mask_freeze_mask = OMAP5430_MASK_FREEZE_CORE_MASK,
.mask_clear_mask = OMAP5430_MASK_CLEAR_CORE_MASK,
.mask_clear_accum_mask = OMAP5430_MASK_CLEAR_ACCUM_CORE_MASK,
.bgap_counter = OMAP5430_BGAP_CTRL_OFFSET,
.counter_mask = OMAP5430_COUNTER_MASK,
......@@ -148,17 +126,11 @@ omap5430_core_temp_sensor_registers = {
.tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK,
.bgap_status = OMAP5430_BGAP_STATUS_OFFSET,
.status_clean_stop_mask = 0x0,
.status_bgap_alert_mask = OMAP5430_BGAP_ALERT_MASK,
.status_hot_mask = OMAP5430_HOT_CORE_FLAG_MASK,
.status_cold_mask = OMAP5430_COLD_CORE_FLAG_MASK,
.bgap_cumul_dtemp = OMAP5430_BGAP_CUMUL_DTEMP_CORE_OFFSET,
.ctrl_dtemp_0 = OMAP5430_BGAP_DTEMP_CORE_0_OFFSET,
.ctrl_dtemp_1 = OMAP5430_BGAP_DTEMP_CORE_1_OFFSET,
.ctrl_dtemp_2 = OMAP5430_BGAP_DTEMP_CORE_2_OFFSET,
.ctrl_dtemp_3 = OMAP5430_BGAP_DTEMP_CORE_3_OFFSET,
.ctrl_dtemp_4 = OMAP5430_BGAP_DTEMP_CORE_4_OFFSET,
.bgap_efuse = OMAP5430_FUSE_OPP_BGAP_CORE,
};
......@@ -171,11 +143,6 @@ static struct temp_sensor_data omap5430_mpu_temp_sensor_data = {
.t_cold = OMAP5430_MPU_T_COLD,
.min_freq = OMAP5430_MPU_MIN_FREQ,
.max_freq = OMAP5430_MPU_MAX_FREQ,
.max_temp = OMAP5430_MPU_MAX_TEMP,
.min_temp = OMAP5430_MPU_MIN_TEMP,
.hyst_val = OMAP5430_MPU_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/* Thresholds and limits for OMAP5430 GPU temperature sensor */
......@@ -186,11 +153,6 @@ static struct temp_sensor_data omap5430_gpu_temp_sensor_data = {
.t_cold = OMAP5430_GPU_T_COLD,
.min_freq = OMAP5430_GPU_MIN_FREQ,
.max_freq = OMAP5430_GPU_MAX_FREQ,
.max_temp = OMAP5430_GPU_MAX_TEMP,
.min_temp = OMAP5430_GPU_MIN_TEMP,
.hyst_val = OMAP5430_GPU_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/* Thresholds and limits for OMAP5430 CORE temperature sensor */
......@@ -201,11 +163,6 @@ static struct temp_sensor_data omap5430_core_temp_sensor_data = {
.t_cold = OMAP5430_CORE_T_COLD,
.min_freq = OMAP5430_CORE_MIN_FREQ,
.max_freq = OMAP5430_CORE_MAX_FREQ,
.max_temp = OMAP5430_CORE_MAX_TEMP,
.min_temp = OMAP5430_CORE_MIN_TEMP,
.hyst_val = OMAP5430_CORE_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/*
......@@ -319,8 +276,7 @@ const struct ti_bandgap_data omap5430_data = {
TI_BANDGAP_FEATURE_FREEZE_BIT |
TI_BANDGAP_FEATURE_TALERT |
TI_BANDGAP_FEATURE_COUNTER_DELAY |
TI_BANDGAP_FEATURE_HISTORY_BUFFER |
TI_BANDGAP_FEATURE_ERRATA_813,
TI_BANDGAP_FEATURE_HISTORY_BUFFER,
.fclock_name = "l3instr_ts_gclk_div",
.div_ck_name = "l3instr_ts_gclk_div",
.conv_table = omap5430_adc_to_temp,
......
......@@ -44,36 +44,24 @@
#define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150
#define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8
#define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4
#define OMAP5430_BGAP_CUMUL_DTEMP_GPU_OFFSET 0x1C0
#define OMAP5430_BGAP_DTEMP_GPU_0_OFFSET 0x1F4
#define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8
#define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC
#define OMAP5430_BGAP_DTEMP_GPU_3_OFFSET 0x200
#define OMAP5430_BGAP_DTEMP_GPU_4_OFFSET 0x204
/* OMAP5430.MPU register offsets */
#define OMAP5430_FUSE_OPP_BGAP_MPU 0x4
#define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C
#define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4
#define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0
#define OMAP5430_BGAP_CUMUL_DTEMP_MPU_OFFSET 0x1BC
#define OMAP5430_BGAP_DTEMP_MPU_0_OFFSET 0x1E0
#define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET 0x1E4
#define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET 0x1E8
#define OMAP5430_BGAP_DTEMP_MPU_3_OFFSET 0x1EC
#define OMAP5430_BGAP_DTEMP_MPU_4_OFFSET 0x1F0
/* OMAP5430.MPU register offsets */
#define OMAP5430_FUSE_OPP_BGAP_CORE 0x8
#define OMAP5430_TEMP_SENSOR_CORE_OFFSET 0x154
#define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET 0x1AC
#define OMAP5430_BGAP_TSHUT_CORE_OFFSET 0x1B8
#define OMAP5430_BGAP_CUMUL_DTEMP_CORE_OFFSET 0x1C4
#define OMAP5430_BGAP_DTEMP_CORE_0_OFFSET 0x208
#define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET 0x20C
#define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET 0x210
#define OMAP5430_BGAP_DTEMP_CORE_3_OFFSET 0x214
#define OMAP5430_BGAP_DTEMP_CORE_4_OFFSET 0x218
/* OMAP5430.common register offsets */
#define OMAP5430_BGAP_CTRL_OFFSET 0x1A0
......@@ -94,17 +82,10 @@
#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
/* OMAP5430.BANDGAP_CTRL */
#define OMAP5430_MASK_SIDLEMODE_MASK (0x3 << 30)
#define OMAP5430_MASK_COUNTER_DELAY_MASK (0x7 << 27)
#define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23)
#define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22)
#define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21)
#define OMAP5430_MASK_CLEAR_CORE_MASK BIT(20)
#define OMAP5430_MASK_CLEAR_GPU_MASK BIT(19)
#define OMAP5430_MASK_CLEAR_MPU_MASK BIT(18)
#define OMAP5430_MASK_CLEAR_ACCUM_CORE_MASK BIT(17)
#define OMAP5430_MASK_CLEAR_ACCUM_GPU_MASK BIT(16)
#define OMAP5430_MASK_CLEAR_ACCUM_MPU_MASK BIT(15)
#define OMAP5430_MASK_HOT_CORE_MASK BIT(5)
#define OMAP5430_MASK_COLD_CORE_MASK BIT(4)
#define OMAP5430_MASK_HOT_GPU_MASK BIT(3)
......@@ -123,17 +104,7 @@
#define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16)
#define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0)
/* OMAP5430.BANDGAP_CUMUL_DTEMP_MPU */
#define OMAP5430_CUMUL_DTEMP_MPU_MASK (0xffffffff << 0)
/* OMAP5430.BANDGAP_CUMUL_DTEMP_GPU */
#define OMAP5430_CUMUL_DTEMP_GPU_MASK (0xffffffff << 0)
/* OMAP5430.BANDGAP_CUMUL_DTEMP_CORE */
#define OMAP5430_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
/* OMAP5430.BANDGAP_STATUS */
#define OMAP5430_BGAP_ALERT_MASK BIT(31)
#define OMAP5430_HOT_CORE_FLAG_MASK BIT(5)
#define OMAP5430_COLD_CORE_FLAG_MASK BIT(4)
#define OMAP5430_HOT_GPU_FLAG_MASK BIT(3)
......@@ -159,10 +130,6 @@
/* bandgap clock limits */
#define OMAP5430_GPU_MAX_FREQ 1500000
#define OMAP5430_GPU_MIN_FREQ 1000000
/* sensor limits */
#define OMAP5430_GPU_MIN_TEMP -40000
#define OMAP5430_GPU_MAX_TEMP 125000
#define OMAP5430_GPU_HYST_VAL 5000
/* interrupts thresholds */
#define OMAP5430_GPU_TSHUT_HOT 915
#define OMAP5430_GPU_TSHUT_COLD 900
......@@ -173,10 +140,6 @@
/* bandgap clock limits */
#define OMAP5430_MPU_MAX_FREQ 1500000
#define OMAP5430_MPU_MIN_FREQ 1000000
/* sensor limits */
#define OMAP5430_MPU_MIN_TEMP -40000
#define OMAP5430_MPU_MAX_TEMP 125000
#define OMAP5430_MPU_HYST_VAL 5000
/* interrupts thresholds */
#define OMAP5430_MPU_TSHUT_HOT 915
#define OMAP5430_MPU_TSHUT_COLD 900
......@@ -187,10 +150,6 @@
/* bandgap clock limits */
#define OMAP5430_CORE_MAX_FREQ 1500000
#define OMAP5430_CORE_MIN_FREQ 1000000
/* sensor limits */
#define OMAP5430_CORE_MIN_TEMP -40000
#define OMAP5430_CORE_MAX_TEMP 125000
#define OMAP5430_CORE_HYST_VAL 5000
/* interrupts thresholds */
#define OMAP5430_CORE_TSHUT_HOT 915
#define OMAP5430_CORE_TSHUT_COLD 900
......
This diff is collapsed.
......@@ -78,11 +78,8 @@
* @bgap_mask_ctrl: BANDGAP_MASK_CTRL register offset
* @mask_hot_mask: mask to bandgap_mask_ctrl.mask_hot
* @mask_cold_mask: mask to bandgap_mask_ctrl.mask_cold
* @mask_sidlemode_mask: mask to bandgap_mask_ctrl.mask_sidlemode
* @mask_counter_delay_mask: mask to bandgap_mask_ctrl.mask_counter_delay
* @mask_freeze_mask: mask to bandgap_mask_ctrl.mask_free
* @mask_clear_mask: mask to bandgap_mask_ctrl.mask_clear
* @mask_clear_accum_mask: mask to bandgap_mask_ctrl.mask_clear_accum
* @bgap_mode_ctrl: BANDGAP_MODE_CTRL register offset
* @mode_ctrl_mask: mask to bandgap_mode_ctrl.mode_ctrl
* @bgap_counter: BANDGAP_COUNTER register offset
......@@ -91,21 +88,13 @@
* @threshold_thot_mask: mask to bandgap_threhold.thot
* @threshold_tcold_mask: mask to bandgap_threhold.tcold
* @tshut_threshold: TSHUT_THRESHOLD register offset (TSHUT thresholds)
* @tshut_efuse_mask: mask to tshut_threshold.tshut_efuse
* @tshut_efuse_shift: shift to tshut_threshold.tshut_efuse
* @tshut_hot_mask: mask to tshut_threhold.thot
* @tshut_cold_mask: mask to tshut_threhold.thot
* @bgap_status: BANDGAP_STATUS register offset
* @status_clean_stop_mask: mask to bandgap_status.clean_stop
* @status_bgap_alert_mask: mask to bandgap_status.bandgap_alert
* @status_hot_mask: mask to bandgap_status.hot
* @status_cold_mask: mask to bandgap_status.cold
* @bgap_cumul_dtemp: BANDGAP_CUMUL_DTEMP register offset
* @ctrl_dtemp_0: CTRL_DTEMP0 register offset
* @ctrl_dtemp_1: CTRL_DTEMP1 register offset
* @ctrl_dtemp_2: CTRL_DTEMP2 register offset
* @ctrl_dtemp_3: CTRL_DTEMP3 register offset
* @ctrl_dtemp_4: CTRL_DTEMP4 register offset
* @bgap_efuse: BANDGAP_EFUSE register offset
*
* The register offsets and bitfields might change across
......@@ -121,17 +110,14 @@ struct temp_sensor_registers {
u32 temp_sensor_ctrl;
u32 bgap_tempsoff_mask;
u32 bgap_soc_mask;
u32 bgap_eocz_mask; /* not used: but needs revisit */
u32 bgap_eocz_mask;
u32 bgap_dtemp_mask;
u32 bgap_mask_ctrl;
u32 mask_hot_mask;
u32 mask_cold_mask;
u32 mask_sidlemode_mask; /* not used: but may be needed for pm */
u32 mask_counter_delay_mask;
u32 mask_freeze_mask;
u32 mask_clear_mask; /* not used: but needed for trending */
u32 mask_clear_accum_mask; /* not used: but needed for trending */
u32 bgap_mode_ctrl;
u32 mode_ctrl_mask;
......@@ -144,23 +130,15 @@ struct temp_sensor_registers {
u32 threshold_tcold_mask;
u32 tshut_threshold;
u32 tshut_efuse_mask; /* not used */
u32 tshut_efuse_shift; /* not used */
u32 tshut_hot_mask;
u32 tshut_cold_mask;
u32 bgap_status;
u32 status_clean_stop_mask; /* not used: but needed for trending */
u32 status_bgap_alert_mask; /* not used */
u32 status_hot_mask;
u32 status_cold_mask;
u32 bgap_cumul_dtemp; /* not used: but needed for trending */
u32 ctrl_dtemp_0; /* not used: but needed for trending */
u32 ctrl_dtemp_1; /* not used: but needed for trending */
u32 ctrl_dtemp_2; /* not used: but needed for trending */
u32 ctrl_dtemp_3; /* not used: but needed for trending */
u32 ctrl_dtemp_4; /* not used: but needed for trending */
u32 ctrl_dtemp_1;
u32 ctrl_dtemp_2;
u32 bgap_efuse;
};
......@@ -172,11 +150,6 @@ struct temp_sensor_registers {
* @t_cold: temperature to trigger a thermal alert (low initial value)
* @min_freq: sensor minimum clock rate
* @max_freq: sensor maximum clock rate
* @max_temp: sensor maximum temperature
* @min_temp: sensor minimum temperature
* @hyst_val: temperature hysteresis considered while converting ADC values
* @update_int1: update interval
* @update_int2: update interval
*
* This data structure will hold the required thresholds and temperature limits
* for a specific temperature sensor, like shutdown temperature, alert
......@@ -189,11 +162,6 @@ struct temp_sensor_data {
u32 t_cold;
u32 min_freq;
u32 max_freq;
int max_temp;
int min_temp;
int hyst_val;
u32 update_int1; /* not used */
u32 update_int2; /* not used */
};
struct ti_bandgap_data;
......@@ -316,8 +284,6 @@ struct ti_temp_sensor {
*
* TI_BANDGAP_FEATURE_ERRATA_814 - used to workaorund when the bandgap device
* has Errata 814
* TI_BANDGAP_FEATURE_ERRATA_813 - used to workaorund when the bandgap device
* has Errata 813
* TI_BANDGAP_FEATURE_UNRELIABLE - used when the sensor readings are too
* inaccurate.
* TI_BANDGAP_HAS(b, f) - macro to check if a bandgap device is capable of a
......@@ -334,8 +300,7 @@ struct ti_temp_sensor {
#define TI_BANDGAP_FEATURE_COUNTER_DELAY BIT(8)
#define TI_BANDGAP_FEATURE_HISTORY_BUFFER BIT(9)
#define TI_BANDGAP_FEATURE_ERRATA_814 BIT(10)
#define TI_BANDGAP_FEATURE_ERRATA_813 BIT(11)
#define TI_BANDGAP_FEATURE_UNRELIABLE BIT(12)
#define TI_BANDGAP_FEATURE_UNRELIABLE BIT(11)
#define TI_BANDGAP_HAS(b, f) \
((b)->conf->features & TI_BANDGAP_FEATURE_ ## f)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment