Commit d0df9a2c authored by Archit Taneja's avatar Archit Taneja Committed by Tomi Valkeinen

OMAPDSS: DISPC: Revert to older DISPC Smart Standby mechanism for OMAP5

DISPC on OMAP5 has a more optimised mechanism of asserting Mstandby to achieve
more power savings when DISPC is configured in Smart Standby mode. This
mechanism leads to underflows when multiple DISPC pipes are enabled.

There is a register field which can let us revert to the older mechanism of
asserting Mstandby. Configure this field to prevent underflows.
Signed-off-by: default avatarArchit Taneja <archit@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent c35eeb2e
...@@ -87,6 +87,9 @@ struct dispc_features { ...@@ -87,6 +87,9 @@ struct dispc_features {
/* no DISPC_IRQ_FRAMEDONETV on this SoC */ /* no DISPC_IRQ_FRAMEDONETV on this SoC */
bool no_framedone_tv:1; bool no_framedone_tv:1;
/* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
bool mstandby_workaround:1;
}; };
#define DISPC_MAX_NR_FIFOS 5 #define DISPC_MAX_NR_FIFOS 5
...@@ -3490,6 +3493,9 @@ static void _omap_dispc_initial_config(void) ...@@ -3490,6 +3493,9 @@ static void _omap_dispc_initial_config(void)
dispc_configure_burst_sizes(); dispc_configure_burst_sizes();
dispc_ovl_enable_zorder_planes(); dispc_ovl_enable_zorder_planes();
if (dispc.feat->mstandby_workaround)
REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
} }
static const struct dispc_features omap24xx_dispc_feats __initconst = { static const struct dispc_features omap24xx_dispc_feats __initconst = {
...@@ -3584,6 +3590,7 @@ static const struct dispc_features omap54xx_dispc_feats __initconst = { ...@@ -3584,6 +3590,7 @@ static const struct dispc_features omap54xx_dispc_feats __initconst = {
.calc_core_clk = calc_core_clk_44xx, .calc_core_clk = calc_core_clk_44xx,
.num_fifos = 5, .num_fifos = 5,
.gfx_fifo_workaround = true, .gfx_fifo_workaround = true,
.mstandby_workaround = true,
}; };
static int __init dispc_init_features(struct platform_device *pdev) static int __init dispc_init_features(struct platform_device *pdev)
......
...@@ -39,6 +39,7 @@ ...@@ -39,6 +39,7 @@
#define DISPC_GLOBAL_BUFFER 0x0800 #define DISPC_GLOBAL_BUFFER 0x0800
#define DISPC_CONTROL3 0x0848 #define DISPC_CONTROL3 0x0848
#define DISPC_CONFIG3 0x084C #define DISPC_CONFIG3 0x084C
#define DISPC_MSTANDBY_CTRL 0x0858
/* DISPC overlay registers */ /* DISPC overlay registers */
#define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
......
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