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Commit d1edf2cd authored by Tom Rini's avatar Tom Rini
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PPC32: In some cases we need to make all pages _PAGE_COHERENT. 

Controll this via the cpu_table flags since it's a requirement
in some CPU and host bridge combinations.
From: Adrian Cox <adrian@humboldt.co.uk>
parent 2379c3f2
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Inline Side-by-side
Showing with 50 additions and 6 deletions
arch/ppc/kernel/cputable.c
View file @ d1edf2cd
......@@ -53,10 +53,19 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
#define PPC_FEATURE_ALTIVEC_COMP 0
#endif
/* We need to mark all pages as being coherent if we're SMP or we
* have a 754x and an MPC107 host bridge. */
#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
#else
#define CPU_FTR_COMMON 0
#endif
struct cpu_spec cpu_specs[] = {
#if CLASSIC_PPC
{ /* 601 */
0xffff0000, 0x00010000, "601",
CPU_FTR_COMMON |
CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
COMMON_PPC | PPC_FEATURE_601_INSTR | PPC_FEATURE_UNIFIED_CACHE,
32, 32,
......@@ -64,6 +73,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 603 */
0xffff0000, 0x00030000, "603",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_CAN_NAP,
COMMON_PPC,
......@@ -72,6 +82,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 603e */
0xffff0000, 0x00060000, "603e",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_CAN_NAP,
COMMON_PPC,
......@@ -80,6 +91,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 603ev */
0xffff0000, 0x00070000, "603ev",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_CAN_NAP,
COMMON_PPC,
......@@ -88,6 +100,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 604 */
0xffff0000, 0x00040000, "604",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
CPU_FTR_HPTE_TABLE,
COMMON_PPC,
......@@ -96,6 +109,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 604e */
0xfffff000, 0x00090000, "604e",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
CPU_FTR_HPTE_TABLE,
COMMON_PPC,
......@@ -104,6 +118,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 604r */
0xffff0000, 0x00090000, "604r",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
CPU_FTR_HPTE_TABLE,
COMMON_PPC,
......@@ -112,6 +127,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 604ev */
0xffff0000, 0x000a0000, "604ev",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
CPU_FTR_HPTE_TABLE,
COMMON_PPC,
......@@ -120,6 +136,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 740/750 (0x4202, don't support TAU ?) */
0xffffffff, 0x00084202, "740/750",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
COMMON_PPC,
......@@ -128,6 +145,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 745/755 */
0xfffff000, 0x00083000, "745/755",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
COMMON_PPC,
......@@ -136,6 +154,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 750CX (80100 and 8010x?) */
0xfffffff0, 0x00080100, "750CX",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
COMMON_PPC,
......@@ -144,6 +163,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 750CX (82201 and 82202) */
0xfffffff0, 0x00082200, "750CX",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
COMMON_PPC,
......@@ -152,6 +172,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 750CXe (82214) */
0xfffffff0, 0x00082210, "750CXe",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
COMMON_PPC,
......@@ -160,6 +181,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 750FX rev 1.x */
0xffffff00, 0x70000100, "750FX",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
......@@ -169,6 +191,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 750FX rev 2.0 must disable HID0[DPM] */
0xffffffff, 0x70000200, "750FX",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
CPU_FTR_NO_DPM,
......@@ -178,6 +201,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 750FX (All revs except 2.0) */
0xffff0000, 0x70000000, "750FX",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
......@@ -188,6 +212,7 @@ struct cpu_spec cpu_specs[] = {
{ /* 740/750 (L2CR bit need fixup for 740) */
0xffff0000, 0x00080000, "740/750",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
COMMON_PPC,
......@@ -196,6 +221,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 7400 rev 1.1 ? (no TAU) */
0xffffffff, 0x000c1101, "7400 (1.1)",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_CAN_NAP,
......@@ -205,6 +231,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 7400 */
0xffff0000, 0x000c0000, "7400",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_CAN_NAP,
......@@ -214,6 +241,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 7410 */
0xffff0000, 0x800c0000, "7410",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_CAN_NAP,
......@@ -223,6 +251,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 7450 2.0 - no doze/nap */
0xffffffff, 0x80000200, "7450",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450,
......@@ -232,6 +261,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 7450 2.1 */
0xffffffff, 0x80000201, "7450",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
......@@ -242,6 +272,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 7450 2.3 and newer */
0xffff0000, 0x80000000, "7450",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR,
......@@ -251,6 +282,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 7455 rev 1.x */
0xffffff00, 0x80010100, "7455",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS,
......@@ -260,6 +292,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 7455 rev 2.0 */
0xffffffff, 0x80010200, "7455",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
......@@ -270,6 +303,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 7455 others */
0xffff0000, 0x80010000, "7455",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
......@@ -280,6 +314,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 7457 */
0xffff0000, 0x80020000, "7457",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
......@@ -290,6 +325,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 82xx (8240, 8245, 8260 are all 603e cores) */
0x7fff0000, 0x00810000, "82xx",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB,
COMMON_PPC,
32, 32,
......@@ -297,6 +333,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* default match, we assume split I/D cache & TB (non-601)... */
0x00000000, 0x00000000, "(generic PPC)",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
COMMON_PPC,
32, 32,
......@@ -306,6 +343,7 @@ struct cpu_spec cpu_specs[] = {
#ifdef CONFIG_PPC64BRIDGE
{ /* Power3 */
0xffff0000, 0x00400000, "Power3 (630)",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
COMMON_PPC | PPC_FEATURE_64,
128, 128,
......@@ -313,6 +351,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* Power3+ */
0xffff0000, 0x00410000, "Power3 (630+)",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
COMMON_PPC | PPC_FEATURE_64,
128, 128,
......@@ -320,6 +359,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* I-star */
0xffff0000, 0x00360000, "I-star",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
COMMON_PPC | PPC_FEATURE_64,
128, 128,
......@@ -327,6 +367,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* S-star */
0xffff0000, 0x00370000, "S-star",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
COMMON_PPC | PPC_FEATURE_64,
128, 128,
......@@ -336,6 +377,7 @@ struct cpu_spec cpu_specs[] = {
#ifdef CONFIG_POWER4
{ /* Power4 */
0xffff0000, 0x00350000, "Power4",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
COMMON_PPC | PPC_FEATURE_64,
128, 128,
......@@ -343,6 +385,7 @@ struct cpu_spec cpu_specs[] = {
},
{ /* PPC970 */
0xffff0000, 0x00390000, "PPC970",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP,
COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
......@@ -480,7 +523,7 @@ struct cpu_spec cpu_specs[] = {
#if !CLASSIC_PPC
{ /* default match */
0x00000000, 0x00000000, "(generic PPC)",
0,
CPU_FTR_COMMON,
PPC_FEATURE_32,
32, 32,
0,
......
arch/ppc/mm/hashtable.S
View file @ d1edf2cd
......@@ -346,9 +346,9 @@ _GLOBAL(create_hpte)
rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
ori r8,r8,0xe14 /* clear out reserved bits and M */
andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */
#ifdef CONFIG_SMP
BEGIN_FTR_SECTION
ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */
#endif
END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
/* Construct the high word of the PPC-style PTE (r5) */
#ifndef CONFIG_PPC64BRIDGE
......
arch/ppc/mm/ppc_mmu.c
View file @ d1edf2cd
......@@ -137,10 +137,10 @@ void __init setbat(int index, unsigned long virt, unsigned long phys,
int wimgxpp;
union ubat *bat = BATS[index];
#ifdef CONFIG_SMP
if ((flags & _PAGE_NO_CACHE) == 0)
if (((flags & _PAGE_NO_CACHE) == 0) &&
(cur_cpu_spec[0]->cpu_features & CPU_FTR_NEED_COHERENT))
flags |= _PAGE_COHERENT;
#endif
bl = (size >> 17) - 1;
if (PVR_VER(mfspr(PVR)) != 1) {
/* 603, 604, etc. */
......
include/asm-ppc/cputable.h
View file @ d1edf2cd
......@@ -75,6 +75,7 @@ extern struct cpu_spec *cur_cpu_spec[];
#define CPU_FTR_DUAL_PLL_750FX 0x00004000
#define CPU_FTR_NO_DPM 0x00008000
#define CPU_FTR_HAS_HIGH_BATS 0x00010000
#define CPU_FTR_NEED_COHERENT 0x00020000
#ifdef __ASSEMBLY__
......
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