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Commit d3caa060 authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Felix Fietkau
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mt76x0: phy: simplify rf configuration routines 

Simplify mt76x0_phy_vco_cal and mt76x0_phy_set_chan_rf_params
routines using mt76x0_rf_wr, mt76x0_rf_set and mt76x0_rf_clear
helper routines. Moreover over get rid of magic numbers
Signed-off-by: default avatarLorenzo Bianconi <lorenzo.bianconi@redhat.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 9c410782
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Inline Side-by-side
Showing with 106 additions and 144 deletions
drivers/net/wireless/mediatek/mt76/mt76x0/phy.c
View file @ d3caa060
...@@ -49,11 +49,11 @@ mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value) ...@@ -49,11 +49,11 @@ mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value)
} }
mt76_wr(dev, MT_RF_CSR_CFG, mt76_wr(dev, MT_RF_CSR_CFG,
FIELD_PREP(MT_RF_CSR_CFG_DATA, value) | FIELD_PREP(MT_RF_CSR_CFG_DATA, value) |
FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |
FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) | FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) |
MT_RF_CSR_CFG_WR | MT_RF_CSR_CFG_WR |
MT_RF_CSR_CFG_KICK); MT_RF_CSR_CFG_KICK);
trace_mt76x0_rf_write(&dev->mt76, bank, offset, value); trace_mt76x0_rf_write(&dev->mt76, bank, offset, value);
out: out:
mutex_unlock(&dev->phy_mutex); mutex_unlock(&dev->phy_mutex);
...@@ -86,9 +86,9 @@ static int mt76x0_rf_csr_rr(struct mt76x02_dev *dev, u32 offset) ...@@ -86,9 +86,9 @@ static int mt76x0_rf_csr_rr(struct mt76x02_dev *dev, u32 offset)
goto out; goto out;
mt76_wr(dev, MT_RF_CSR_CFG, mt76_wr(dev, MT_RF_CSR_CFG,
FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |
FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) | FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) |
MT_RF_CSR_CFG_KICK); MT_RF_CSR_CFG_KICK);
if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))
goto out; goto out;
...@@ -168,13 +168,11 @@ mt76x0_rf_set(struct mt76x02_dev *dev, u32 offset, u8 val) ...@@ -168,13 +168,11 @@ mt76x0_rf_set(struct mt76x02_dev *dev, u32 offset, u8 val)
return mt76x0_rf_rmw(dev, offset, 0, val); return mt76x0_rf_rmw(dev, offset, 0, val);
} }
#if 0
static int static int
rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask) mt76x0_rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask)
{ {
return mt76x0_rf_rmw(dev, offset, mask, 0); return mt76x0_rf_rmw(dev, offset, mask, 0);
} }
#endif
static void static void
mt76x0_phy_rf_csr_wr_rp(struct mt76x02_dev *dev, mt76x0_phy_rf_csr_wr_rp(struct mt76x02_dev *dev,
...@@ -222,46 +220,31 @@ static void mt76x0_phy_vco_cal(struct mt76x02_dev *dev, u8 channel) ...@@ -222,46 +220,31 @@ static void mt76x0_phy_vco_cal(struct mt76x02_dev *dev, u8 channel)
if ((val & 0x70) != 0x30) if ((val & 0x70) != 0x30)
return; return;
/* /* closed loop calibarion - B0.R06.[3:0]: 1001 */
* Calibration Mode - Open loop, closed loop, and amplitude: mt76x0_rf_rmw(dev, MT_RF(0, 6), MT_RF_VCO_BP_CLOSE_LOOP_MASK,
* B0.R06.[0]: 1 MT_RF_VCO_BP_CLOSE_LOOP | BIT(0));
* B0.R06.[3:1] bp_close_code: 100
* B0.R05.[7:0] bp_open_code: 0x0
* B0.R04.[2:0] cal_bits: 000
* B0.R03.[2:0] startup_time: 011
* B0.R03.[6:4] settle_time:
* 80MHz channel: 110
* 40MHz channel: 101
* 20MHz channel: 100
*/
val = mt76x0_rf_rr(dev, MT_RF(0, 6));
val &= ~0xf;
val |= 0x09;
mt76x0_rf_wr(dev, MT_RF(0, 6), val);
val = mt76x0_rf_rr(dev, MT_RF(0, 5)); /* open loop calibration - B0.R05.[7:0]: 0x0 */
if (val != 0) mt76x0_rf_wr(dev, MT_RF(0, 5), 0x0);
mt76x0_rf_wr(dev, MT_RF(0, 5), 0x0);
val = mt76x0_rf_rr(dev, MT_RF(0, 4)); /* caliration mask - B0.R04.[2:0]: 000 */
val &= ~0x07; mt76x0_rf_clear(dev, MT_RF(0, 4), MT_RF_VCO_CAL_MASK);
mt76x0_rf_wr(dev, MT_RF(0, 4), val);
/* startup time - B0.R03.[2:0] startup_time: 011 */
val = mt76x0_rf_rr(dev, MT_RF(0, 3)); mt76x0_rf_rmw(dev, MT_RF(0, 3), MT_RF_START_TIME_MASK,
val &= ~0x77; MT_RF_START_TIME);
if (channel == 1 || channel == 7 || channel == 9 || channel >= 13) {
val |= 0x63; /* settle_time - B0.R03.[6:4] */
} else if (channel == 3 || channel == 4 || channel == 10) { if (channel == 3 || channel == 4 || channel == 10)
val |= 0x53; val = 0x50;
} else if (channel == 2 || channel == 5 || channel == 6 || else if (channel == 2 || channel == 5 || channel == 6 ||
channel == 8 || channel == 11 || channel == 12) { channel == 8 || channel == 11 || channel == 12)
val |= 0x43; val = 0x40;
} else { else
WARN(1, "Unknown channel %u\n", channel); val = 0x60;
return; mt76x0_rf_rmw(dev, MT_RF(0, 3), MT_RF_SETTLE_TIME_MASK, val);
}
mt76x0_rf_wr(dev, MT_RF(0, 3), val);
/* enable vco */
mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7)); mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7));
msleep(2); msleep(2);
...@@ -297,18 +280,17 @@ mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band) ...@@ -297,18 +280,17 @@ mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band)
static void static void
mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_band) mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_band)
{ {
const struct mt76x0_freq_item *freq_item;
u16 rf_band = rf_bw_band & 0xff00; u16 rf_band = rf_bw_band & 0xff00;
u16 rf_bw = rf_bw_band & 0x00ff; u16 rf_bw = rf_bw_band & 0x00ff;
enum nl80211_band band; enum nl80211_band band;
bool b_sdm = false;
u32 mac_reg; u32 mac_reg;
u8 rf_val;
int i; int i;
bool bSDM = false;
const struct mt76x0_freq_item *freq_item;
for (i = 0; i < ARRAY_SIZE(mt76x0_sdm_channel); i++) { for (i = 0; i < ARRAY_SIZE(mt76x0_sdm_channel); i++) {
if (channel == mt76x0_sdm_channel[i]) { if (channel == mt76x0_sdm_channel[i]) {
bSDM = true; b_sdm = true;
break; break;
} }
} }
...@@ -317,7 +299,7 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban ...@@ -317,7 +299,7 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
if (channel == mt76x0_frequency_plan[i].channel) { if (channel == mt76x0_frequency_plan[i].channel) {
rf_band = mt76x0_frequency_plan[i].band; rf_band = mt76x0_frequency_plan[i].band;
if (bSDM) if (b_sdm)
freq_item = &(mt76x0_sdm_frequency_plan[i]); freq_item = &(mt76x0_sdm_frequency_plan[i]);
else else
freq_item = &(mt76x0_frequency_plan[i]); freq_item = &(mt76x0_frequency_plan[i]);
...@@ -328,97 +310,73 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban ...@@ -328,97 +310,73 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
mt76x0_rf_wr(dev, MT_RF(0, 34), freq_item->pllR34); mt76x0_rf_wr(dev, MT_RF(0, 34), freq_item->pllR34);
mt76x0_rf_wr(dev, MT_RF(0, 33), freq_item->pllR33); mt76x0_rf_wr(dev, MT_RF(0, 33), freq_item->pllR33);
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 32)); mt76x0_rf_rmw(dev, MT_RF(0, 32), 0xe0,
rf_val &= ~0xE0; freq_item->pllR32_b7b5);
rf_val |= freq_item->pllR32_b7b5;
mt76x0_rf_wr(dev, MT_RF(0, 32), rf_val);
/* R32<4:0> pll_den: (Denomina - 8) */ /* R32<4:0> pll_den: (Denomina - 8) */
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 32)); mt76x0_rf_rmw(dev, MT_RF(0, 32), MT_RF_PLL_DEN_MASK,
rf_val &= ~0x1F; freq_item->pllR32_b4b0);
rf_val |= freq_item->pllR32_b4b0;
mt76x0_rf_wr(dev, MT_RF(0, 32), rf_val);
/* R31<7:5> */ /* R31<7:5> */
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 31)); mt76x0_rf_rmw(dev, MT_RF(0, 31), 0xe0,
rf_val &= ~0xE0; freq_item->pllR31_b7b5);
rf_val |= freq_item->pllR31_b7b5;
mt76x0_rf_wr(dev, MT_RF(0, 31), rf_val);
/* R31<4:0> pll_k(Nominator) */ /* R31<4:0> pll_k(Nominator) */
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 31)); mt76x0_rf_rmw(dev, MT_RF(0, 31), MT_RF_PLL_K_MASK,
rf_val &= ~0x1F; freq_item->pllR31_b4b0);
rf_val |= freq_item->pllR31_b4b0;
mt76x0_rf_wr(dev, MT_RF(0, 31), rf_val);
/* R30<7> sdm_reset_n */ /* R30<7> sdm_reset_n */
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 30)); if (b_sdm) {
rf_val &= ~0x80; mt76x0_rf_clear(dev, MT_RF(0, 30),
if (bSDM) { MT_RF_SDM_RESET_MASK);
mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val); mt76x0_rf_set(dev, MT_RF(0, 30),
rf_val |= 0x80; MT_RF_SDM_RESET_MASK);
mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
} else { } else {
rf_val |= freq_item->pllR30_b7; mt76x0_rf_rmw(dev, MT_RF(0, 30),
mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val); MT_RF_SDM_RESET_MASK,
freq_item->pllR30_b7);
} }
/* R30<6:2> sdmmash_prbs,sin */ /* R30<6:2> sdmmash_prbs,sin */
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 30)); mt76x0_rf_rmw(dev, MT_RF(0, 30),
rf_val &= ~0x7C; MT_RF_SDM_MASH_PRBS_MASK,
rf_val |= freq_item->pllR30_b6b2; freq_item->pllR30_b6b2);
mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
/* R30<1> sdm_bp */ /* R30<1> sdm_bp */
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 30)); mt76x0_rf_rmw(dev, MT_RF(0, 30), MT_RF_SDM_BP_MASK,
rf_val &= ~0x02; freq_item->pllR30_b1 << 1);
rf_val |= (freq_item->pllR30_b1 << 1);
mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
/* R30<0> R29<7:0> (hex) pll_n */ /* R30<0> R29<7:0> (hex) pll_n */
rf_val = freq_item->pll_n & 0x00FF; mt76x0_rf_wr(dev, MT_RF(0, 29),
mt76x0_rf_wr(dev, MT_RF(0, 29), rf_val); freq_item->pll_n & 0xff);
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 30)); mt76x0_rf_rmw(dev, MT_RF(0, 30), 0x1,
rf_val &= ~0x1; (freq_item->pll_n >> 8) & 0x1);
rf_val |= ((freq_item->pll_n >> 8) & 0x0001);
mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
/* R28<7:6> isi_iso */ /* R28<7:6> isi_iso */
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 28)); mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_ISI_ISO_MASK,
rf_val &= ~0xC0; freq_item->pllR28_b7b6);
rf_val |= freq_item->pllR28_b7b6;
mt76x0_rf_wr(dev, MT_RF(0, 28), rf_val);
/* R28<5:4> pfd_dly */ /* R28<5:4> pfd_dly */
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 28)); mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_PFD_DLY_MASK,
rf_val &= ~0x30; freq_item->pllR28_b5b4);
rf_val |= freq_item->pllR28_b5b4;
mt76x0_rf_wr(dev, MT_RF(0, 28), rf_val);
/* R28<3:2> clksel option */ /* R28<3:2> clksel option */
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 28)); mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_CLK_SEL_MASK,
rf_val &= ~0x0C; freq_item->pllR28_b3b2);
rf_val |= freq_item->pllR28_b3b2;
mt76x0_rf_wr(dev, MT_RF(0, 28), rf_val);
/* R28<1:0> R27<7:0> R26<7:0> (hex) sdm_k */ /* R28<1:0> R27<7:0> R26<7:0> (hex) sdm_k */
rf_val = freq_item->pll_sdm_k & 0x000000FF; mt76x0_rf_wr(dev, MT_RF(0, 26),
mt76x0_rf_wr(dev, MT_RF(0, 26), rf_val); freq_item->pll_sdm_k & 0xff);
mt76x0_rf_wr(dev, MT_RF(0, 27),
rf_val = ((freq_item->pll_sdm_k >> 8) & 0x000000FF); (freq_item->pll_sdm_k >> 8) & 0xff);
mt76x0_rf_wr(dev, MT_RF(0, 27), rf_val);
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 28)); mt76x0_rf_rmw(dev, MT_RF(0, 28), 0x3,
rf_val &= ~0x3; (freq_item->pll_sdm_k >> 16) & 0x3);
rf_val |= ((freq_item->pll_sdm_k >> 16) & 0x0003);
mt76x0_rf_wr(dev, MT_RF(0, 28), rf_val);
/* R24<1:0> xo_div */ /* R24<1:0> xo_div */
rf_val = mt76x0_rf_rr(dev, MT_RF(0, 24)); mt76x0_rf_rmw(dev, MT_RF(0, 24), MT_RF_XO_DIV_MASK,
rf_val &= ~0x3; freq_item->pllR24_b1b0);
rf_val |= freq_item->pllR24_b1b0;
mt76x0_rf_wr(dev, MT_RF(0, 24), rf_val);
break; break;
} }
...@@ -445,9 +403,7 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban ...@@ -445,9 +403,7 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
} }
} }
mac_reg = mt76_rr(dev, MT_RF_MISC); mt76_clear(dev, MT_RF_MISC, 0xc);
mac_reg &= ~0xC; /* Clear 0x518[3:2] */
mt76_wr(dev, MT_RF_MISC, mac_reg);
band = (rf_band & RF_G_BAND) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; band = (rf_band & RF_G_BAND) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
if (mt76x02_ext_pa_enabled(dev, band)) { if (mt76x02_ext_pa_enabled(dev, band)) {
...@@ -456,15 +412,10 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban ...@@ -456,15 +412,10 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
[2]1'b1: enable external A band PA, 1'b0: disable external A band PA [2]1'b1: enable external A band PA, 1'b0: disable external A band PA
[3]1'b1: enable external G band PA, 1'b0: disable external G band PA [3]1'b1: enable external G band PA, 1'b0: disable external G band PA
*/ */
if (rf_band & RF_A_BAND) { if (rf_band & RF_A_BAND)
mac_reg = mt76_rr(dev, MT_RF_MISC); mt76_set(dev, MT_RF_MISC, BIT(2));
mac_reg |= 0x4; else
mt76_wr(dev, MT_RF_MISC, mac_reg); mt76_set(dev, MT_RF_MISC, BIT(3));
} else {
mac_reg = mt76_rr(dev, MT_RF_MISC);
mac_reg |= 0x8;
mt76_wr(dev, MT_RF_MISC, mac_reg);
}
/* External PA */ /* External PA */
for (i = 0; i < ARRAY_SIZE(mt76x0_rf_ext_pa_tab); i++) for (i = 0; i < ARRAY_SIZE(mt76x0_rf_ext_pa_tab); i++)
...@@ -710,12 +661,10 @@ int mt76x0_phy_set_channel(struct mt76x02_dev *dev, ...@@ -710,12 +661,10 @@ int mt76x0_phy_set_channel(struct mt76x02_dev *dev,
mt76x0_phy_set_chan_rf_params(dev, channel, rf_bw_band); mt76x0_phy_set_chan_rf_params(dev, channel, rf_bw_band);
/* set Japan Tx filter at channel 14 */ /* set Japan Tx filter at channel 14 */
val = mt76_rr(dev, MT_BBP(CORE, 1));
if (channel == 14) if (channel == 14)
val |= 0x20; mt76_set(dev, MT_BBP(CORE, 1), 0x20);
else else
val &= ~0x20; mt76_clear(dev, MT_BBP(CORE, 1), 0x20);
mt76_wr(dev, MT_BBP(CORE, 1), val);
mt76x0_read_rx_gain(dev); mt76x0_read_rx_gain(dev);
mt76x0_phy_set_chan_bbp_params(dev, rf_bw_band); mt76x0_phy_set_chan_bbp_params(dev, rf_bw_band);
...@@ -903,20 +852,16 @@ static void mt76x0_phy_rf_init(struct mt76x02_dev *dev) ...@@ -903,20 +852,16 @@ static void mt76x0_phy_rf_init(struct mt76x02_dev *dev)
min_t(u8, dev->cal.rx.freq_offset, 0xbf)); min_t(u8, dev->cal.rx.freq_offset, 0xbf));
val = mt76x0_rf_rr(dev, MT_RF(0, 22)); val = mt76x0_rf_rr(dev, MT_RF(0, 22));
/* /* Reset procedure DAC during power-up:
Reset the DAC (Set B0.R73<7>=1, then set B0.R73<7>=0, and then set B0.R73<7>) during power up. * - set B0.R73<7>
* - clear B0.R73<7>
* - set B0.R73<7>
*/ */
val = mt76x0_rf_rr(dev, MT_RF(0, 73)); mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7));
val |= 0x80; mt76x0_rf_clear(dev, MT_RF(0, 73), BIT(7));
mt76x0_rf_wr(dev, MT_RF(0, 73), val); mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7));
val &= ~0x80;
mt76x0_rf_wr(dev, MT_RF(0, 73), val);
val |= 0x80;
mt76x0_rf_wr(dev, MT_RF(0, 73), val);
/* /* vcocal_en: initiate VCO calibration (reset after completion)) */
vcocal_en (initiate VCO calibration (reset after completion)) - It should be at the end of RF configuration.
*/
mt76x0_rf_set(dev, MT_RF(0, 4), 0x80); mt76x0_rf_set(dev, MT_RF(0, 4), 0x80);
} }
......
drivers/net/wireless/mediatek/mt76/mt76x0/phy.h
View file @ d3caa060
...@@ -30,6 +30,23 @@ ...@@ -30,6 +30,23 @@
#define MT_RF_BANK(offset) (offset >> 16) #define MT_RF_BANK(offset) (offset >> 16)
#define MT_RF_REG(offset) (offset & 0xff) #define MT_RF_REG(offset) (offset & 0xff)
#define MT_RF_VCO_BP_CLOSE_LOOP BIT(3)
#define MT_RF_VCO_BP_CLOSE_LOOP_MASK GENMASK(3, 0)
#define MT_RF_VCO_CAL_MASK GENMASK(2, 0)
#define MT_RF_START_TIME 0x3
#define MT_RF_START_TIME_MASK GENMASK(2, 0)
#define MT_RF_SETTLE_TIME_MASK GENMASK(6, 4)
#define MT_RF_PLL_DEN_MASK GENMASK(4, 0)
#define MT_RF_PLL_K_MASK GENMASK(4, 0)
#define MT_RF_SDM_RESET_MASK BIT(7)
#define MT_RF_SDM_MASH_PRBS_MASK GENMASK(6, 2)
#define MT_RF_SDM_BP_MASK BIT(1)
#define MT_RF_ISI_ISO_MASK GENMASK(7, 6)
#define MT_RF_PFD_DLY_MASK GENMASK(5, 4)
#define MT_RF_CLK_SEL_MASK GENMASK(3, 2)
#define MT_RF_XO_DIV_MASK GENMASK(1, 0)
struct mt76x0_bbp_switch_item { struct mt76x0_bbp_switch_item {
u16 bw_band; u16 bw_band;
struct mt76_reg_pair reg_pair; struct mt76_reg_pair reg_pair;
......
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