Commit d4032ccc authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'samsung-soc-4.10-2' of...

Merge tag 'samsung-soc-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into fixes

Samsung mach/soc update for v4.10:

1. Minor cleanup in smp_operations.
2. Another step in switching s3c24xx to new DMA API.
3. Drop fixed requirement for HZ=200 on Samsung platforms.

* tag 'samsung-soc-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: Drop fixed 200 Hz timer requirement from Samsung platforms
  ARM: S3C24XX: Add DMA slave maps for remaining s3c24xx SoCs
  ARM: EXYNOS: Remove smp_init_cpus hook from platsmp.c
parents cb2cc436 da6b21e9
...@@ -1502,8 +1502,7 @@ source kernel/Kconfig.preempt ...@@ -1502,8 +1502,7 @@ source kernel/Kconfig.preempt
config HZ_FIXED config HZ_FIXED
int int
default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ default 200 if ARCH_EBSA110
ARCH_S5PV210 || ARCH_EXYNOS4
default 128 if SOC_AT91RM9200 default 128 if SOC_AT91RM9200
default 0 default 0
......
...@@ -385,36 +385,6 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -385,36 +385,6 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
return pen_release != -1 ? ret : 0; return pen_release != -1 ? ret : 0;
} }
/*
* Initialise the CPU possible map early - this describes the CPUs
* which may be present or become present in the system.
*/
static void __init exynos_smp_init_cpus(void)
{
void __iomem *scu_base = scu_base_addr();
unsigned int i, ncores;
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
else
/*
* CPU Nodes are passed thru DT and set_cpu_possible
* is set by "arm_dt_init_cpu_maps".
*/
return;
/* sanity check */
if (ncores > nr_cpu_ids) {
pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
ncores, nr_cpu_ids);
ncores = nr_cpu_ids;
}
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
}
static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
{ {
int i; int i;
...@@ -479,7 +449,6 @@ static void exynos_cpu_die(unsigned int cpu) ...@@ -479,7 +449,6 @@ static void exynos_cpu_die(unsigned int cpu)
#endif /* CONFIG_HOTPLUG_CPU */ #endif /* CONFIG_HOTPLUG_CPU */
const struct smp_operations exynos_smp_ops __initconst = { const struct smp_operations exynos_smp_ops __initconst = {
.smp_init_cpus = exynos_smp_init_cpus,
.smp_prepare_cpus = exynos_smp_prepare_cpus, .smp_prepare_cpus = exynos_smp_prepare_cpus,
.smp_secondary_init = exynos_secondary_init, .smp_secondary_init = exynos_secondary_init,
.smp_boot_secondary = exynos_boot_secondary, .smp_boot_secondary = exynos_boot_secondary,
......
...@@ -345,10 +345,40 @@ static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = { ...@@ -345,10 +345,40 @@ static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
}; };
static const struct dma_slave_map s3c2410_dma_slave_map[] = {
{ "s3c2410-sdi", "rx-tx", (void *)DMACH_SDI },
{ "s3c2410-spi.0", "rx", (void *)DMACH_SPI0_RX },
{ "s3c2410-spi.0", "tx", (void *)DMACH_SPI0_TX },
{ "s3c2410-spi.1", "rx", (void *)DMACH_SPI1_RX },
{ "s3c2410-spi.1", "tx", (void *)DMACH_SPI1_TX },
/*
* The DMA request source[1] (DMACH_UARTx_SRC2) are
* not used in the UART driver.
*/
{ "s3c2410-uart.0", "rx", (void *)DMACH_UART0 },
{ "s3c2410-uart.0", "tx", (void *)DMACH_UART0 },
{ "s3c2410-uart.1", "rx", (void *)DMACH_UART1 },
{ "s3c2410-uart.1", "tx", (void *)DMACH_UART1 },
{ "s3c2410-uart.2", "rx", (void *)DMACH_UART2 },
{ "s3c2410-uart.2", "tx", (void *)DMACH_UART2 },
{ "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
{ "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
{ "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
{ "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
{ "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
{ "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
{ "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
{ "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
{ "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
{ "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
};
static struct s3c24xx_dma_platdata s3c2410_dma_platdata = { static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
.num_phy_channels = 4, .num_phy_channels = 4,
.channels = s3c2410_dma_channels, .channels = s3c2410_dma_channels,
.num_channels = DMACH_MAX, .num_channels = DMACH_MAX,
.slave_map = s3c2410_dma_slave_map,
.slavecnt = ARRAY_SIZE(s3c2410_dma_slave_map),
}; };
struct platform_device s3c2410_device_dma = { struct platform_device s3c2410_device_dma = {
...@@ -388,10 +418,36 @@ static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = { ...@@ -388,10 +418,36 @@ static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 }, [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
}; };
static const struct dma_slave_map s3c2412_dma_slave_map[] = {
{ "s3c2412-sdi", "rx-tx", (void *)DMACH_SDI },
{ "s3c2412-spi.0", "rx", (void *)DMACH_SPI0_RX },
{ "s3c2412-spi.0", "tx", (void *)DMACH_SPI0_TX },
{ "s3c2412-spi.1", "rx", (void *)DMACH_SPI1_RX },
{ "s3c2412-spi.1", "tx", (void *)DMACH_SPI1_TX },
{ "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
{ "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
{ "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
{ "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
{ "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
{ "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
{ "s3c2412-iis", "rx", (void *)DMACH_I2S_IN },
{ "s3c2412-iis", "tx", (void *)DMACH_I2S_OUT },
{ "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
{ "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
{ "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
{ "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
{ "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
{ "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
{ "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
{ "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
};
static struct s3c24xx_dma_platdata s3c2412_dma_platdata = { static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
.num_phy_channels = 4, .num_phy_channels = 4,
.channels = s3c2412_dma_channels, .channels = s3c2412_dma_channels,
.num_channels = DMACH_MAX, .num_channels = DMACH_MAX,
.slave_map = s3c2412_dma_slave_map,
.slavecnt = ARRAY_SIZE(s3c2412_dma_slave_map),
}; };
struct platform_device s3c2412_device_dma = { struct platform_device s3c2412_device_dma = {
...@@ -534,10 +590,30 @@ static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = { ...@@ -534,10 +590,30 @@ static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
[DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 }, [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
}; };
static const struct dma_slave_map s3c2443_dma_slave_map[] = {
{ "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
{ "s3c2443-spi.0", "rx", (void *)DMACH_SPI0_RX },
{ "s3c2443-spi.0", "tx", (void *)DMACH_SPI0_TX },
{ "s3c2443-spi.1", "rx", (void *)DMACH_SPI1_RX },
{ "s3c2443-spi.1", "tx", (void *)DMACH_SPI1_TX },
{ "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
{ "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
{ "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
{ "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
{ "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
{ "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
{ "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
{ "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
{ "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
{ "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
};
static struct s3c24xx_dma_platdata s3c2443_dma_platdata = { static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
.num_phy_channels = 6, .num_phy_channels = 6,
.channels = s3c2443_dma_channels, .channels = s3c2443_dma_channels,
.num_channels = DMACH_MAX, .num_channels = DMACH_MAX,
.slave_map = s3c2443_dma_slave_map,
.slavecnt = ARRAY_SIZE(s3c2443_dma_slave_map),
}; };
struct platform_device s3c2443_device_dma = { struct platform_device s3c2443_device_dma = {
......
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