Commit d50f4630 authored by Pankaj Bansal's avatar Pankaj Bansal Committed by Marc Kleine-Budde

arm: dts: Remove p1010-flexcan compatible from imx series dts

The flexcan driver has been modified to check for big-endian dts
property for be read/write to flexcan registers/mb.

An exception to this rule is powerpc P1010RDB, which is always
big-endian, even if big-endian is not present in dts. This is
checked using p1010-flexcan compatible in dts.

Therefore, remove p1010-flexcan compatible from imx series dts,
as their flexcan core is little endian.
Signed-off-by: default avatarPankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent c8ae67fe
...@@ -122,7 +122,7 @@ i2c3: i2c@43f84000 { ...@@ -122,7 +122,7 @@ i2c3: i2c@43f84000 {
}; };
can1: can@43f88000 { can1: can@43f88000 {
compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan"; compatible = "fsl,imx25-flexcan";
reg = <0x43f88000 0x4000>; reg = <0x43f88000 0x4000>;
interrupts = <43>; interrupts = <43>;
clocks = <&clks 75>, <&clks 75>; clocks = <&clks 75>, <&clks 75>;
...@@ -131,7 +131,7 @@ can1: can@43f88000 { ...@@ -131,7 +131,7 @@ can1: can@43f88000 {
}; };
can2: can@43f8c000 { can2: can@43f8c000 {
compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan"; compatible = "fsl,imx25-flexcan";
reg = <0x43f8c000 0x4000>; reg = <0x43f8c000 0x4000>;
interrupts = <44>; interrupts = <44>;
clocks = <&clks 76>, <&clks 76>; clocks = <&clks 76>, <&clks 76>;
......
...@@ -1038,7 +1038,7 @@ lcdif: lcdif@80030000 { ...@@ -1038,7 +1038,7 @@ lcdif: lcdif@80030000 {
}; };
can0: can@80032000 { can0: can@80032000 {
compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; compatible = "fsl,imx28-flexcan";
reg = <0x80032000 0x2000>; reg = <0x80032000 0x2000>;
interrupts = <8>; interrupts = <8>;
clocks = <&clks 58>, <&clks 58>; clocks = <&clks 58>, <&clks 58>;
...@@ -1047,7 +1047,7 @@ can0: can@80032000 { ...@@ -1047,7 +1047,7 @@ can0: can@80032000 {
}; };
can1: can@80034000 { can1: can@80034000 {
compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; compatible = "fsl,imx28-flexcan";
reg = <0x80034000 0x2000>; reg = <0x80034000 0x2000>;
interrupts = <9>; interrupts = <9>;
clocks = <&clks 59>, <&clks 59>; clocks = <&clks 59>, <&clks 59>;
......
...@@ -303,7 +303,7 @@ wdog: wdog@53fdc000 { ...@@ -303,7 +303,7 @@ wdog: wdog@53fdc000 {
}; };
can1: can@53fe4000 { can1: can@53fe4000 {
compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan"; compatible = "fsl,imx35-flexcan";
reg = <0x53fe4000 0x1000>; reg = <0x53fe4000 0x1000>;
clocks = <&clks 33>, <&clks 33>; clocks = <&clks 33>, <&clks 33>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
...@@ -312,7 +312,7 @@ can1: can@53fe4000 { ...@@ -312,7 +312,7 @@ can1: can@53fe4000 {
}; };
can2: can@53fe8000 { can2: can@53fe8000 {
compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan"; compatible = "fsl,imx35-flexcan";
reg = <0x53fe8000 0x1000>; reg = <0x53fe8000 0x1000>;
clocks = <&clks 34>, <&clks 34>; clocks = <&clks 34>, <&clks 34>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
......
...@@ -545,7 +545,7 @@ uart2: serial@53fc0000 { ...@@ -545,7 +545,7 @@ uart2: serial@53fc0000 {
}; };
can1: can@53fc8000 { can1: can@53fc8000 {
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; compatible = "fsl,imx53-flexcan";
reg = <0x53fc8000 0x4000>; reg = <0x53fc8000 0x4000>;
interrupts = <82>; interrupts = <82>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
...@@ -555,7 +555,7 @@ can1: can@53fc8000 { ...@@ -555,7 +555,7 @@ can1: can@53fc8000 {
}; };
can2: can@53fcc000 { can2: can@53fcc000 {
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; compatible = "fsl,imx53-flexcan";
reg = <0x53fcc000 0x4000>; reg = <0x53fcc000 0x4000>;
interrupts = <83>; interrupts = <83>;
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
......
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