From d53442e94db0f214989287aa7cd3806cffd1d0b3 Mon Sep 17 00:00:00 2001
From: Peter De Schrijver <pdeschrijver@nvidia.com>
Date: Thu, 6 Jun 2013 13:47:29 +0300
Subject: [PATCH] clk: tegra: override bits for Tegra114 PLLM
Define override bits for Tegra114 PLLM.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed up trivial merge conflict]
---
drivers/clk/tegra/clk-tegra114.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 435b2879b92c..7fe36eaa993b 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -251,6 +251,10 @@
#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
#define CLK_SOURCE_EMC 0x19c
+/* PLLM override registers */
+#define PMC_PLLM_WB0_OVERRIDE 0x1dc
+#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
+
static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
static void __iomem *clk_base;
@@ -395,10 +399,13 @@ static struct tegra_clk_pll_params pll_c3_params = {
static struct div_nmp pllm_nmp = {
.divm_shift = 0,
.divm_width = 8,
+ .override_divm_shift = 0,
.divn_shift = 8,
.divn_width = 8,
+ .override_divn_shift = 8,
.divp_shift = 20,
.divp_width = 1,
+ .override_divp_shift = 27,
};
static struct pdiv_map pllm_p[] = {
@@ -431,6 +438,8 @@ static struct tegra_clk_pll_params pll_m_params = {
.max_p = 2,
.pdiv_tohw = pllm_p,
.div_nmp = &pllm_nmp,
+ .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
+ .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
};
static struct div_nmp pllp_nmp = {
--
2.30.9