Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
linux
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
nexedi
linux
Commits
d7a9d45d
Commit
d7a9d45d
authored
Jan 23, 2020
by
Tony Lindgren
Browse files
Options
Browse Files
Download
Plain Diff
Merge branch 'omap-for-v5.6/ti-sysc-dt-cam' into omap-for-v5.6/dt
parents
6bcc319f
1a209516
Changes
20
Hide whitespace changes
Inline
Side-by-side
Showing
20 changed files
with
559 additions
and
34 deletions
+559
-34
Documentation/devicetree/bindings/clock/ti-clkctrl.txt
Documentation/devicetree/bindings/clock/ti-clkctrl.txt
+8
-3
Documentation/devicetree/bindings/clock/ti/dra7-atl.txt
Documentation/devicetree/bindings/clock/ti/dra7-atl.txt
+2
-2
arch/arm/boot/dts/am437x-sk-evm.dts
arch/arm/boot/dts/am437x-sk-evm.dts
+26
-1
arch/arm/boot/dts/am43x-epos-evm.dts
arch/arm/boot/dts/am43x-epos-evm.dts
+22
-1
arch/arm/boot/dts/am43xx-clocks.dtsi
arch/arm/boot/dts/am43xx-clocks.dtsi
+54
-0
arch/arm/boot/dts/dra7-evm-common.dtsi
arch/arm/boot/dts/dra7-evm-common.dtsi
+1
-1
arch/arm/boot/dts/dra7-l4.dtsi
arch/arm/boot/dts/dra7-l4.dtsi
+62
-9
arch/arm/boot/dts/dra72-evm-common.dtsi
arch/arm/boot/dts/dra72-evm-common.dtsi
+32
-1
arch/arm/boot/dts/dra72x.dtsi
arch/arm/boot/dts/dra72x.dtsi
+42
-0
arch/arm/boot/dts/dra76-evm.dts
arch/arm/boot/dts/dra76-evm.dts
+35
-0
arch/arm/boot/dts/dra76x.dtsi
arch/arm/boot/dts/dra76x.dtsi
+42
-0
arch/arm/boot/dts/dra7xx-clocks.dtsi
arch/arm/boot/dts/dra7xx-clocks.dtsi
+44
-2
arch/arm/mach-omap2/clockdomains7xx_data.c
arch/arm/mach-omap2/clockdomains7xx_data.c
+1
-1
drivers/clk/ti/clk-54xx.c
drivers/clk/ti/clk-54xx.c
+15
-0
drivers/clk/ti/clk-7xx.c
drivers/clk/ti/clk-7xx.c
+61
-1
drivers/clk/ti/clk.c
drivers/clk/ti/clk.c
+3
-1
drivers/clk/ti/clkctrl.c
drivers/clk/ti/clkctrl.c
+85
-11
include/dt-bindings/clock/dra7.h
include/dt-bindings/clock/dra7.h
+23
-0
include/dt-bindings/clock/omap5.h
include/dt-bindings/clock/omap5.h
+1
-0
include/dt-bindings/clock/ti-dra7-atl.h
include/dt-bindings/clock/ti-dra7-atl.h
+0
-0
No files found.
Documentation/devicetree/bindings/clock/ti-clkctrl.txt
View file @
d7a9d45d
...
@@ -16,18 +16,23 @@ For more information, please see the Linux clock framework binding at
...
@@ -16,18 +16,23 @@ For more information, please see the Linux clock framework binding at
Documentation/devicetree/bindings/clock/clock-bindings.txt.
Documentation/devicetree/bindings/clock/clock-bindings.txt.
Required properties :
Required properties :
- compatible : shall be "ti,clkctrl"
- compatible : shall be "ti,clkctrl" or a clock domain specific name:
"ti,clkctrl-l4-cfg"
"ti,clkctrl-l4-per"
"ti,clkctrl-l4-secure"
"ti,clkctrl-l4-wkup"
- #clock-cells : shall contain 2 with the first entry being the instance
- #clock-cells : shall contain 2 with the first entry being the instance
offset from the clock domain base and the second being the
offset from the clock domain base and the second being the
clock index
clock index
- reg : clock registers
Example: Clock controller node on omap 4430:
Example: Clock controller node on omap 4430:
&cm2 {
&cm2 {
l4per: cm@1400 {
l4per: cm@1400 {
cm_l4per@0 {
cm_l4per@0 {
cm_l4per_clkctrl: clk@20 {
cm_l4per_clkctrl: cl
oc
k@20 {
compatible = "ti,clkctrl";
compatible = "ti,clkctrl
-l4-per", "ti,clkctrl
";
reg = <0x20 0x1b0>;
reg = <0x20 0x1b0>;
#clock-cells = <2>;
#clock-cells = <2>;
};
};
...
...
Documentation/devicetree/bindings/clock/ti/dra7-atl.txt
View file @
d7a9d45d
...
@@ -43,7 +43,7 @@ Configuration of ATL instances:
...
@@ -43,7 +43,7 @@ Configuration of ATL instances:
- aws : Audio word select signal selection
- aws : Audio word select signal selection
};
};
For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include
For valid word select signals, see the dt-bindings/cl
oc
k/ti-dra7-atl.h include
file.
file.
Examples:
Examples:
...
@@ -83,7 +83,7 @@ atl: atl@4843c000 {
...
@@ -83,7 +83,7 @@ atl: atl@4843c000 {
clock-names = "fck";
clock-names = "fck";
};
};
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/cl
oc
k/ti-dra7-atl.h>
&atl {
&atl {
...
...
arch/arm/boot/dts/am437x-sk-evm.dts
View file @
d7a9d45d
...
@@ -272,6 +272,12 @@ AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
...
@@ -272,6 +272,12 @@ AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
>;
>;
};
};
clkout1_pin
:
pinmux_clkout1_pin
{
pinctrl
-
single
,
pins
=
<
0x270
(
PIN_OUTPUT_PULLDOWN
|
MUX_MODE3
)
/*
XDMA_EVENT_INTR0
/
CLKOUT1
*/
>;
};
cpsw_default
:
cpsw_default
{
cpsw_default
:
cpsw_default
{
pinctrl
-
single
,
pins
=
<
pinctrl
-
single
,
pins
=
<
/*
Slave
1
*/
/*
Slave
1
*/
...
@@ -593,6 +599,25 @@ &i2c1 {
...
@@ -593,6 +599,25 @@ &i2c1 {
pinctrl
-
0
=
<&
i2c1_pins
>;
pinctrl
-
0
=
<&
i2c1_pins
>;
clock
-
frequency
=
<
400000
>;
clock
-
frequency
=
<
400000
>;
ov2659
@
30
{
compatible
=
"ovti,ov2659"
;
reg
=
<
0x30
>;
pinctrl
-
names
=
"default"
;
pinctrl
-
0
=
<&
clkout1_pin
>;
clocks
=
<&
clkout1_mux_ck
>;
clock
-
names
=
"xvclk"
;
assigned
-
clocks
=
<&
clkout1_mux_ck
>;
assigned
-
clock
-
parents
=
<&
clkout1_osc_div_ck
>;
port
{
ov2659_1
:
endpoint
{
remote
-
endpoint
=
<&
vpfe0_ep
>;
link
-
frequencies
=
/
bits
/
64
<
70000000
>;
};
};
};
edt
-
ft5306
@
38
{
edt
-
ft5306
@
38
{
status
=
"okay"
;
status
=
"okay"
;
compatible
=
"edt,edt-ft5306"
,
"edt,edt-ft5x06"
;
compatible
=
"edt,edt-ft5306"
,
"edt,edt-ft5x06"
;
...
@@ -877,7 +902,7 @@ &vpfe0 {
...
@@ -877,7 +902,7 @@ &vpfe0 {
/*
Camera
port
*/
/*
Camera
port
*/
port
{
port
{
vpfe0_ep
:
endpoint
{
vpfe0_ep
:
endpoint
{
/*
remote
-
endpoint
=
<&
sensor
>;
add
once
we
have
it
*/
remote
-
endpoint
=
<&
ov2659_1
>;
ti
,
am437x
-
vpfe
-
interface
=
<
0
>;
ti
,
am437x
-
vpfe
-
interface
=
<
0
>;
bus
-
width
=
<
8
>;
bus
-
width
=
<
8
>;
hsync
-
active
=
<
0
>;
hsync
-
active
=
<
0
>;
...
...
arch/arm/boot/dts/am43x-epos-evm.dts
View file @
d7a9d45d
...
@@ -145,6 +145,12 @@ sound0_master: simple-audio-card,codec {
...
@@ -145,6 +145,12 @@ sound0_master: simple-audio-card,codec {
system
-
clock
-
frequency
=
<
12000000
>;
system
-
clock
-
frequency
=
<
12000000
>;
};
};
};
};
audio_mstrclk
:
clock
{
compatible
=
"fixed-clock"
;
#
clock
-
cells
=
<
0
>;
clock
-
frequency
=
<
12000000
>;
};
};
};
&
am43xx_pinmux
{
&
am43xx_pinmux
{
...
@@ -696,6 +702,21 @@ tlv320aic3111: tlv320aic3111@18 {
...
@@ -696,6 +702,21 @@ tlv320aic3111: tlv320aic3111@18 {
IOVDD
-
supply
=
<&
dcdc4
>;
/*
V3_3D
->
DCDC4
*/
IOVDD
-
supply
=
<&
dcdc4
>;
/*
V3_3D
->
DCDC4
*/
DVDD
-
supply
=
<&
ldo1
>;
/*
V1_8AUD
->
V1_8D
->
LDO1
*/
DVDD
-
supply
=
<&
ldo1
>;
/*
V1_8AUD
->
V1_8D
->
LDO1
*/
};
};
ov2659
@
30
{
compatible
=
"ovti,ov2659"
;
reg
=
<
0x30
>;
clocks
=
<&
audio_mstrclk
>;
clock
-
names
=
"xvclk"
;
port
{
ov2659_1
:
endpoint
{
remote
-
endpoint
=
<&
vpfe1_ep
>;
link
-
frequencies
=
/
bits
/
64
<
70000000
>;
};
};
};
};
};
&
i2c2
{
&
i2c2
{
...
@@ -962,7 +983,7 @@ &vpfe1 {
...
@@ -962,7 +983,7 @@ &vpfe1 {
port
{
port
{
vpfe1_ep
:
endpoint
{
vpfe1_ep
:
endpoint
{
/*
remote
-
endpoint
=
<&
sensor
>;
add
once
we
have
it
*/
remote
-
endpoint
=
<&
ov2659_1
>;
ti
,
am437x
-
vpfe
-
interface
=
<
0
>;
ti
,
am437x
-
vpfe
-
interface
=
<
0
>;
bus
-
width
=
<
8
>;
bus
-
width
=
<
8
>;
hsync
-
active
=
<
0
>;
hsync
-
active
=
<
0
>;
...
...
arch/arm/boot/dts/am43xx-clocks.dtsi
View file @
d7a9d45d
...
@@ -704,6 +704,60 @@ usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
...
@@ -704,6 +704,60 @@ usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
ti,bit-shift = <8>;
ti,bit-shift = <8>;
reg = <0x2a48>;
reg = <0x2a48>;
};
};
clkout1_osc_div_ck: clkout1-osc-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <20>;
ti,max-div = <4>;
reg = <0x4100>;
};
clkout1_src2_mux_ck: clkout1-src2-mux-ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>;
reg = <0x4100>;
};
clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4100>;
};
clkout1_src2_post_div_ck: clkout1-src2-post-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
ti,index-power-of-two;
reg = <0x4100>;
};
clkout1_mux_ck: clkout1-mux-ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
ti,bit-shift = <16>;
reg = <0x4100>;
};
clkout1_ck: clkout1-ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout1_mux_ck>;
ti,bit-shift = <23>;
reg = <0x4100>;
};
};
};
&prcm {
&prcm {
...
...
arch/arm/boot/dts/dra7-evm-common.dtsi
View file @
d7a9d45d
...
@@ -4,7 +4,7 @@
...
@@ -4,7 +4,7 @@
*/
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/cl
oc
k/ti-dra7-atl.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/input.h>
/ {
/ {
...
...
arch/arm/boot/dts/dra7-l4.dtsi
View file @
d7a9d45d
...
@@ -4166,35 +4166,88 @@ usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
...
@@ -4166,35 +4166,88 @@ usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
};
};
target-module@170000 { /* 0x48970000, ap 21 0a.0 */
target-module@170000 { /* 0x48970000, ap 21 0a.0 */
compatible = "ti,sysc";
compatible = "ti,sysc-omap4", "ti,sysc";
status = "disabled";
reg = <0x170010 0x4>;
reg-names = "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x170000 0x10000>;
ranges = <0x0 0x170000 0x10000>;
status = "disabled";
};
};
target-module@190000 { /* 0x48990000, ap 23 2e.0 */
target-module@190000 { /* 0x48990000, ap 23 2e.0 */
compatible = "ti,sysc";
compatible = "ti,sysc-omap4", "ti,sysc";
status = "disabled";
reg = <0x190010 0x4>;
reg-names = "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x190000 0x10000>;
ranges = <0x0 0x190000 0x10000>;
status = "disabled";
};
};
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
compatible = "ti,sysc";
compatible = "ti,sysc-omap4", "ti,sysc";
status = "disabled";
reg = <0x1b0000 0x4>,
<0x1b0010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1b0000 0x10000>;
ranges = <0x0 0x1b0000 0x10000>;
status = "disabled";
};
};
target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */
target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
compatible = "ti,sysc";
compatible = "ti,sysc-omap4", "ti,sysc";
status = "disabled";
reg = <0x1d0010 0x4>;
reg-names = "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1d0000 0x10000>;
ranges = <0x0 0x1d0000 0x10000>;
vpe: vpe@0 {
compatible = "ti,dra7-vpe";
reg = <0x0000 0x120>,
<0x0700 0x80>,
<0x5700 0x18>,
<0xd000 0x400>;
reg-names = "vpe_top",
"sc",
"csc",
"vpdma";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};
};
};
};
...
...
arch/arm/boot/dts/dra72-evm-common.dtsi
View file @
d7a9d45d
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
#include "dra72x.dtsi"
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/cl
oc
k/ti-dra7-atl.h>
/ {
/ {
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
...
@@ -187,6 +187,12 @@ vmmcwl_fixed: fixedregulator-mmcwl {
...
@@ -187,6 +187,12 @@ vmmcwl_fixed: fixedregulator-mmcwl {
gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
enable-active-high;
};
};
clk_ov5640_fixed: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
};
&dra7_pmx_core {
&dra7_pmx_core {
...
@@ -269,6 +275,23 @@ p1 {
...
@@ -269,6 +275,23 @@ p1 {
line-name = "vin6_sel_s0";
line-name = "vin6_sel_s0";
};
};
};
};
ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&clk_ov5640_fixed>;
clock-names = "xclk";
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2_phy0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
};
&uart1 {
&uart1 {
...
@@ -580,3 +603,11 @@ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
...
@@ -580,3 +603,11 @@ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
&pcie1_rc {
&pcie1_rc {
status = "okay";
status = "okay";
};
};
&csi2_0 {
csi2_phy0: endpoint {
remote-endpoint = <&csi2_cam0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
arch/arm/boot/dts/dra72x.dtsi
View file @
d7a9d45d
...
@@ -17,6 +17,48 @@ pmu {
...
@@ -17,6 +17,48 @@ pmu {
};
};
};
};
&l4_per2 {
target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5b000 0x4>,
<0x5b010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x5b000 0x1000>;
cal: cal@0 {
compatible = "ti,dra72-cal";
reg = <0x0000 0x400>,
<0x0800 0x40>,
<0x0900 0x40>;
reg-names = "cal_top",
"cal_rx_core0",
"cal_rx_core1";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
ti,camerrx-control = <&scm_conf 0xE94>;
ports {
#address-cells = <1>;
#size-cells = <0>;
csi2_0: port@0 {
reg = <0>;
};
csi2_1: port@1 {
reg = <1>;
};
};
};
};
};
&dss {
&dss {
reg = <0x58000000 0x80>,
reg = <0x58000000 0x80>,
<0x58004054 0x4>,
<0x58004054 0x4>,
...
...
arch/arm/boot/dts/dra76-evm.dts
View file @
d7a9d45d
...
@@ -124,6 +124,12 @@ aic_dvdd: fixedregulator-aic_dvdd {
...
@@ -124,6 +124,12 @@ aic_dvdd: fixedregulator-aic_dvdd {
regulator
-
max
-
microvolt
=
<
1800000
>;
regulator
-
max
-
microvolt
=
<
1800000
>;
};
};
clk_ov5640_fixed
:
clock
{
compatible
=
"fixed-clock"
;
#
clock
-
cells
=
<
0
>;
clock
-
frequency
=
<
24000000
>;
};
hdmi0
:
connector
{
hdmi0
:
connector
{
compatible
=
"hdmi-connector"
;
compatible
=
"hdmi-connector"
;
label
=
"hdmi"
;
label
=
"hdmi"
;
...
@@ -366,6 +372,27 @@ tlv320aic3106: tlv320aic3106@19 {
...
@@ -366,6 +372,27 @@ tlv320aic3106: tlv320aic3106@19 {
};
};
};
};
&
i2c5
{
status
=
"okay"
;
clock
-
frequency
=
<
400000
>;
ov5640
@
3
c
{
compatible
=
"ovti,ov5640"
;
reg
=
<
0x3c
>;
clocks
=
<&
clk_ov5640_fixed
>;
clock
-
names
=
"xclk"
;
port
{
csi2_cam0
:
endpoint
{
remote
-
endpoint
=
<&
csi2_phy0
>;
clock
-
lanes
=
<
0
>;
data
-
lanes
=
<
1
2
>;
};
};
};
};
&
cpu0
{
&
cpu0
{
vdd
-
supply
=
<&
buck10_reg
>;
vdd
-
supply
=
<&
buck10_reg
>;
};
};
...
@@ -513,3 +540,11 @@ can-transceiver {
...
@@ -513,3 +540,11 @@ can-transceiver {
max
-
bitrate
=
<
5000000
>;
max
-
bitrate
=
<
5000000
>;
};
};
};
};
&
csi2_0
{
csi2_phy0
:
endpoint
{
remote
-
endpoint
=
<&
csi2_cam0
>;
clock
-
lanes
=
<
0
>;
data
-
lanes
=
<
1
2
>;
};
};
arch/arm/boot/dts/dra76x.dtsi
View file @
d7a9d45d
...
@@ -41,6 +41,48 @@ m_can0: mcan@1a00 {
...
@@ -41,6 +41,48 @@ m_can0: mcan@1a00 {
};
};
&l4_per3 {
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x1b0000 0x4>,
<0x1b0010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1b0000 0x10000>;
cal: cal@0 {
compatible = "ti,dra76-cal";
reg = <0x0000 0x400>,
<0x0800 0x40>,
<0x0900 0x40>;
reg-names = "cal_top",
"cal_rx_core0",
"cal_rx_core1";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
ti,camerrx-control = <&scm_conf 0x6dc>;
ports {
#address-cells = <1>;
#size-cells = <0>;
csi2_0: port@0 {
reg = <0>;
};
csi2_1: port@1 {
reg = <1>;
};
};
};
};
};
/* MCAN interrupts are hard-wired to irqs 67, 68 */
/* MCAN interrupts are hard-wired to irqs 67, 68 */
&crossbar_mpu {
&crossbar_mpu {
ti,irqs-skip = <10 67 68 133 139 140>;
ti,irqs-skip = <10 67 68 133 139 140>;
...
...
arch/arm/boot/dts/dra7xx-clocks.dtsi
View file @
d7a9d45d
...
@@ -1591,10 +1591,10 @@ dsp2_clkctrl: dsp2-clkctrl@20 {
...
@@ -1591,10 +1591,10 @@ dsp2_clkctrl: dsp2-clkctrl@20 {
rtc_cm: rtc-cm@700 {
rtc_cm: rtc-cm@700 {
compatible = "ti,omap4-cm";
compatible = "ti,omap4-cm";
reg = <0x700 0x
10
0>;
reg = <0x700 0x
6
0>;
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <1>;
ranges = <0 0x700 0x
10
0>;
ranges = <0 0x700 0x
6
0>;
rtc_clkctrl: rtc-clkctrl@20 {
rtc_clkctrl: rtc-clkctrl@20 {
compatible = "ti,clkctrl";
compatible = "ti,clkctrl";
...
@@ -1603,6 +1603,20 @@ rtc_clkctrl: rtc-clkctrl@20 {
...
@@ -1603,6 +1603,20 @@ rtc_clkctrl: rtc-clkctrl@20 {
};
};
};
};
vpe_cm: vpe-cm@760 {
compatible = "ti,omap4-cm";
reg = <0x760 0xc>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x760 0xc>;
vpe_clkctrl: vpe-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x0 0xc>;
#clock-cells = <2>;
};
};
};
};
&cm_core {
&cm_core {
...
@@ -1720,6 +1734,20 @@ l3instr_clkctrl: l3instr-clkctrl@20 {
...
@@ -1720,6 +1734,20 @@ l3instr_clkctrl: l3instr-clkctrl@20 {
};
};
};
};
cam_cm: cam-cm@1000 {
compatible = "ti,omap4-cm";
reg = <0x1000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x100>;
cam_clkctrl: cam-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x2c>;
#clock-cells = <2>;
};
};
dss_cm: dss-cm@1100 {
dss_cm: dss-cm@1100 {
compatible = "ti,omap4-cm";
compatible = "ti,omap4-cm";
reg = <0x1100 0x100>;
reg = <0x1100 0x100>;
...
@@ -1734,6 +1762,20 @@ dss_clkctrl: dss-clkctrl@20 {
...
@@ -1734,6 +1762,20 @@ dss_clkctrl: dss-clkctrl@20 {
};
};
};
};
gpu_cm: gpu-cm@1200 {
compatible = "ti,omap4-cm";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1200 0x100>;
gpu_clkctrl: gpu-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
l3init_cm: l3init-cm@1300 {
l3init_cm: l3init-cm@1300 {
compatible = "ti,omap4-cm";
compatible = "ti,omap4-cm";
reg = <0x1300 0x100>;
reg = <0x1300 0x100>;
...
...
arch/arm/mach-omap2/clockdomains7xx_data.c
View file @
d7a9d45d
...
@@ -606,7 +606,7 @@ static struct clockdomain cam_7xx_clkdm = {
...
@@ -606,7 +606,7 @@ static struct clockdomain cam_7xx_clkdm = {
.
dep_bit
=
DRA7XX_CAM_STATDEP_SHIFT
,
.
dep_bit
=
DRA7XX_CAM_STATDEP_SHIFT
,
.
wkdep_srcs
=
cam_wkup_sleep_deps
,
.
wkdep_srcs
=
cam_wkup_sleep_deps
,
.
sleepdep_srcs
=
cam_wkup_sleep_deps
,
.
sleepdep_srcs
=
cam_wkup_sleep_deps
,
.
flags
=
CLKDM_CAN_
HWSUP_
SWSUP
,
.
flags
=
CLKDM_CAN_SWSUP
,
};
};
static
struct
clockdomain
l4per_7xx_clkdm
=
{
static
struct
clockdomain
l4per_7xx_clkdm
=
{
...
...
drivers/clk/ti/clk-54xx.c
View file @
d7a9d45d
...
@@ -35,6 +35,20 @@ static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst =
...
@@ -35,6 +35,20 @@ static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst =
{
0
},
{
0
},
};
};
static
const
char
*
const
omap5_aess_fclk_parents
[]
__initconst
=
{
"abe_clk"
,
NULL
,
};
static
const
struct
omap_clkctrl_div_data
omap5_aess_fclk_data
__initconst
=
{
.
max_div
=
2
,
};
static
const
struct
omap_clkctrl_bit_data
omap5_aess_bit_data
[]
__initconst
=
{
{
24
,
TI_CLK_DIVIDER
,
omap5_aess_fclk_parents
,
&
omap5_aess_fclk_data
},
{
0
},
};
static
const
char
*
const
omap5_dmic_gfclk_parents
[]
__initconst
=
{
static
const
char
*
const
omap5_dmic_gfclk_parents
[]
__initconst
=
{
"abe_cm:clk:0018:26"
,
"abe_cm:clk:0018:26"
,
"pad_clks_ck"
,
"pad_clks_ck"
,
...
@@ -122,6 +136,7 @@ static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst =
...
@@ -122,6 +136,7 @@ static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst =
static
const
struct
omap_clkctrl_reg_data
omap5_abe_clkctrl_regs
[]
__initconst
=
{
static
const
struct
omap_clkctrl_reg_data
omap5_abe_clkctrl_regs
[]
__initconst
=
{
{
OMAP5_L4_ABE_CLKCTRL
,
NULL
,
0
,
"abe_iclk"
},
{
OMAP5_L4_ABE_CLKCTRL
,
NULL
,
0
,
"abe_iclk"
},
{
OMAP5_AESS_CLKCTRL
,
omap5_aess_bit_data
,
CLKF_SW_SUP
,
"abe_cm:clk:0008:24"
},
{
OMAP5_MCPDM_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
"pad_clks_ck"
},
{
OMAP5_MCPDM_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
"pad_clks_ck"
},
{
OMAP5_DMIC_CLKCTRL
,
omap5_dmic_bit_data
,
CLKF_SW_SUP
,
"abe_cm:clk:0018:24"
},
{
OMAP5_DMIC_CLKCTRL
,
omap5_dmic_bit_data
,
CLKF_SW_SUP
,
"abe_cm:clk:0018:24"
},
{
OMAP5_MCBSP1_CLKCTRL
,
omap5_mcbsp1_bit_data
,
CLKF_SW_SUP
,
"abe_cm:clk:0028:24"
},
{
OMAP5_MCBSP1_CLKCTRL
,
omap5_mcbsp1_bit_data
,
CLKF_SW_SUP
,
"abe_cm:clk:0028:24"
},
...
...
drivers/clk/ti/clk-7xx.c
View file @
d7a9d45d
...
@@ -146,6 +146,29 @@ static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst =
...
@@ -146,6 +146,29 @@ static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst =
{
0
},
{
0
},
};
};
static
const
char
*
const
dra7_cam_gfclk_mux_parents
[]
__initconst
=
{
"l3_iclk_div"
,
"core_iss_main_clk"
,
NULL
,
};
static
const
struct
omap_clkctrl_bit_data
dra7_cam_bit_data
[]
__initconst
=
{
{
24
,
TI_CLK_MUX
,
dra7_cam_gfclk_mux_parents
,
NULL
},
{
0
},
};
static
const
struct
omap_clkctrl_reg_data
dra7_cam_clkctrl_regs
[]
__initconst
=
{
{
DRA7_CAM_VIP1_CLKCTRL
,
dra7_cam_bit_data
,
CLKF_HW_SUP
,
"l3_iclk_div"
},
{
DRA7_CAM_VIP2_CLKCTRL
,
dra7_cam_bit_data
,
CLKF_HW_SUP
,
"l3_iclk_div"
},
{
DRA7_CAM_VIP3_CLKCTRL
,
dra7_cam_bit_data
,
CLKF_HW_SUP
,
"l3_iclk_div"
},
{
0
},
};
static
const
struct
omap_clkctrl_reg_data
dra7_vpe_clkctrl_regs
[]
__initconst
=
{
{
DRA7_VPE_VPE_CLKCTRL
,
NULL
,
CLKF_HW_SUP
,
"dpll_core_h23x2_ck"
},
{
0
},
};
static
const
struct
omap_clkctrl_reg_data
dra7_coreaon_clkctrl_regs
[]
__initconst
=
{
static
const
struct
omap_clkctrl_reg_data
dra7_coreaon_clkctrl_regs
[]
__initconst
=
{
{
DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
"wkupaon_iclk_mux"
},
{
DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
"wkupaon_iclk_mux"
},
{
DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
"wkupaon_iclk_mux"
},
{
DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
"wkupaon_iclk_mux"
},
...
@@ -275,6 +298,40 @@ static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst =
...
@@ -275,6 +298,40 @@ static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst =
{
0
},
{
0
},
};
};
static
const
char
*
const
dra7_gpu_core_mux_parents
[]
__initconst
=
{
"dpll_core_h14x2_ck"
,
"dpll_per_h14x2_ck"
,
"dpll_gpu_m2_ck"
,
NULL
,
};
static
const
char
*
const
dra7_gpu_hyd_mux_parents
[]
__initconst
=
{
"dpll_core_h14x2_ck"
,
"dpll_per_h14x2_ck"
,
"dpll_gpu_m2_ck"
,
NULL
,
};
static
const
char
*
const
dra7_gpu_sys_clk_parents
[]
__initconst
=
{
"sys_clkin"
,
NULL
,
};
static
const
struct
omap_clkctrl_div_data
dra7_gpu_sys_clk_data
__initconst
=
{
.
max_div
=
2
,
};
static
const
struct
omap_clkctrl_bit_data
dra7_gpu_core_bit_data
[]
__initconst
=
{
{
24
,
TI_CLK_MUX
,
dra7_gpu_core_mux_parents
,
NULL
,
},
{
26
,
TI_CLK_MUX
,
dra7_gpu_hyd_mux_parents
,
NULL
,
},
{
0
},
};
static
const
struct
omap_clkctrl_reg_data
dra7_gpu_clkctrl_regs
[]
__initconst
=
{
{
DRA7_GPU_CLKCTRL
,
dra7_gpu_core_bit_data
,
CLKF_SW_SUP
,
"gpu_cm:clk:0000:24"
,
},
{
0
},
};
static
const
char
*
const
dra7_mmc1_fclk_mux_parents
[]
__initconst
=
{
static
const
char
*
const
dra7_mmc1_fclk_mux_parents
[]
__initconst
=
{
"func_128m_clk"
,
"func_128m_clk"
,
"dpll_per_m2x2_ck"
,
"dpll_per_m2x2_ck"
,
...
@@ -405,7 +462,7 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
...
@@ -405,7 +462,7 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
};
};
static
const
struct
omap_clkctrl_reg_data
dra7_gmac_clkctrl_regs
[]
__initconst
=
{
static
const
struct
omap_clkctrl_reg_data
dra7_gmac_clkctrl_regs
[]
__initconst
=
{
{
DRA7_GMAC_GMAC_CLKCTRL
,
dra7_gmac_bit_data
,
CLKF_SW_SUP
,
"
dpll_gmac_c
k"
},
{
DRA7_GMAC_GMAC_CLKCTRL
,
dra7_gmac_bit_data
,
CLKF_SW_SUP
,
"
gmac_main_cl
k"
},
{
0
},
{
0
},
};
};
...
@@ -769,6 +826,7 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
...
@@ -769,6 +826,7 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
{
0x4a005550
,
dra7_ipu_clkctrl_regs
},
{
0x4a005550
,
dra7_ipu_clkctrl_regs
},
{
0x4a005620
,
dra7_dsp2_clkctrl_regs
},
{
0x4a005620
,
dra7_dsp2_clkctrl_regs
},
{
0x4a005720
,
dra7_rtc_clkctrl_regs
},
{
0x4a005720
,
dra7_rtc_clkctrl_regs
},
{
0x4a005760
,
dra7_vpe_clkctrl_regs
},
{
0x4a008620
,
dra7_coreaon_clkctrl_regs
},
{
0x4a008620
,
dra7_coreaon_clkctrl_regs
},
{
0x4a008720
,
dra7_l3main1_clkctrl_regs
},
{
0x4a008720
,
dra7_l3main1_clkctrl_regs
},
{
0x4a008920
,
dra7_ipu2_clkctrl_regs
},
{
0x4a008920
,
dra7_ipu2_clkctrl_regs
},
...
@@ -777,7 +835,9 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
...
@@ -777,7 +835,9 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
{
0x4a008c00
,
dra7_atl_clkctrl_regs
},
{
0x4a008c00
,
dra7_atl_clkctrl_regs
},
{
0x4a008d20
,
dra7_l4cfg_clkctrl_regs
},
{
0x4a008d20
,
dra7_l4cfg_clkctrl_regs
},
{
0x4a008e20
,
dra7_l3instr_clkctrl_regs
},
{
0x4a008e20
,
dra7_l3instr_clkctrl_regs
},
{
0x4a009020
,
dra7_cam_clkctrl_regs
},
{
0x4a009120
,
dra7_dss_clkctrl_regs
},
{
0x4a009120
,
dra7_dss_clkctrl_regs
},
{
0x4a009220
,
dra7_gpu_clkctrl_regs
},
{
0x4a009320
,
dra7_l3init_clkctrl_regs
},
{
0x4a009320
,
dra7_l3init_clkctrl_regs
},
{
0x4a0093b0
,
dra7_pcie_clkctrl_regs
},
{
0x4a0093b0
,
dra7_pcie_clkctrl_regs
},
{
0x4a0093d0
,
dra7_gmac_clkctrl_regs
},
{
0x4a0093d0
,
dra7_gmac_clkctrl_regs
},
...
...
drivers/clk/ti/clk.c
View file @
d7a9d45d
...
@@ -171,7 +171,9 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
...
@@ -171,7 +171,9 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
node
=
of_find_node_by_name
(
NULL
,
buf
);
node
=
of_find_node_by_name
(
NULL
,
buf
);
if
(
num_args
&&
compat_mode
)
{
if
(
num_args
&&
compat_mode
)
{
parent
=
node
;
parent
=
node
;
node
=
of_get_child_by_name
(
parent
,
"clk"
);
node
=
of_get_child_by_name
(
parent
,
"clock"
);
if
(
!
node
)
node
=
of_get_child_by_name
(
parent
,
"clk"
);
of_node_put
(
parent
);
of_node_put
(
parent
);
}
}
...
...
drivers/clk/ti/clkctrl.c
View file @
d7a9d45d
...
@@ -440,6 +440,63 @@ static void __init _clkctrl_add_provider(void *data,
...
@@ -440,6 +440,63 @@ static void __init _clkctrl_add_provider(void *data,
of_clk_add_hw_provider
(
np
,
_ti_omap4_clkctrl_xlate
,
data
);
of_clk_add_hw_provider
(
np
,
_ti_omap4_clkctrl_xlate
,
data
);
}
}
/* Get clock name based on compatible string for clkctrl */
static
char
*
__init
clkctrl_get_name
(
struct
device_node
*
np
)
{
struct
property
*
prop
;
const
int
prefix_len
=
11
;
const
char
*
compat
;
char
*
name
;
of_property_for_each_string
(
np
,
"compatible"
,
prop
,
compat
)
{
if
(
!
strncmp
(
"ti,clkctrl-"
,
compat
,
prefix_len
))
{
/* Two letter minimum name length for l3, l4 etc */
if
(
strnlen
(
compat
+
prefix_len
,
16
)
<
2
)
continue
;
name
=
kasprintf
(
GFP_KERNEL
,
"%s"
,
compat
+
prefix_len
);
if
(
!
name
)
continue
;
strreplace
(
name
,
'-'
,
'_'
);
return
name
;
}
}
of_node_put
(
np
);
return
NULL
;
}
/* Get clkctrl clock base name based on clkctrl_name or dts node */
static
const
char
*
__init
clkctrl_get_clock_name
(
struct
device_node
*
np
,
const
char
*
clkctrl_name
,
int
offset
,
int
index
,
bool
legacy_naming
)
{
char
*
clock_name
;
/* l4per-clkctrl:1234:0 style naming based on clkctrl_name */
if
(
clkctrl_name
&&
!
legacy_naming
)
{
clock_name
=
kasprintf
(
GFP_KERNEL
,
"%s-clkctrl:%04x:%d"
,
clkctrl_name
,
offset
,
index
);
strreplace
(
clock_name
,
'_'
,
'-'
);
return
clock_name
;
}
/* l4per:1234:0 old style naming based on clkctrl_name */
if
(
clkctrl_name
)
return
kasprintf
(
GFP_KERNEL
,
"%s_cm:clk:%04x:%d"
,
clkctrl_name
,
offset
,
index
);
/* l4per_cm:1234:0 old style naming based on parent node name */
if
(
legacy_naming
)
return
kasprintf
(
GFP_KERNEL
,
"%pOFn:clk:%04x:%d"
,
np
->
parent
,
offset
,
index
);
/* l4per-clkctrl:1234:0 style naming based on node name */
return
kasprintf
(
GFP_KERNEL
,
"%pOFn:%04x:%d"
,
np
,
offset
,
index
);
}
static
void
__init
_ti_omap4_clkctrl_setup
(
struct
device_node
*
node
)
static
void
__init
_ti_omap4_clkctrl_setup
(
struct
device_node
*
node
)
{
{
struct
omap_clkctrl_provider
*
provider
;
struct
omap_clkctrl_provider
*
provider
;
...
@@ -448,8 +505,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
...
@@ -448,8 +505,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
struct
clk_init_data
init
=
{
NULL
};
struct
clk_init_data
init
=
{
NULL
};
struct
clk_hw_omap
*
hw
;
struct
clk_hw_omap
*
hw
;
struct
clk
*
clk
;
struct
clk
*
clk
;
struct
omap_clkctrl_clk
*
clkctrl_clk
;
struct
omap_clkctrl_clk
*
clkctrl_clk
=
NULL
;
const
__be32
*
addrp
;
const
__be32
*
addrp
;
bool
legacy_naming
;
char
*
clkctrl_name
;
u32
addr
;
u32
addr
;
int
ret
;
int
ret
;
char
*
c
;
char
*
c
;
...
@@ -537,7 +596,19 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
...
@@ -537,7 +596,19 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
provider
->
base
=
of_iomap
(
node
,
0
);
provider
->
base
=
of_iomap
(
node
,
0
);
if
(
ti_clk_get_features
()
->
flags
&
TI_CLK_CLKCTRL_COMPAT
)
{
legacy_naming
=
ti_clk_get_features
()
->
flags
&
TI_CLK_CLKCTRL_COMPAT
;
clkctrl_name
=
clkctrl_get_name
(
node
);
if
(
clkctrl_name
)
{
provider
->
clkdm_name
=
kasprintf
(
GFP_KERNEL
,
"%s_clkdm"
,
clkctrl_name
);
goto
clkdm_found
;
}
/*
* The code below can be removed when all clkctrl nodes use domain
* specific compatible proprerty and standard clock node naming
*/
if
(
legacy_naming
)
{
provider
->
clkdm_name
=
kasprintf
(
GFP_KERNEL
,
"%pOFnxxx"
,
node
->
parent
);
provider
->
clkdm_name
=
kasprintf
(
GFP_KERNEL
,
"%pOFnxxx"
,
node
->
parent
);
if
(
!
provider
->
clkdm_name
)
{
if
(
!
provider
->
clkdm_name
)
{
kfree
(
provider
);
kfree
(
provider
);
...
@@ -573,7 +644,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
...
@@ -573,7 +644,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
*
c
=
'_'
;
*
c
=
'_'
;
c
++
;
c
++
;
}
}
clkdm_found:
INIT_LIST_HEAD
(
&
provider
->
clocks
);
INIT_LIST_HEAD
(
&
provider
->
clocks
);
/* Generate clocks */
/* Generate clocks */
...
@@ -612,15 +683,15 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
...
@@ -612,15 +683,15 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
init
.
flags
=
0
;
init
.
flags
=
0
;
if
(
reg_data
->
flags
&
CLKF_SET_RATE_PARENT
)
if
(
reg_data
->
flags
&
CLKF_SET_RATE_PARENT
)
init
.
flags
|=
CLK_SET_RATE_PARENT
;
init
.
flags
|=
CLK_SET_RATE_PARENT
;
if
(
ti_clk_get_features
()
->
flags
&
TI_CLK_CLKCTRL_COMPAT
)
init
.
name
=
kasprintf
(
GFP_KERNEL
,
"%pOFn:%pOFn:%04x:%d"
,
init
.
name
=
clkctrl_get_clock_name
(
node
,
clkctrl_name
,
node
->
parent
,
node
,
reg_data
->
offset
,
0
,
reg_data
->
offset
,
0
);
legacy_naming
);
else
if
(
!
init
.
name
)
init
.
name
=
kasprintf
(
GFP_KERNEL
,
"%pOFn:%04x:%d"
,
goto
cleanup
;
node
,
reg_data
->
offset
,
0
);
clkctrl_clk
=
kzalloc
(
sizeof
(
*
clkctrl_clk
),
GFP_KERNEL
);
clkctrl_clk
=
kzalloc
(
sizeof
(
*
clkctrl_clk
),
GFP_KERNEL
);
if
(
!
init
.
name
||
!
clkctrl_clk
)
if
(
!
clkctrl_clk
)
goto
cleanup
;
goto
cleanup
;
init
.
ops
=
&
omap4_clkctrl_clk_ops
;
init
.
ops
=
&
omap4_clkctrl_clk_ops
;
...
@@ -642,11 +713,14 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
...
@@ -642,11 +713,14 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
if
(
ret
==
-
EPROBE_DEFER
)
if
(
ret
==
-
EPROBE_DEFER
)
ti_clk_retry_init
(
node
,
provider
,
_clkctrl_add_provider
);
ti_clk_retry_init
(
node
,
provider
,
_clkctrl_add_provider
);
kfree
(
clkctrl_name
);
return
;
return
;
cleanup:
cleanup:
kfree
(
hw
);
kfree
(
hw
);
kfree
(
init
.
name
);
kfree
(
init
.
name
);
kfree
(
clkctrl_name
);
kfree
(
clkctrl_clk
);
kfree
(
clkctrl_clk
);
}
}
CLK_OF_DECLARE
(
ti_omap4_clkctrl_clock
,
"ti,clkctrl"
,
CLK_OF_DECLARE
(
ti_omap4_clkctrl_clock
,
"ti,clkctrl"
,
...
...
include/dt-bindings/clock/dra7.h
View file @
d7a9d45d
...
@@ -29,6 +29,16 @@
...
@@ -29,6 +29,16 @@
#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
/* vip clocks */
#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* vpe clocks */
#define DRA7_VPE_CLKCTRL_OFFSET 0x60
#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64)
/* coreaon clocks */
/* coreaon clocks */
#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
...
@@ -78,6 +88,9 @@
...
@@ -78,6 +88,9 @@
#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* gpu clocks */
#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* l3init clocks */
/* l3init clocks */
#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
...
@@ -192,6 +205,16 @@
...
@@ -192,6 +205,16 @@
/* rtc clocks */
/* rtc clocks */
#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44)
#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44)
/* vip clocks */
#define DRA7_CAM_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* vpe clocks */
#define DRA7_VPE_CLKCTRL_OFFSET 0x60
#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
#define DRA7_VPE_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64)
/* coreaon clocks */
/* coreaon clocks */
#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
...
...
include/dt-bindings/clock/omap5.h
View file @
d7a9d45d
...
@@ -16,6 +16,7 @@
...
@@ -16,6 +16,7 @@
/* abe clocks */
/* abe clocks */
#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
...
...
include/dt-bindings/clk/ti-dra7-atl.h
→
include/dt-bindings/cl
oc
k/ti-dra7-atl.h
View file @
d7a9d45d
File moved
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment