Commit d8c25d3a authored by Stephen Boyd's avatar Stephen Boyd

clk: qcom: pll: Add support for configuring SR PLLs

Some SR type PLLs need to be configured for a certain rate when
linux boots. Add support for these types of PLLs so that we can
program PLL15's rate on apq8064.
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent f87dfcab
...@@ -166,7 +166,7 @@ const struct clk_ops clk_pll_vote_ops = { ...@@ -166,7 +166,7 @@ const struct clk_ops clk_pll_vote_ops = {
EXPORT_SYMBOL_GPL(clk_pll_vote_ops); EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
static void static void
clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap) clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count)
{ {
u32 val; u32 val;
u32 mask; u32 mask;
...@@ -175,7 +175,7 @@ clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap) ...@@ -175,7 +175,7 @@ clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap)
regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0); regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0);
/* Program bias count and lock count */ /* Program bias count and lock count */
val = 1 << PLL_BIAS_COUNT_SHIFT; val = 1 << PLL_BIAS_COUNT_SHIFT | lock_count << PLL_LOCK_COUNT_SHIFT;
mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT; mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT; mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
regmap_update_bits(regmap, pll->mode_reg, mask, val); regmap_update_bits(regmap, pll->mode_reg, mask, val);
...@@ -212,11 +212,20 @@ static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap, ...@@ -212,11 +212,20 @@ static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
regmap_update_bits(regmap, pll->config_reg, mask, val); regmap_update_bits(regmap, pll->config_reg, mask, val);
} }
void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
const struct pll_config *config, bool fsm_mode)
{
clk_pll_configure(pll, regmap, config);
if (fsm_mode)
clk_pll_set_fsm_mode(pll, regmap, 8);
}
EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
const struct pll_config *config, bool fsm_mode) const struct pll_config *config, bool fsm_mode)
{ {
clk_pll_configure(pll, regmap, config); clk_pll_configure(pll, regmap, config);
if (fsm_mode) if (fsm_mode)
clk_pll_set_fsm_mode(pll, regmap); clk_pll_set_fsm_mode(pll, regmap, 0);
} }
EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp); EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
...@@ -60,6 +60,8 @@ struct pll_config { ...@@ -60,6 +60,8 @@ struct pll_config {
u32 aux_output_mask; u32 aux_output_mask;
}; };
void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
const struct pll_config *config, bool fsm_mode);
void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
const struct pll_config *config, bool fsm_mode); const struct pll_config *config, bool fsm_mode);
......
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