Commit d99a2118 authored by Michael Krufky's avatar Michael Krufky Committed by Mauro Carvalho Chehab

V4L/DVB: lgdt3305: consolidate init functions

Signed-off-by: default avatarMichael Krufky <mkrufky@kernellabs.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 241b0f41
......@@ -587,7 +587,7 @@ static int lgdt3305_sleep(struct dvb_frontend *fe)
return 0;
}
static int lgdt3304_init(struct dvb_frontend *fe)
static int lgdt3305_init(struct dvb_frontend *fe)
{
struct lgdt3305_state *state = fe->demodulator_priv;
int ret;
......@@ -624,78 +624,47 @@ static int lgdt3304_init(struct dvb_frontend *fe)
{ .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, },
};
lg_dbg("\n");
ret = lgdt3305_write_regs(state, lgdt3304_init_data,
ARRAY_SIZE(lgdt3304_init_data));
if (lg_fail(ret))
goto fail;
ret = lgdt3305_soft_reset(state);
fail:
return ret;
}
static int lgdt3305_init(struct dvb_frontend *fe)
{
struct lgdt3305_state *state = fe->demodulator_priv;
int ret;
static struct lgdt3305_reg lgdt3305_init_data[] = {
{ .reg = LGDT3305_GEN_CTRL_1,
.val = 0x03, },
{ .reg = LGDT3305_GEN_CTRL_2,
.val = 0xb0, },
{ .reg = LGDT3305_GEN_CTRL_3,
.val = 0x01, },
{ .reg = LGDT3305_GEN_CONTROL,
.val = 0x6f, },
{ .reg = LGDT3305_GEN_CTRL_4,
.val = 0x03, },
{ .reg = LGDT3305_DGTL_AGC_REF_1,
.val = 0x32, },
{ .reg = LGDT3305_DGTL_AGC_REF_2,
.val = 0xc4, },
{ .reg = LGDT3305_CR_CTR_FREQ_1,
.val = 0x00, },
{ .reg = LGDT3305_CR_CTR_FREQ_2,
.val = 0x00, },
{ .reg = LGDT3305_CR_CTR_FREQ_3,
.val = 0x00, },
{ .reg = LGDT3305_CR_CTR_FREQ_4,
.val = 0x00, },
{ .reg = LGDT3305_CR_CTRL_7,
.val = 0x79, },
{ .reg = LGDT3305_AGC_POWER_REF_1,
.val = 0x32, },
{ .reg = LGDT3305_AGC_POWER_REF_2,
.val = 0xc4, },
{ .reg = LGDT3305_AGC_DELAY_PT_1,
.val = 0x0d, },
{ .reg = LGDT3305_AGC_DELAY_PT_2,
.val = 0x30, },
{ .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1,
.val = 0x80, },
{ .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2,
.val = 0x00, },
{ .reg = LGDT3305_IFBW_1,
.val = 0x80, },
{ .reg = LGDT3305_IFBW_2,
.val = 0x00, },
{ .reg = LGDT3305_AGC_CTRL_1,
.val = 0x30, },
{ .reg = LGDT3305_AGC_CTRL_4,
.val = 0x61, },
{ .reg = LGDT3305_FEC_BLOCK_CTRL,
.val = 0xff, },
{ .reg = LGDT3305_TP_CTRL_1,
.val = 0x1b, },
{ .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, },
{ .reg = LGDT3305_GEN_CTRL_2, .val = 0xb0, },
{ .reg = LGDT3305_GEN_CTRL_3, .val = 0x01, },
{ .reg = LGDT3305_GEN_CONTROL, .val = 0x6f, },
{ .reg = LGDT3305_GEN_CTRL_4, .val = 0x03, },
{ .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, },
{ .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, },
{ .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, },
{ .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, },
{ .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, },
{ .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, },
{ .reg = LGDT3305_CR_CTRL_7, .val = 0x79, },
{ .reg = LGDT3305_AGC_POWER_REF_1, .val = 0x32, },
{ .reg = LGDT3305_AGC_POWER_REF_2, .val = 0xc4, },
{ .reg = LGDT3305_AGC_DELAY_PT_1, .val = 0x0d, },
{ .reg = LGDT3305_AGC_DELAY_PT_2, .val = 0x30, },
{ .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, },
{ .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, },
{ .reg = LGDT3305_IFBW_1, .val = 0x80, },
{ .reg = LGDT3305_IFBW_2, .val = 0x00, },
{ .reg = LGDT3305_AGC_CTRL_1, .val = 0x30, },
{ .reg = LGDT3305_AGC_CTRL_4, .val = 0x61, },
{ .reg = LGDT3305_FEC_BLOCK_CTRL, .val = 0xff, },
{ .reg = LGDT3305_TP_CTRL_1, .val = 0x1b, },
};
lg_dbg("\n");
switch (state->cfg->demod_chip) {
case LGDT3304:
ret = lgdt3305_write_regs(state, lgdt3304_init_data,
ARRAY_SIZE(lgdt3304_init_data));
break;
case LGDT3305:
ret = lgdt3305_write_regs(state, lgdt3305_init_data,
ARRAY_SIZE(lgdt3305_init_data));
break;
default:
ret = -EINVAL;
}
if (lg_fail(ret))
goto fail;
......@@ -1198,7 +1167,7 @@ static struct dvb_frontend_ops lgdt3304_ops = {
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl,
.init = lgdt3304_init,
.init = lgdt3305_init,
.set_frontend = lgdt3304_set_parameters,
.get_frontend = lgdt3305_get_frontend,
.get_tune_settings = lgdt3305_get_tune_settings,
......
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