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Commit dbf9bfe6 authored by jack wang's avatar jack wang Committed by James Bottomley
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[SCSI] pm8001: add SAS/SATA HBA driver 

This driver supports PMC-Sierra PCIe SAS/SATA 8x6G SPC 8001 chip based
host adapters.
Signed-off-by: default avatarJack Wang <jack_wang@usish.com>
Signed-off-by: default avatarLindar Liu <lindar_liu@usish.com>
Signed-off-by: default avatarTom Peng <tom_peng@usish.com>
Signed-off-by: default avatarKevin Ao <aoqingyun@usish.com>
Signed-off-by: default avatarJames Bottomley <James.Bottomley@suse.de>
parent 35e66019
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MAINTAINERS
View file @ dbf9bfe6
...@@ -4116,6 +4116,13 @@ W: http://www.pmc-sierra.com/ ...@@ -4116,6 +4116,13 @@ W: http://www.pmc-sierra.com/
S: Supported S: Supported
F: drivers/scsi/pmcraid.* F: drivers/scsi/pmcraid.*
PMC SIERRA PM8001 DRIVER
M: jack_wang@usish.com
M: lindar_liu@usish.com
L: linux-scsi@vger.kernel.org
S: Supported
F: drivers/scsi/pm8001/
POSIX CLOCKS and TIMERS POSIX CLOCKS and TIMERS
M: Thomas Gleixner <tglx@linutronix.de> M: Thomas Gleixner <tglx@linutronix.de>
S: Supported S: Supported
......
drivers/scsi/Kconfig
View file @ dbf9bfe6
...@@ -1818,6 +1818,14 @@ config SCSI_PMCRAID ...@@ -1818,6 +1818,14 @@ config SCSI_PMCRAID
---help--- ---help---
This driver supports the PMC SIERRA MaxRAID adapters. This driver supports the PMC SIERRA MaxRAID adapters.
config SCSI_PM8001
tristate "PMC-Sierra SPC 8001 SAS/SATA Based Host Adapter driver"
depends on PCI && SCSI
select SCSI_SAS_LIBSAS
help
This driver supports PMC-Sierra PCIE SAS/SATA 8x6G SPC 8001 chip
based host adapters.
config SCSI_SRP config SCSI_SRP
tristate "SCSI RDMA Protocol helper library" tristate "SCSI RDMA Protocol helper library"
depends on SCSI && PCI depends on SCSI && PCI
......
drivers/scsi/Makefile
View file @ dbf9bfe6
...@@ -70,6 +70,7 @@ obj-$(CONFIG_SCSI_AIC79XX) += aic7xxx/ ...@@ -70,6 +70,7 @@ obj-$(CONFIG_SCSI_AIC79XX) += aic7xxx/
obj-$(CONFIG_SCSI_AACRAID) += aacraid/ obj-$(CONFIG_SCSI_AACRAID) += aacraid/
obj-$(CONFIG_SCSI_AIC7XXX_OLD) += aic7xxx_old.o obj-$(CONFIG_SCSI_AIC7XXX_OLD) += aic7xxx_old.o
obj-$(CONFIG_SCSI_AIC94XX) += aic94xx/ obj-$(CONFIG_SCSI_AIC94XX) += aic94xx/
obj-$(CONFIG_SCSI_PM8001) += pm8001/
obj-$(CONFIG_SCSI_IPS) += ips.o obj-$(CONFIG_SCSI_IPS) += ips.o
obj-$(CONFIG_SCSI_FD_MCS) += fd_mcs.o obj-$(CONFIG_SCSI_FD_MCS) += fd_mcs.o
obj-$(CONFIG_SCSI_FUTURE_DOMAIN)+= fdomain.o obj-$(CONFIG_SCSI_FUTURE_DOMAIN)+= fdomain.o
......
drivers/scsi/pm8001/Makefile 0 → 100644
View file @ dbf9bfe6
#
# Kernel configuration file for the PM8001 SAS/SATA 8x6G based HBA driver
#
# Copyright (C) 2008-2009 USI Co., Ltd.
obj-$(CONFIG_SCSI_PM8001) += pm8001.o
pm8001-y += pm8001_init.o \
pm8001_sas.o \
pm8001_ctl.o \
pm8001_hwi.o
drivers/scsi/pm8001/pm8001_chips.h 0 → 100644
View file @ dbf9bfe6
/*
* PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
*
* Copyright (c) 2008-2009 USI Co., Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
*/
#ifndef _PM8001_CHIPS_H_
#define _PM8001_CHIPS_H_
static inline u32 pm8001_read_32(void *virt_addr)
{
return *((u32 *)virt_addr);
}
static inline void pm8001_write_32(void *addr, u32 offset, u32 val)
{
*((u32 *)(addr + offset)) = val;
}
static inline u32 pm8001_cr32(struct pm8001_hba_info *pm8001_ha, u32 bar,
u32 offset)
{
return readl(pm8001_ha->io_mem[bar].memvirtaddr + offset);
}
static inline void pm8001_cw32(struct pm8001_hba_info *pm8001_ha, u32 bar,
u32 addr, u32 val)
{
writel(val, pm8001_ha->io_mem[bar].memvirtaddr + addr);
}
static inline u32 pm8001_mr32(void __iomem *addr, u32 offset)
{
return readl(addr + offset);
}
static inline void pm8001_mw32(void __iomem *addr, u32 offset, u32 val)
{
writel(val, addr + offset);
}
static inline u32 get_pci_bar_index(u32 pcibar)
{
switch (pcibar) {
case 0x18:
case 0x1C:
return 1;
case 0x20:
return 2;
case 0x24:
return 3;
default:
return 0;
}
}
#endif /* _PM8001_CHIPS_H_ */
drivers/scsi/pm8001/pm8001_ctl.c 0 → 100644
View file @ dbf9bfe6
/*
* PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
*
* Copyright (c) 2008-2009 USI Co., Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
*/
#include <linux/firmware.h>
#include "pm8001_sas.h"
#include "pm8001_ctl.h"
/* scsi host attributes */
/**
* pm8001_ctl_mpi_interface_rev_show - MPI interface revision number
* @cdev: pointer to embedded class device
* @buf: the buffer returned
*
* A sysfs 'read-only' shost attribute.
*/
static ssize_t pm8001_ctl_mpi_interface_rev_show(struct device *cdev,
struct device_attribute *attr, char *buf)
{
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
return snprintf(buf, PAGE_SIZE, "%d\n",
pm8001_ha->main_cfg_tbl.interface_rev);
}
static
DEVICE_ATTR(interface_rev, S_IRUGO, pm8001_ctl_mpi_interface_rev_show, NULL);
/**
* pm8001_ctl_fw_version_show - firmware version
* @cdev: pointer to embedded class device
* @buf: the buffer returned
*
* A sysfs 'read-only' shost attribute.
*/
static ssize_t pm8001_ctl_fw_version_show(struct device *cdev,
struct device_attribute *attr, char *buf)
{
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
return snprintf(buf, PAGE_SIZE, "%02x.%02x.%02x.%02x\n",
(u8)(pm8001_ha->main_cfg_tbl.firmware_rev >> 24),
(u8)(pm8001_ha->main_cfg_tbl.firmware_rev >> 16),
(u8)(pm8001_ha->main_cfg_tbl.firmware_rev >> 8),
(u8)(pm8001_ha->main_cfg_tbl.firmware_rev));
}
static DEVICE_ATTR(fw_version, S_IRUGO, pm8001_ctl_fw_version_show, NULL);
/**
* pm8001_ctl_max_out_io_show - max outstanding io supported
* @cdev: pointer to embedded class device
* @buf: the buffer returned
*
* A sysfs 'read-only' shost attribute.
*/
static ssize_t pm8001_ctl_max_out_io_show(struct device *cdev,
struct device_attribute *attr, char *buf)
{
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
return snprintf(buf, PAGE_SIZE, "%d\n",
pm8001_ha->main_cfg_tbl.max_out_io);
}
static DEVICE_ATTR(max_out_io, S_IRUGO, pm8001_ctl_max_out_io_show, NULL);
/**
* pm8001_ctl_max_devices_show - max devices support
* @cdev: pointer to embedded class device
* @buf: the buffer returned
*
* A sysfs 'read-only' shost attribute.
*/
static ssize_t pm8001_ctl_max_devices_show(struct device *cdev,
struct device_attribute *attr, char *buf)
{
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
return snprintf(buf, PAGE_SIZE, "%04d\n",
(u16)(pm8001_ha->main_cfg_tbl.max_sgl >> 16));
}
static DEVICE_ATTR(max_devices, S_IRUGO, pm8001_ctl_max_devices_show, NULL);
/**
* pm8001_ctl_max_sg_list_show - max sg list supported iff not 0.0 for no
* hardware limitation
* @cdev: pointer to embedded class device
* @buf: the buffer returned
*
* A sysfs 'read-only' shost attribute.
*/
static ssize_t pm8001_ctl_max_sg_list_show(struct device *cdev,
struct device_attribute *attr, char *buf)
{
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
return snprintf(buf, PAGE_SIZE, "%04d\n",
pm8001_ha->main_cfg_tbl.max_sgl & 0x0000FFFF);
}
static DEVICE_ATTR(max_sg_list, S_IRUGO, pm8001_ctl_max_sg_list_show, NULL);
#define SAS_1_0 0x1
#define SAS_1_1 0x2
#define SAS_2_0 0x4
static ssize_t
show_sas_spec_support_status(unsigned int mode, char *buf)
{
ssize_t len = 0;
if (mode & SAS_1_1)
len = sprintf(buf, "%s", "SAS1.1");
if (mode & SAS_2_0)
len += sprintf(buf + len, "%s%s", len ? ", " : "", "SAS2.0");
len += sprintf(buf + len, "\n");
return len;
}
/**
* pm8001_ctl_sas_spec_support_show - sas spec supported
* @cdev: pointer to embedded class device
* @buf: the buffer returned
*
* A sysfs 'read-only' shost attribute.
*/
static ssize_t pm8001_ctl_sas_spec_support_show(struct device *cdev,
struct device_attribute *attr, char *buf)
{
unsigned int mode;
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
mode = (pm8001_ha->main_cfg_tbl.ctrl_cap_flag & 0xfe000000)>>25;
return show_sas_spec_support_status(mode, buf);
}
static DEVICE_ATTR(sas_spec_support, S_IRUGO,
pm8001_ctl_sas_spec_support_show, NULL);
/**
* pm8001_ctl_sas_address_show - sas address
* @cdev: pointer to embedded class device
* @buf: the buffer returned
*
* This is the controller sas address
*
* A sysfs 'read-only' shost attribute.
*/
static ssize_t pm8001_ctl_host_sas_address_show(struct device *cdev,
struct device_attribute *attr, char *buf)
{
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
return snprintf(buf, PAGE_SIZE, "0x%016llx\n",
be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr));
}
static DEVICE_ATTR(host_sas_address, S_IRUGO,
pm8001_ctl_host_sas_address_show, NULL);
/**
* pm8001_ctl_logging_level_show - logging level
* @cdev: pointer to embedded class device
* @buf: the buffer returned
*
* A sysfs 'read/write' shost attribute.
*/
static ssize_t pm8001_ctl_logging_level_show(struct device *cdev,
struct device_attribute *attr, char *buf)
{
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
return snprintf(buf, PAGE_SIZE, "%08xh\n", pm8001_ha->logging_level);
}
static ssize_t pm8001_ctl_logging_level_store(struct device *cdev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
int val = 0;
if (sscanf(buf, "%x", &val) != 1)
return -EINVAL;
pm8001_ha->logging_level = val;
return strlen(buf);
}
static DEVICE_ATTR(logging_level, S_IRUGO | S_IWUSR,
pm8001_ctl_logging_level_show, pm8001_ctl_logging_level_store);
/**
* pm8001_ctl_aap_log_show - aap1 event log
* @cdev: pointer to embedded class device
* @buf: the buffer returned
*
* A sysfs 'read-only' shost attribute.
*/
static ssize_t pm8001_ctl_aap_log_show(struct device *cdev,
struct device_attribute *attr, char *buf)
{
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
int i;
#define AAP1_MEMMAP(r, c) \
(*(u32 *)((u8*)pm8001_ha->memoryMap.region[AAP1].virt_ptr + (r) * 32 \
+ (c)))
char *str = buf;
int max = 2;
for (i = 0; i < max; i++) {
str += sprintf(str, "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x"
"0x%08x 0x%08x\n",
AAP1_MEMMAP(i, 0),
AAP1_MEMMAP(i, 4),
AAP1_MEMMAP(i, 8),
AAP1_MEMMAP(i, 12),
AAP1_MEMMAP(i, 16),
AAP1_MEMMAP(i, 20),
AAP1_MEMMAP(i, 24),
AAP1_MEMMAP(i, 28));
}
return str - buf;
}
static DEVICE_ATTR(aap_log, S_IRUGO, pm8001_ctl_aap_log_show, NULL);
/**
* pm8001_ctl_aap_log_show - IOP event log
* @cdev: pointer to embedded class device
* @buf: the buffer returned
*
* A sysfs 'read-only' shost attribute.
*/
static ssize_t pm8001_ctl_iop_log_show(struct device *cdev,
struct device_attribute *attr, char *buf)
{
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
#define IOP_MEMMAP(r, c) \
(*(u32 *)((u8*)pm8001_ha->memoryMap.region[IOP].virt_ptr + (r) * 32 \
+ (c)))
int i;
char *str = buf;
int max = 2;
for (i = 0; i < max; i++) {
str += sprintf(str, "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x"
"0x%08x 0x%08x\n",
IOP_MEMMAP(i, 0),
IOP_MEMMAP(i, 4),
IOP_MEMMAP(i, 8),
IOP_MEMMAP(i, 12),
IOP_MEMMAP(i, 16),
IOP_MEMMAP(i, 20),
IOP_MEMMAP(i, 24),
IOP_MEMMAP(i, 28));
}
return str - buf;
}
static DEVICE_ATTR(iop_log, S_IRUGO, pm8001_ctl_iop_log_show, NULL);
#define FLASH_CMD_NONE 0x00
#define FLASH_CMD_UPDATE 0x01
#define FLASH_CMD_SET_NVMD 0x02
struct flash_command {
u8 command[8];
int code;
};
static struct flash_command flash_command_table[] =
{
{"set_nvmd", FLASH_CMD_SET_NVMD},
{"update", FLASH_CMD_UPDATE},
{"", FLASH_CMD_NONE} /* Last entry should be NULL. */
};
struct error_fw {
char *reason;
int err_code;
};
static struct error_fw flash_error_table[] =
{
{"Failed to open fw image file", FAIL_OPEN_BIOS_FILE},
{"image header mismatch", FLASH_UPDATE_HDR_ERR},
{"image offset mismatch", FLASH_UPDATE_OFFSET_ERR},
{"image CRC Error", FLASH_UPDATE_CRC_ERR},
{"image length Error.", FLASH_UPDATE_LENGTH_ERR},
{"Failed to program flash chip", FLASH_UPDATE_HW_ERR},
{"Flash chip not supported.", FLASH_UPDATE_DNLD_NOT_SUPPORTED},
{"Flash update disabled.", FLASH_UPDATE_DISABLED},
{"Flash in progress", FLASH_IN_PROGRESS},
{"Image file size Error", FAIL_FILE_SIZE},
{"Input parameter error", FAIL_PARAMETERS},
{"Out of memory", FAIL_OUT_MEMORY},
{"OK", 0} /* Last entry err_code = 0. */
};
static int pm8001_set_nvmd(struct pm8001_hba_info *pm8001_ha)
{
struct pm8001_ioctl_payload *payload;
DECLARE_COMPLETION_ONSTACK(completion);
u8 *ioctlbuffer = NULL;
u32 length = 0;
u32 ret = 0;
length = 1024 * 5 + sizeof(*payload) - 1;
ioctlbuffer = kzalloc(length, GFP_KERNEL);
if (!ioctlbuffer)
return -ENOMEM;
if ((pm8001_ha->fw_image->size <= 0) ||
(pm8001_ha->fw_image->size > 4096)) {
ret = FAIL_FILE_SIZE;
goto out;
}
payload = (struct pm8001_ioctl_payload *)ioctlbuffer;
memcpy((u8 *)payload->func_specific, (u8 *)pm8001_ha->fw_image->data,
pm8001_ha->fw_image->size);
payload->length = pm8001_ha->fw_image->size;
payload->id = 0;
pm8001_ha->nvmd_completion = &completion;
ret = PM8001_CHIP_DISP->set_nvmd_req(pm8001_ha, payload);
wait_for_completion(&completion);
out:
kfree(ioctlbuffer);
return ret;
}
static int pm8001_update_flash(struct pm8001_hba_info *pm8001_ha)
{
struct pm8001_ioctl_payload *payload;
DECLARE_COMPLETION_ONSTACK(completion);
u8 *ioctlbuffer = NULL;
u32 length = 0;
struct fw_control_info *fwControl;
u32 loopNumber, loopcount = 0;
u32 sizeRead = 0;
u32 partitionSize, partitionSizeTmp;
u32 ret = 0;
u32 partitionNumber = 0;
struct pm8001_fw_image_header *image_hdr;
length = 1024 * 16 + sizeof(*payload) - 1;
ioctlbuffer = kzalloc(length, GFP_KERNEL);
image_hdr = (struct pm8001_fw_image_header *)pm8001_ha->fw_image->data;
if (!ioctlbuffer)
return -ENOMEM;
if (pm8001_ha->fw_image->size < 28) {
ret = FAIL_FILE_SIZE;
goto out;
}
while (sizeRead < pm8001_ha->fw_image->size) {
partitionSizeTmp =
*(u32 *)((u8 *)&image_hdr->image_length + sizeRead);
partitionSize = be32_to_cpu(partitionSizeTmp);
loopcount = (partitionSize + HEADER_LEN)/IOCTL_BUF_SIZE;
if (loopcount % IOCTL_BUF_SIZE)
loopcount++;
if (loopcount == 0)
loopcount++;
for (loopNumber = 0; loopNumber < loopcount; loopNumber++) {
payload = (struct pm8001_ioctl_payload *)ioctlbuffer;
payload->length = 1024*16;
payload->id = 0;
fwControl =
(struct fw_control_info *)payload->func_specific;
fwControl->len = IOCTL_BUF_SIZE; /* IN */
fwControl->size = partitionSize + HEADER_LEN;/* IN */
fwControl->retcode = 0;/* OUT */
fwControl->offset = loopNumber * IOCTL_BUF_SIZE;/*OUT */
/* for the last chunk of data in case file size is not even with
4k, load only the rest*/
if (((loopcount-loopNumber) == 1) &&
((partitionSize + HEADER_LEN) % IOCTL_BUF_SIZE)) {
fwControl->len =
(partitionSize + HEADER_LEN) % IOCTL_BUF_SIZE;
memcpy((u8 *)fwControl->buffer,
(u8 *)pm8001_ha->fw_image->data + sizeRead,
(partitionSize + HEADER_LEN) % IOCTL_BUF_SIZE);
sizeRead +=
(partitionSize + HEADER_LEN) % IOCTL_BUF_SIZE;
} else {
memcpy((u8 *)fwControl->buffer,
(u8 *)pm8001_ha->fw_image->data + sizeRead,
IOCTL_BUF_SIZE);
sizeRead += IOCTL_BUF_SIZE;
}
pm8001_ha->nvmd_completion = &completion;
ret = PM8001_CHIP_DISP->fw_flash_update_req(pm8001_ha, payload);
wait_for_completion(&completion);
if (ret || (fwControl->retcode > FLASH_UPDATE_IN_PROGRESS)) {
ret = fwControl->retcode;
kfree(ioctlbuffer);
ioctlbuffer = NULL;
break;
}
}
if (ret)
break;
partitionNumber++;
}
out:
kfree(ioctlbuffer);
return ret;
}
static ssize_t pm8001_store_update_fw(struct device *cdev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
char *cmd_ptr, *filename_ptr;
int res, i;
int flash_command = FLASH_CMD_NONE;
int err = 0;
if (!capable(CAP_SYS_ADMIN))
return -EACCES;
cmd_ptr = kzalloc(count*2, GFP_KERNEL);
if (!cmd_ptr) {
err = FAIL_OUT_MEMORY;
goto out;
}
filename_ptr = cmd_ptr + count;
res = sscanf(buf, "%s %s", cmd_ptr, filename_ptr);
if (res != 2) {
err = FAIL_PARAMETERS;
goto out1;
}
for (i = 0; flash_command_table[i].code != FLASH_CMD_NONE; i++) {
if (!memcmp(flash_command_table[i].command,
cmd_ptr, strlen(cmd_ptr))) {
flash_command = flash_command_table[i].code;
break;
}
}
if (flash_command == FLASH_CMD_NONE) {
err = FAIL_PARAMETERS;
goto out1;
}
if (pm8001_ha->fw_status == FLASH_IN_PROGRESS) {
err = FLASH_IN_PROGRESS;
goto out1;
}
err = request_firmware(&pm8001_ha->fw_image,
filename_ptr,
pm8001_ha->dev);
if (err) {
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("Failed to load firmware image file %s,"
" error %d\n", filename_ptr, err));
err = FAIL_OPEN_BIOS_FILE;
goto out1;
}
switch (flash_command) {
case FLASH_CMD_UPDATE:
pm8001_ha->fw_status = FLASH_IN_PROGRESS;
err = pm8001_update_flash(pm8001_ha);
break;
case FLASH_CMD_SET_NVMD:
pm8001_ha->fw_status = FLASH_IN_PROGRESS;
err = pm8001_set_nvmd(pm8001_ha);
break;
default:
pm8001_ha->fw_status = FAIL_PARAMETERS;
err = FAIL_PARAMETERS;
break;
}
release_firmware(pm8001_ha->fw_image);
out1:
kfree(cmd_ptr);
out:
pm8001_ha->fw_status = err;
if (!err)
return count;
else
return -err;
}
static ssize_t pm8001_show_update_fw(struct device *cdev,
struct device_attribute *attr, char *buf)
{
int i;
struct Scsi_Host *shost = class_to_shost(cdev);
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
for (i = 0; flash_error_table[i].err_code != 0; i++) {
if (flash_error_table[i].err_code == pm8001_ha->fw_status)
break;
}
if (pm8001_ha->fw_status != FLASH_IN_PROGRESS)
pm8001_ha->fw_status = FLASH_OK;
return snprintf(buf, PAGE_SIZE, "status=%x %s\n",
flash_error_table[i].err_code,
flash_error_table[i].reason);
}
static DEVICE_ATTR(update_fw, S_IRUGO|S_IWUGO,
pm8001_show_update_fw, pm8001_store_update_fw);
struct device_attribute *pm8001_host_attrs[] = {
&dev_attr_interface_rev,
&dev_attr_fw_version,
&dev_attr_update_fw,
&dev_attr_aap_log,
&dev_attr_iop_log,
&dev_attr_max_out_io,
&dev_attr_max_devices,
&dev_attr_max_sg_list,
&dev_attr_sas_spec_support,
&dev_attr_logging_level,
&dev_attr_host_sas_address,
NULL,
};
drivers/scsi/pm8001/pm8001_ctl.h 0 → 100644
View file @ dbf9bfe6
/*
* PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
*
* Copyright (c) 2008-2009 USI Co., Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
*/
#ifndef PM8001_CTL_H_INCLUDED
#define PM8001_CTL_H_INCLUDED
#define IOCTL_BUF_SIZE 4096
#define HEADER_LEN 28
#define SIZE_OFFSET 16
struct pm8001_ioctl_payload {
u32 signature;
u16 major_function;
u16 minor_function;
u16 length;
u16 status;
u16 offset;
u16 id;
u8 func_specific[1];
};
#define FLASH_OK 0x000000
#define FAIL_OPEN_BIOS_FILE 0x000100
#define FAIL_FILE_SIZE 0x000a00
#define FAIL_PARAMETERS 0x000b00
#define FAIL_OUT_MEMORY 0x000c00
#define FLASH_IN_PROGRESS 0x001000
#endif /* PM8001_CTL_H_INCLUDED */
drivers/scsi/pm8001/pm8001_defs.h 0 → 100644
View file @ dbf9bfe6
/*
* PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
*
* Copyright (c) 2008-2009 USI Co., Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
*/
#ifndef _PM8001_DEFS_H_
#define _PM8001_DEFS_H_
enum chip_flavors {
chip_8001,
};
#define USI_MAX_MEMCNT 9
#define PM8001_MAX_DMA_SG SG_ALL
enum phy_speed {
PHY_SPEED_15 = 0x01,
PHY_SPEED_30 = 0x02,
PHY_SPEED_60 = 0x04,
};
enum data_direction {
DATA_DIR_NONE = 0x0, /* NO TRANSFER */
DATA_DIR_IN = 0x01, /* INBOUND */
DATA_DIR_OUT = 0x02, /* OUTBOUND */
DATA_DIR_BYRECIPIENT = 0x04, /* UNSPECIFIED */
};
enum port_type {
PORT_TYPE_SAS = (1L << 1),
PORT_TYPE_SATA = (1L << 0),
};
/* driver compile-time configuration */
#define PM8001_MAX_CCB 512 /* max ccbs supported */
#define PM8001_MAX_INB_NUM 1
#define PM8001_MAX_OUTB_NUM 1
#define PM8001_CAN_QUEUE 128 /* SCSI Queue depth */
/* unchangeable hardware details */
#define PM8001_MAX_PHYS 8 /* max. possible phys */
#define PM8001_MAX_PORTS 8 /* max. possible ports */
#define PM8001_MAX_DEVICES 1024 /* max supported device */
enum memory_region_num {
AAP1 = 0x0, /* application acceleration processor */
IOP, /* IO processor */
CI, /* consumer index */
PI, /* producer index */
IB, /* inbound queue */
OB, /* outbound queue */
NVMD, /* NVM device */
DEV_MEM, /* memory for devices */
CCB_MEM, /* memory for command control block */
};
#define PM8001_EVENT_LOG_SIZE (128 * 1024)
/*error code*/
enum mpi_err {
MPI_IO_STATUS_SUCCESS = 0x0,
MPI_IO_STATUS_BUSY = 0x01,
MPI_IO_STATUS_FAIL = 0x02,
};
/**
* Phy Control constants
*/
enum phy_control_type {
PHY_LINK_RESET = 0x01,
PHY_HARD_RESET = 0x02,
PHY_NOTIFY_ENABLE_SPINUP = 0x10,
};
enum pm8001_hba_info_flags {
PM8001F_INIT_TIME = (1U << 0),
PM8001F_RUN_TIME = (1U << 1),
};
#endif
drivers/scsi/pm8001/pm8001_hwi.c 0 → 100644
View file @ dbf9bfe6
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/scsi/pm8001/pm8001_hwi.h 0 → 100644
View file @ dbf9bfe6
/*
* PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
*
* Copyright (c) 2008-2009 USI Co., Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
*/
#ifndef _PMC8001_REG_H_
#define _PMC8001_REG_H_
#include <linux/types.h>
#include <scsi/libsas.h>
/* for Request Opcode of IOMB */
#define OPC_INB_ECHO 1 /* 0x000 */
#define OPC_INB_PHYSTART 4 /* 0x004 */
#define OPC_INB_PHYSTOP 5 /* 0x005 */
#define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
#define OPC_INB_SSPINITMSTART 7 /* 0x007 */
#define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */
#define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
#define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
#define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
#define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */
#define OPC_INB_SSPINIEXTEDCIOSTART 13 /* 0x00D */
#define OPC_INB_SSPTGTEDCIOSTART 14 /* 0x00E */
#define OPC_INB_SSP_ABORT 15 /* 0x00F */
#define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */
#define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */
#define OPC_INB_SMP_REQUEST 18 /* 0x012 */
/* SMP_RESPONSE is removed */
#define OPC_INB_SMP_RESPONSE 19 /* 0x013 */
#define OPC_INB_SMP_ABORT 20 /* 0x014 */
#define OPC_INB_REG_DEV 22 /* 0x016 */
#define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */
#define OPC_INB_SATA_ABORT 24 /* 0x018 */
#define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */
#define OPC_INB_GET_DEV_INFO 26 /* 0x01A */
#define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */
#define OPC_INB_GPIO 34 /* 0x022 */
#define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */
#define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */
#define OPC_INB_SAS_HW_EVENT_ACK 37 /* 0x025 */
#define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */
#define OPC_INB_PORT_CONTROL 39 /* 0x027 */
#define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */
#define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */
#define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */
#define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */
#define OPC_INB_SET_DEV_INFO 44 /* 0x02C */
#define OPC_INB_SAS_RE_INITIALIZE 45 /* 0x02D */
/* for Response Opcode of IOMB */
#define OPC_OUB_ECHO 1 /* 0x001 */
#define OPC_OUB_HW_EVENT 4 /* 0x004 */
#define OPC_OUB_SSP_COMP 5 /* 0x005 */
#define OPC_OUB_SMP_COMP 6 /* 0x006 */
#define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */
#define OPC_OUB_DEV_REGIST 10 /* 0x00A */
#define OPC_OUB_DEREG_DEV 11 /* 0x00B */
#define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */
#define OPC_OUB_SATA_COMP 13 /* 0x00D */
#define OPC_OUB_SATA_EVENT 14 /* 0x00E */
#define OPC_OUB_SSP_EVENT 15 /* 0x00F */
#define OPC_OUB_DEV_HANDLE_ARRIV 16 /* 0x010 */
/* SMP_RECEIVED Notification is removed */
#define OPC_OUB_SMP_RECV_EVENT 17 /* 0x011 */
#define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */
#define OPC_OUB_DEV_INFO 19 /* 0x013 */
#define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */
#define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */
#define OPC_OUB_GPIO_EVENT 23 /* 0x017 */
#define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */
#define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */
#define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */
#define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */
#define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
#define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */
#define OPC_OUB_SAS_HW_EVENT_ACK 31 /* 0x01F */
#define OPC_OUB_PORT_CONTROL 32 /* 0x020 */
#define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */
#define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */
#define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */
#define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */
#define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */
#define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */
#define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */
#define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */
#define OPC_OUB_SAS_RE_INITIALIZE 41 /* 0x029 */
/* for phy start*/
#define SPINHOLD_DISABLE (0x00 << 14)
#define SPINHOLD_ENABLE (0x01 << 14)
#define LINKMODE_SAS (0x01 << 12)
#define LINKMODE_DSATA (0x02 << 12)
#define LINKMODE_AUTO (0x03 << 12)
#define LINKRATE_15 (0x01 << 8)
#define LINKRATE_30 (0x02 << 8)
#define LINKRATE_60 (0x04 << 8)
struct mpi_msg_hdr{
__le32 header; /* Bits [11:0] - Message operation code */
/* Bits [15:12] - Message Category */
/* Bits [21:16] - Outboundqueue ID for the
operation completion message */
/* Bits [23:22] - Reserved */
/* Bits [28:24] - Buffer Count, indicates how
many buffer are allocated for the massage */
/* Bits [30:29] - Reserved */
/* Bits [31] - Message Valid bit */
} __attribute__((packed, aligned(4)));
/*
* brief the data structure of PHY Start Command
* use to describe enable the phy (64 bytes)
*/
struct phy_start_req {
__le32 tag;
__le32 ase_sh_lm_slr_phyid;
struct sas_identify_frame sas_identify;
u32 reserved[5];
} __attribute__((packed, aligned(4)));
/*
* brief the data structure of PHY Start Command
* use to disable the phy (64 bytes)
*/
struct phy_stop_req {
__le32 tag;
__le32 phy_id;
u32 reserved[13];
} __attribute__((packed, aligned(4)));
/* set device bits fis - device to host */
struct set_dev_bits_fis {
u8 fis_type; /* 0xA1*/
u8 n_i_pmport;
/* b7 : n Bit. Notification bit. If set device needs attention. */
/* b6 : i Bit. Interrupt Bit */
/* b5-b4: reserved2 */
/* b3-b0: PM Port */
u8 status;
u8 error;
u32 _r_a;
} __attribute__ ((packed));
/* PIO setup FIS - device to host */
struct pio_setup_fis {
u8 fis_type; /* 0x5f */
u8 i_d_pmPort;
/* b7 : reserved */
/* b6 : i bit. Interrupt bit */
/* b5 : d bit. data transfer direction. set to 1 for device to host
xfer */
/* b4 : reserved */
/* b3-b0: PM Port */
u8 status;
u8 error;
u8 lbal;
u8 lbam;
u8 lbah;
u8 device;
u8 lbal_exp;
u8 lbam_exp;
u8 lbah_exp;
u8 _r_a;
u8 sector_count;
u8 sector_count_exp;
u8 _r_b;
u8 e_status;
u8 _r_c[2];
u8 transfer_count;
} __attribute__ ((packed));
/*
* brief the data structure of SATA Completion Response
* use to discribe the sata task response (64 bytes)
*/
struct sata_completion_resp {
__le32 tag;
__le32 status;
__le32 param;
u32 sata_resp[12];
} __attribute__((packed, aligned(4)));
/*
* brief the data structure of SAS HW Event Notification
* use to alert the host about the hardware event(64 bytes)
*/
struct hw_event_resp {
__le32 lr_evt_status_phyid_portid;
__le32 evt_param;
__le32 npip_portstate;
struct sas_identify_frame sas_identify;
struct dev_to_host_fis sata_fis;
} __attribute__((packed, aligned(4)));
/*
* brief the data structure of REGISTER DEVICE Command
* use to describe MPI REGISTER DEVICE Command (64 bytes)
*/
struct reg_dev_req {
__le32 tag;
__le32 phyid_portid;
__le32 dtype_dlr_retry;
__le32 firstburstsize_ITNexustimeout;
u32 sas_addr_hi;
u32 sas_addr_low;
__le32 upper_device_id;
u32 reserved[8];
} __attribute__((packed, aligned(4)));
/*
* brief the data structure of DEREGISTER DEVICE Command
* use to request spc to remove all internal resources associated
* with the device id (64 bytes)
*/
struct dereg_dev_req {
__le32 tag;
__le32 device_id;
u32 reserved[13];
} __attribute__((packed, aligned(4)));
/*
* brief the data structure of DEVICE_REGISTRATION Response
* use to notify the completion of the device registration (64 bytes)
*/
struct dev_reg_resp {
__le32 tag;
__le32 status;
__le32 device_id;
u32 reserved[12];
} __attribute__((packed, aligned(4)));
/*
* brief the data structure of Local PHY Control Command
* use to issue PHY CONTROL to local phy (64 bytes)
*/
struct local_phy_ctl_req {
__le32 tag;
__le32 phyop_phyid;
u32 reserved1[13];
} __attribute__((packed, aligned(4)));
/**
* brief the data structure of Local Phy Control Response
* use to describe MPI Local Phy Control Response (64 bytes)
*/
struct local_phy_ctl_resp {
__le32 tag;
__le32 phyop_phyid;
__le32 status;
u32 reserved[12];
} __attribute__((packed, aligned(4)));
#define OP_BITS 0x0000FF00
#define ID_BITS 0x0000000F
/*
* brief the data structure of PORT Control Command
* use to control port properties (64 bytes)
*/
struct port_ctl_req {
__le32 tag;
__le32 portop_portid;
__le32 param0;
__le32 param1;
u32 reserved1[11];
} __attribute__((packed, aligned(4)));
/*
* brief the data structure of HW Event Ack Command
* use to acknowledge receive HW event (64 bytes)
*/
struct hw_event_ack_req {
__le32 tag;
__le32 sea_phyid_portid;
__le32 param0;
__le32 param1;
u32 reserved1[11];
} __attribute__((packed, aligned(4)));
/*
* brief the data structure of SSP Completion Response
* use to indicate a SSP Completion (n bytes)
*/
struct ssp_completion_resp {
__le32 tag;
__le32 status;
__le32 param;
__le32 ssptag_rescv_rescpad;
struct ssp_response_iu ssp_resp_iu;
__le32 residual_count;
} __attribute__((packed, aligned(4)));
#define SSP_RESCV_BIT 0x00010000
/*
* brief the data structure of SATA EVNET esponse
* use to indicate a SATA Completion (64 bytes)
*/
struct sata_event_resp {
__le32 tag;
__le32 event;
__le32 port_id;
__le32 device_id;
u32 reserved[11];
} __attribute__((packed, aligned(4)));
/*
* brief the data structure of SSP EVNET esponse
* use to indicate a SSP Completion (64 bytes)
*/
struct ssp_event_resp {
__le32 tag;
__le32 event;
__le32 port_id;
__le32 device_id;
u32 reserved[11];
} __attribute__((packed, aligned(4)));
/**
* brief the data structure of General Event Notification Response
* use to describe MPI General Event Notification Response (64 bytes)
*/
struct general_event_resp {
__le32 status;
__le32 inb_IOMB_payload[14];
} __attribute__((packed, aligned(4)));
#define GENERAL_EVENT_PAYLOAD 14
#define OPCODE_BITS 0x00000fff
/*
* brief the data structure of SMP Request Command
* use to describe MPI SMP REQUEST Command (64 bytes)
*/
struct smp_req {
__le32 tag;
__le32 device_id;
__le32 len_ip_ir;
/* Bits [0] - Indirect response */
/* Bits [1] - Indirect Payload */
/* Bits [15:2] - Reserved */
/* Bits [23:16] - direct payload Len */
/* Bits [31:24] - Reserved */
u8 smp_req16[16];
union {
u8 smp_req[32];
struct {
__le64 long_req_addr;/* sg dma address, LE */
__le32 long_req_size;/* LE */
u32 _r_a;
__le64 long_resp_addr;/* sg dma address, LE */
__le32 long_resp_size;/* LE */
u32 _r_b;
} long_smp_req;/* sequencer extension */
};
} __attribute__((packed, aligned(4)));
/*
* brief the data structure of SMP Completion Response
* use to describe MPI SMP Completion Response (64 bytes)
*/
struct smp_completion_resp {
__le32 tag;
__le32 status;
__le32 param;
__le32 _r_a[12];
} __attribute__((packed, aligned(4)));
/*
*brief the data structure of SSP SMP SATA Abort Command
* use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
*/
struct task_abort_req {
__le32 tag;
__le32 device_id;
__le32 tag_to_abort;
__le32 abort_all;
u32 reserved[11];
} __attribute__((packed, aligned(4)));
/* These flags used for SSP SMP & SATA Abort */
#define ABORT_MASK 0x3
#define ABORT_SINGLE 0x0
#define ABORT_ALL 0x1
/**
* brief the data structure of SSP SATA SMP Abort Response
* use to describe SSP SMP & SATA Abort Response ( 64 bytes)
*/
struct task_abort_resp {
__le32 tag;
__le32 status;
__le32 scp;
u32 reserved[12];
} __attribute__((packed, aligned(4)));
/**
* brief the data structure of SAS Diagnostic Start/End Command
* use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
*/
struct sas_diag_start_end_req {
__le32 tag;
__le32 operation_phyid;
u32 reserved[13];
} __attribute__((packed, aligned(4)));
/**
* brief the data structure of SAS Diagnostic Execute Command
* use to describe MPI SAS Diagnostic Execute Command (64 bytes)
*/
struct sas_diag_execute_req{
__le32 tag;
__le32 cmdtype_cmddesc_phyid;
__le32 pat1_pat2;
__le32 threshold;
__le32 codepat_errmsk;
__le32 pmon;
__le32 pERF1CTL;
u32 reserved[8];
} __attribute__((packed, aligned(4)));
#define SAS_DIAG_PARAM_BYTES 24
/*
* brief the data structure of Set Device State Command
* use to describe MPI Set Device State Command (64 bytes)
*/
struct set_dev_state_req {
__le32 tag;
__le32 device_id;
__le32 nds;
u32 reserved[12];
} __attribute__((packed, aligned(4)));
/*
* brief the data structure of SATA Start Command
* use to describe MPI SATA IO Start Command (64 bytes)
*/
struct sata_start_req {
__le32 tag;
__le32 device_id;
__le32 data_len;
__le32 ncqtag_atap_dir_m;
struct host_to_dev_fis sata_fis;
u32 reserved1;
u32 reserved2;
u32 addr_low;
u32 addr_high;
__le32 len;
__le32 esgl;
} __attribute__((packed, aligned(4)));
/**
* brief the data structure of SSP INI TM Start Command
* use to describe MPI SSP INI TM Start Command (64 bytes)
*/
struct ssp_ini_tm_start_req {
__le32 tag;
__le32 device_id;
__le32 relate_tag;
__le32 tmf;
u8 lun[8];
__le32 ds_ads_m;
u32 reserved[8];
} __attribute__((packed, aligned(4)));
struct ssp_info_unit {
u8 lun[8];/* SCSI Logical Unit Number */
u8 reserved1;/* reserved */
u8 efb_prio_attr;
/* B7 : enabledFirstBurst */
/* B6-3 : taskPriority */
/* B2-0 : taskAttribute */
u8 reserved2; /* reserved */
u8 additional_cdb_len;
/* B7-2 : additional_cdb_len */
/* B1-0 : reserved */
u8 cdb[16];/* The SCSI CDB up to 16 bytes length */
} __attribute__((packed, aligned(4)));
/**
* brief the data structure of SSP INI IO Start Command
* use to describe MPI SSP INI IO Start Command (64 bytes)
*/
struct ssp_ini_io_start_req {
__le32 tag;
__le32 device_id;
__le32 data_len;
__le32 dir_m_tlr;
struct ssp_info_unit ssp_iu;
__le32 addr_low;
__le32 addr_high;
__le32 len;
__le32 esgl;
} __attribute__((packed, aligned(4)));
/**
* brief the data structure of Firmware download
* use to describe MPI FW DOWNLOAD Command (64 bytes)
*/
struct fw_flash_Update_req {
__le32 tag;
__le32 cur_image_offset;
__le32 cur_image_len;
__le32 total_image_len;
u32 reserved0[7];
__le32 sgl_addr_lo;
__le32 sgl_addr_hi;
__le32 len;
__le32 ext_reserved;
} __attribute__((packed, aligned(4)));
#define FWFLASH_IOMB_RESERVED_LEN 0x07
/**
* brief the data structure of FW_FLASH_UPDATE Response
* use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
*
*/
struct fw_flash_Update_resp {
dma_addr_t tag;
__le32 status;
u32 reserved[13];
} __attribute__((packed, aligned(4)));
/**
* brief the data structure of Get NVM Data Command
* use to get data from NVM in HBA(64 bytes)
*/
struct get_nvm_data_req {
__le32 tag;
__le32 len_ir_vpdd;
__le32 vpd_offset;
u32 reserved[8];
__le32 resp_addr_lo;
__le32 resp_addr_hi;
__le32 resp_len;
u32 reserved1;
} __attribute__((packed, aligned(4)));
struct set_nvm_data_req {
__le32 tag;
__le32 len_ir_vpdd;
__le32 vpd_offset;
u32 reserved[8];
__le32 resp_addr_lo;
__le32 resp_addr_hi;
__le32 resp_len;
u32 reserved1;
} __attribute__((packed, aligned(4)));
#define TWI_DEVICE 0x0
#define C_SEEPROM 0x1
#define VPD_FLASH 0x4
#define AAP1_RDUMP 0x5
#define IOP_RDUMP 0x6
#define EXPAN_ROM 0x7
#define IPMode 0x80000000
#define NVMD_TYPE 0x0000000F
#define NVMD_STAT 0x0000FFFF
#define NVMD_LEN 0xFF000000
/**
* brief the data structure of Get NVMD Data Response
* use to describe MPI Get NVMD Data Response (64 bytes)
*/
struct get_nvm_data_resp {
__le32 tag;
__le32 ir_tda_bn_dps_das_nvm;
__le32 dlen_status;
__le32 nvm_data[12];
} __attribute__((packed, aligned(4)));
/**
* brief the data structure of SAS Diagnostic Start/End Response
* use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
*
*/
struct sas_diag_start_end_resp {
__le32 tag;
__le32 status;
u32 reserved[13];
} __attribute__((packed, aligned(4)));
/**
* brief the data structure of SAS Diagnostic Execute Response
* use to describe MPI SAS Diagnostic Execute Response (64 bytes)
*
*/
struct sas_diag_execute_resp {
__le32 tag;
__le32 cmdtype_cmddesc_phyid;
__le32 Status;
__le32 ReportData;
u32 reserved[11];
} __attribute__((packed, aligned(4)));
/**
* brief the data structure of Set Device State Response
* use to describe MPI Set Device State Response (64 bytes)
*
*/
struct set_dev_state_resp {
__le32 tag;
__le32 status;
__le32 device_id;
__le32 pds_nds;
u32 reserved[11];
} __attribute__((packed, aligned(4)));
#define NDS_BITS 0x0F
#define PDS_BITS 0xF0
/*
* HW Events type
*/
#define HW_EVENT_RESET_START 0x01
#define HW_EVENT_CHIP_RESET_COMPLETE 0x02
#define HW_EVENT_PHY_STOP_STATUS 0x03
#define HW_EVENT_SAS_PHY_UP 0x04
#define HW_EVENT_SATA_PHY_UP 0x05
#define HW_EVENT_SATA_SPINUP_HOLD 0x06
#define HW_EVENT_PHY_DOWN 0x07
#define HW_EVENT_PORT_INVALID 0x08
#define HW_EVENT_BROADCAST_CHANGE 0x09
#define HW_EVENT_PHY_ERROR 0x0A
#define HW_EVENT_BROADCAST_SES 0x0B
#define HW_EVENT_INBOUND_CRC_ERROR 0x0C
#define HW_EVENT_HARD_RESET_RECEIVED 0x0D
#define HW_EVENT_MALFUNCTION 0x0E
#define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
#define HW_EVENT_BROADCAST_EXP 0x10
#define HW_EVENT_PHY_START_STATUS 0x11
#define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
#define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
#define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
#define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
#define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
#define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
#define HW_EVENT_PORT_RECOVER 0x18
#define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
#define HW_EVENT_PORT_RESET_COMPLETE 0x20
#define EVENT_BROADCAST_ASYNCH_EVENT 0x21
/* port state */
#define PORT_NOT_ESTABLISHED 0x00
#define PORT_VALID 0x01
#define PORT_LOSTCOMM 0x02
#define PORT_IN_RESET 0x04
#define PORT_INVALID 0x08
/*
* SSP/SMP/SATA IO Completion Status values
*/
#define IO_SUCCESS 0x00
#define IO_ABORTED 0x01
#define IO_OVERFLOW 0x02
#define IO_UNDERFLOW 0x03
#define IO_FAILED 0x04
#define IO_ABORT_RESET 0x05
#define IO_NOT_VALID 0x06
#define IO_NO_DEVICE 0x07
#define IO_ILLEGAL_PARAMETER 0x08
#define IO_LINK_FAILURE 0x09
#define IO_PROG_ERROR 0x0A
#define IO_EDC_IN_ERROR 0x0B
#define IO_EDC_OUT_ERROR 0x0C
#define IO_ERROR_HW_TIMEOUT 0x0D
#define IO_XFER_ERROR_BREAK 0x0E
#define IO_XFER_ERROR_PHY_NOT_READY 0x0F
#define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
#define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
#define IO_OPEN_CNX_ERROR_BREAK 0x12
#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
#define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
#define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
#define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
#define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
#define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
#define IO_XFER_ERROR_NAK_RECEIVED 0x19
#define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
#define IO_XFER_ERROR_PEER_ABORTED 0x1B
#define IO_XFER_ERROR_RX_FRAME 0x1C
#define IO_XFER_ERROR_DMA 0x1D
#define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
#define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
#define IO_XFER_ERROR_SATA 0x20
#define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
#define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
#define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
#define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
#define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
#define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
#define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
#define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
#define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
#define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
#define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
#define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
#define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
#define IO_XFER_CMD_FRAME_ISSUED 0x36
#define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
#define IO_PORT_IN_RESET 0x38
#define IO_DS_NON_OPERATIONAL 0x39
#define IO_DS_IN_RECOVERY 0x3A
#define IO_TM_TAG_NOT_FOUND 0x3B
#define IO_XFER_PIO_SETUP_ERROR 0x3C
#define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
#define IO_DS_IN_ERROR 0x3E
#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
#define IO_ABORT_IN_PROGRESS 0x40
#define IO_ABORT_DELAYED 0x41
#define IO_INVALID_LENGTH 0x42
/* WARNING: This error code must always be the last number.
* If you add error code, modify this code also
* It is used as an index
*/
#define IO_ERROR_UNKNOWN_GENERIC 0x43
/* MSGU CONFIGURATION TABLE*/
#define SPC_MSGU_CFG_TABLE_UPDATE 0x01/* Inbound doorbell bit0 */
#define SPC_MSGU_CFG_TABLE_RESET 0x02/* Inbound doorbell bit1 */
#define SPC_MSGU_CFG_TABLE_FREEZE 0x04/* Inbound doorbell bit2 */
#define SPC_MSGU_CFG_TABLE_UNFREEZE 0x08/* Inbound doorbell bit4 */
#define MSGU_IBDB_SET 0x04
#define MSGU_HOST_INT_STATUS 0x08
#define MSGU_HOST_INT_MASK 0x0C
#define MSGU_IOPIB_INT_STATUS 0x18
#define MSGU_IOPIB_INT_MASK 0x1C
#define MSGU_IBDB_CLEAR 0x20/* RevB - Host not use */
#define MSGU_MSGU_CONTROL 0x24
#define MSGU_ODR 0x3C/* RevB */
#define MSGU_ODCR 0x40/* RevB */
#define MSGU_SCRATCH_PAD_0 0x44
#define MSGU_SCRATCH_PAD_1 0x48
#define MSGU_SCRATCH_PAD_2 0x4C
#define MSGU_SCRATCH_PAD_3 0x50
#define MSGU_HOST_SCRATCH_PAD_0 0x54
#define MSGU_HOST_SCRATCH_PAD_1 0x58
#define MSGU_HOST_SCRATCH_PAD_2 0x5C
#define MSGU_HOST_SCRATCH_PAD_3 0x60
#define MSGU_HOST_SCRATCH_PAD_4 0x64
#define MSGU_HOST_SCRATCH_PAD_5 0x68
#define MSGU_HOST_SCRATCH_PAD_6 0x6C
#define MSGU_HOST_SCRATCH_PAD_7 0x70
#define MSGU_ODMR 0x74/* RevB */
/* bit definition for ODMR register */
#define ODMR_MASK_ALL 0xFFFFFFFF/* mask all
interrupt vector */
#define ODMR_CLEAR_ALL 0/* clear all
interrupt vector */
/* bit definition for ODCR register */
#define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all
interrupt vector*/
/* MSIX Interupts */
#define MSIX_TABLE_OFFSET 0x2000
#define MSIX_TABLE_ELEMENT_SIZE 0x10
#define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
#define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET)
#define MSIX_INTERRUPT_DISABLE 0x1
#define MSIX_INTERRUPT_ENABLE 0x0
/* state definition for Scratch Pad1 register */
#define SCRATCH_PAD1_POR 0x00 /* power on reset state */
#define SCRATCH_PAD1_SFR 0x01 /* soft reset state */
#define SCRATCH_PAD1_ERR 0x02 /* error state */
#define SCRATCH_PAD1_RDY 0x03 /* ready state */
#define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */
#define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */
#define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1
Mask, bit1-0 State, bit2 Soft Reset, bit3 FW RDY for Soft Reset */
#define SCRATCH_PAD1_RESERVED 0x000003F8 /* Scratch Pad1
Reserved bit 3 to 9 */
/* state definition for Scratch Pad2 register */
#define SCRATCH_PAD2_POR 0x00 /* power on state */
#define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
#define SCRATCH_PAD2_ERR 0x02 /* error state */
#define SCRATCH_PAD2_RDY 0x03 /* ready state */
#define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset flag*/
#define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
#define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2
Mask, bit1-0 State */
#define SCRATCH_PAD2_RESERVED 0x000003FC /* Scratch Pad1
Reserved bit 2 to 9 */
#define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */
#define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */
/* main configuration offset - byte offset */
#define MAIN_SIGNATURE_OFFSET 0x00/* DWORD 0x00 */
#define MAIN_INTERFACE_REVISION 0x04/* DWORD 0x01 */
#define MAIN_FW_REVISION 0x08/* DWORD 0x02 */
#define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C/* DWORD 0x03 */
#define MAIN_MAX_SGL_OFFSET 0x10/* DWORD 0x04 */
#define MAIN_CNTRL_CAP_OFFSET 0x14/* DWORD 0x05 */
#define MAIN_GST_OFFSET 0x18/* DWORD 0x06 */
#define MAIN_IBQ_OFFSET 0x1C/* DWORD 0x07 */
#define MAIN_OBQ_OFFSET 0x20/* DWORD 0x08 */
#define MAIN_IQNPPD_HPPD_OFFSET 0x24/* DWORD 0x09 */
#define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28/* DWORD 0x0A */
#define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C/* DWORD 0x0B */
#define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30/* DWORD 0x0C */
#define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34/* DWORD 0x0D */
#define MAIN_TITNX_EVENT_PID03_OFFSET 0x38/* DWORD 0x0E */
#define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C/* DWORD 0x0F */
#define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40/* DWORD 0x10 */
#define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44/* DWORD 0x11 */
#define MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48/* DWORD 0x12 */
#define MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C/* DWORD 0x13 */
#define MAIN_EVENT_LOG_ADDR_HI 0x50/* DWORD 0x14 */
#define MAIN_EVENT_LOG_ADDR_LO 0x54/* DWORD 0x15 */
#define MAIN_EVENT_LOG_BUFF_SIZE 0x58/* DWORD 0x16 */
#define MAIN_EVENT_LOG_OPTION 0x5C/* DWORD 0x17 */
#define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60/* DWORD 0x18 */
#define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64/* DWORD 0x19 */
#define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68/* DWORD 0x1A */
#define MAIN_IOP_EVENT_LOG_OPTION 0x6C/* DWORD 0x1B */
#define MAIN_FATAL_ERROR_INTERRUPT 0x70/* DWORD 0x1C */
#define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74/* DWORD 0x1D */
#define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78/* DWORD 0x1E */
#define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C/* DWORD 0x1F */
#define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80/* DWORD 0x20 */
#define MAIN_HDA_FLAGS_OFFSET 0x84/* DWORD 0x21 */
#define MAIN_ANALOG_SETUP_OFFSET 0x88/* DWORD 0x22 */
/* Gereral Status Table offset - byte offset */
#define GST_GSTLEN_MPIS_OFFSET 0x00
#define GST_IQ_FREEZE_STATE0_OFFSET 0x04
#define GST_IQ_FREEZE_STATE1_OFFSET 0x08
#define GST_MSGUTCNT_OFFSET 0x0C
#define GST_IOPTCNT_OFFSET 0x10
#define GST_PHYSTATE_OFFSET 0x18
#define GST_PHYSTATE0_OFFSET 0x18
#define GST_PHYSTATE1_OFFSET 0x1C
#define GST_PHYSTATE2_OFFSET 0x20
#define GST_PHYSTATE3_OFFSET 0x24
#define GST_PHYSTATE4_OFFSET 0x28
#define GST_PHYSTATE5_OFFSET 0x2C
#define GST_PHYSTATE6_OFFSET 0x30
#define GST_PHYSTATE7_OFFSET 0x34
#define GST_RERRINFO_OFFSET 0x44
/* General Status Table - MPI state */
#define GST_MPI_STATE_UNINIT 0x00
#define GST_MPI_STATE_INIT 0x01
#define GST_MPI_STATE_TERMINATION 0x02
#define GST_MPI_STATE_ERROR 0x03
#define GST_MPI_STATE_MASK 0x07
#define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
#define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
/* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
#define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
#define PCIE_EVENT_INTERRUPT 0x003044
#define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
#define PCIE_ERROR_INTERRUPT 0x00304C
/* signature defintion for host scratch pad0 register */
#define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
/* Signature for Soft Reset */
/* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
#define SPC_REG_RESET 0x000000/* reset register */
/* bit difination for SPC_RESET register */
#define SPC_REG_RESET_OSSP 0x00000001
#define SPC_REG_RESET_RAAE 0x00000002
#define SPC_REG_RESET_PCS_SPBC 0x00000004
#define SPC_REG_RESET_PCS_IOP_SS 0x00000008
#define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
#define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
#define SPC_REG_RESET_PCS_LM 0x00000040
#define SPC_REG_RESET_PCS 0x00000080
#define SPC_REG_RESET_GSM 0x00000100
#define SPC_REG_RESET_DDR2 0x00010000
#define SPC_REG_RESET_BDMA_CORE 0x00020000
#define SPC_REG_RESET_BDMA_SXCBI 0x00040000
#define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
#define SPC_REG_RESET_PCIE_PWR 0x00100000
#define SPC_REG_RESET_PCIE_SFT 0x00200000
#define SPC_REG_RESET_PCS_SXCBI 0x00400000
#define SPC_REG_RESET_LMS_SXCBI 0x00800000
#define SPC_REG_RESET_PMIC_SXCBI 0x01000000
#define SPC_REG_RESET_PMIC_CORE 0x02000000
#define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
#define SPC_REG_RESET_DEVICE 0x80000000
/* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
#define SPC_IBW_AXI_TRANSLATION_LOW 0x003258
#define MBIC_AAP1_ADDR_BASE 0x060000
#define MBIC_IOP_ADDR_BASE 0x070000
#define GSM_ADDR_BASE 0x0700000
/* Dynamic map through Bar4 - 0x00700000 */
#define GSM_CONFIG_RESET 0x00000000
#define RAM_ECC_DB_ERR 0x00000018
#define GSM_READ_ADDR_PARITY_INDIC 0x00000058
#define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
#define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
#define GSM_READ_ADDR_PARITY_CHECK 0x00000038
#define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
#define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
#define RB6_ACCESS_REG 0x6A0000
#define HDAC_EXEC_CMD 0x0002
#define HDA_C_PA 0xcb
#define HDA_SEQ_ID_BITS 0x00ff0000
#define HDA_GSM_OFFSET_BITS 0x00FFFFFF
#define MBIC_AAP1_ADDR_BASE 0x060000
#define MBIC_IOP_ADDR_BASE 0x070000
#define GSM_ADDR_BASE 0x0700000
#define SPC_TOP_LEVEL_ADDR_BASE 0x000000
#define GSM_CONFIG_RESET_VALUE 0x00003b00
#define GPIO_ADDR_BASE 0x00090000
#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
/* RB6 offset */
#define SPC_RB6_OFFSET 0x80C0
/* Magic number of soft reset for RB6 */
#define RB6_MAGIC_NUMBER_RST 0x1234
/* Device Register status */
#define DEVREG_SUCCESS 0x00
#define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
#define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
#define DEVREG_FAILURE_INVALID_PHY_ID 0x03
#define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
#define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
#define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
#define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
#endif
drivers/scsi/pm8001/pm8001_init.c 0 → 100644
View file @ dbf9bfe6
/*
* PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
*
* Copyright (c) 2008-2009 USI Co., Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
*/
#include "pm8001_sas.h"
#include "pm8001_chips.h"
static struct scsi_transport_template *pm8001_stt;
static const struct pm8001_chip_info pm8001_chips[] = {
[chip_8001] = { 8, &pm8001_8001_dispatch,},
};
static int pm8001_id;
LIST_HEAD(hba_list);
/**
* The main structure which LLDD must register for scsi core.
*/
static struct scsi_host_template pm8001_sht = {
.module = THIS_MODULE,
.name = DRV_NAME,
.queuecommand = sas_queuecommand,
.target_alloc = sas_target_alloc,
.slave_configure = pm8001_slave_configure,
.slave_destroy = sas_slave_destroy,
.scan_finished = pm8001_scan_finished,
.scan_start = pm8001_scan_start,
.change_queue_depth = sas_change_queue_depth,
.change_queue_type = sas_change_queue_type,
.bios_param = sas_bios_param,
.can_queue = 1,
.cmd_per_lun = 1,
.this_id = -1,
.sg_tablesize = SG_ALL,
.max_sectors = SCSI_DEFAULT_MAX_SECTORS,
.use_clustering = ENABLE_CLUSTERING,
.eh_device_reset_handler = sas_eh_device_reset_handler,
.eh_bus_reset_handler = sas_eh_bus_reset_handler,
.slave_alloc = pm8001_slave_alloc,
.target_destroy = sas_target_destroy,
.ioctl = sas_ioctl,
.shost_attrs = pm8001_host_attrs,
};
/**
* Sas layer call this function to execute specific task.
*/
static struct sas_domain_function_template pm8001_transport_ops = {
.lldd_dev_found = pm8001_dev_found,
.lldd_dev_gone = pm8001_dev_gone,
.lldd_execute_task = pm8001_queue_command,
.lldd_control_phy = pm8001_phy_control,
.lldd_abort_task = pm8001_abort_task,
.lldd_abort_task_set = pm8001_abort_task_set,
.lldd_clear_aca = pm8001_clear_aca,
.lldd_clear_task_set = pm8001_clear_task_set,
.lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
.lldd_lu_reset = pm8001_lu_reset,
.lldd_query_task = pm8001_query_task,
};
/**
*pm8001_phy_init - initiate our adapter phys
*@pm8001_ha: our hba structure.
*@phy_id: phy id.
*/
static void __devinit pm8001_phy_init(struct pm8001_hba_info *pm8001_ha,
int phy_id)
{
struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
struct asd_sas_phy *sas_phy = &phy->sas_phy;
phy->phy_state = 0;
phy->pm8001_ha = pm8001_ha;
sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
sas_phy->class = SAS;
sas_phy->iproto = SAS_PROTOCOL_ALL;
sas_phy->tproto = 0;
sas_phy->type = PHY_TYPE_PHYSICAL;
sas_phy->role = PHY_ROLE_INITIATOR;
sas_phy->oob_mode = OOB_NOT_CONNECTED;
sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
sas_phy->id = phy_id;
sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
sas_phy->frame_rcvd = &phy->frame_rcvd[0];
sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
sas_phy->lldd_phy = phy;
}
/**
*pm8001_free - free hba
*@pm8001_ha: our hba structure.
*
*/
static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
{
int i;
struct pm8001_wq *wq;
if (!pm8001_ha)
return;
for (i = 0; i < USI_MAX_MEMCNT; i++) {
if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
pci_free_consistent(pm8001_ha->pdev,
pm8001_ha->memoryMap.region[i].element_size,
pm8001_ha->memoryMap.region[i].virt_ptr,
pm8001_ha->memoryMap.region[i].phys_addr);
}
}
PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
if (pm8001_ha->shost)
scsi_host_put(pm8001_ha->shost);
list_for_each_entry(wq, &pm8001_ha->wq_list, entry)
cancel_delayed_work(&wq->work_q);
kfree(pm8001_ha->tags);
kfree(pm8001_ha);
}
#ifdef PM8001_USE_TASKLET
static void pm8001_tasklet(unsigned long opaque)
{
struct pm8001_hba_info *pm8001_ha;
pm8001_ha = (struct pm8001_hba_info *)opaque;;
if (unlikely(!pm8001_ha))
BUG_ON(1);
PM8001_CHIP_DISP->isr(pm8001_ha);
}
#endif
/**
* pm8001_interrupt - when HBA originate a interrupt,we should invoke this
* dispatcher to handle each case.
* @irq: irq number.
* @opaque: the passed general host adapter struct
*/
static irqreturn_t pm8001_interrupt(int irq, void *opaque)
{
struct pm8001_hba_info *pm8001_ha;
irqreturn_t ret = IRQ_HANDLED;
struct sas_ha_struct *sha = opaque;
pm8001_ha = sha->lldd_ha;
if (unlikely(!pm8001_ha))
return IRQ_NONE;
if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
return IRQ_NONE;
#ifdef PM8001_USE_TASKLET
tasklet_schedule(&pm8001_ha->tasklet);
#else
ret = PM8001_CHIP_DISP->isr(pm8001_ha);
#endif
return ret;
}
/**
* pm8001_alloc - initiate our hba structure and 6 DMAs area.
* @pm8001_ha:our hba structure.
*
*/
static int __devinit pm8001_alloc(struct pm8001_hba_info *pm8001_ha)
{
int i;
spin_lock_init(&pm8001_ha->lock);
for (i = 0; i < pm8001_ha->chip->n_phy; i++)
pm8001_phy_init(pm8001_ha, i);
pm8001_ha->tags = kmalloc(sizeof(*pm8001_ha->tags)*PM8001_MAX_DEVICES,
GFP_KERNEL);
/* MPI Memory region 1 for AAP Event Log for fw */
pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
pm8001_ha->memoryMap.region[AAP1].alignment = 32;
/* MPI Memory region 2 for IOP Event Log for fw */
pm8001_ha->memoryMap.region[IOP].num_elements = 1;
pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
pm8001_ha->memoryMap.region[IOP].alignment = 32;
/* MPI Memory region 3 for consumer Index of inbound queues */
pm8001_ha->memoryMap.region[CI].num_elements = 1;
pm8001_ha->memoryMap.region[CI].element_size = 4;
pm8001_ha->memoryMap.region[CI].total_len = 4;
pm8001_ha->memoryMap.region[CI].alignment = 4;
/* MPI Memory region 4 for producer Index of outbound queues */
pm8001_ha->memoryMap.region[PI].num_elements = 1;
pm8001_ha->memoryMap.region[PI].element_size = 4;
pm8001_ha->memoryMap.region[PI].total_len = 4;
pm8001_ha->memoryMap.region[PI].alignment = 4;
/* MPI Memory region 5 inbound queues */
pm8001_ha->memoryMap.region[IB].num_elements = 256;
pm8001_ha->memoryMap.region[IB].element_size = 64;
pm8001_ha->memoryMap.region[IB].total_len = 256 * 64;
pm8001_ha->memoryMap.region[IB].alignment = 64;
/* MPI Memory region 6 inbound queues */
pm8001_ha->memoryMap.region[OB].num_elements = 256;
pm8001_ha->memoryMap.region[OB].element_size = 64;
pm8001_ha->memoryMap.region[OB].total_len = 256 * 64;
pm8001_ha->memoryMap.region[OB].alignment = 64;
/* Memory region write DMA*/
pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
/* Memory region for devices*/
pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
sizeof(struct pm8001_device);
pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
sizeof(struct pm8001_device);
/* Memory region for ccb_info*/
pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
sizeof(struct pm8001_ccb_info);
pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
sizeof(struct pm8001_ccb_info);
for (i = 0; i < USI_MAX_MEMCNT; i++) {
if (pm8001_mem_alloc(pm8001_ha->pdev,
&pm8001_ha->memoryMap.region[i].virt_ptr,
&pm8001_ha->memoryMap.region[i].phys_addr,
&pm8001_ha->memoryMap.region[i].phys_addr_hi,
&pm8001_ha->memoryMap.region[i].phys_addr_lo,
pm8001_ha->memoryMap.region[i].total_len,
pm8001_ha->memoryMap.region[i].alignment) != 0) {
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("Mem%d alloc failed\n",
i));
goto err_out;
}
}
pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
for (i = 0; i < PM8001_MAX_DEVICES; i++) {
pm8001_ha->devices[i].dev_type = NO_DEVICE;
pm8001_ha->devices[i].id = i;
pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
pm8001_ha->devices[i].running_req = 0;
}
pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
for (i = 0; i < PM8001_MAX_CCB; i++) {
pm8001_ha->ccb_info[i].ccb_dma_handle =
pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
i * sizeof(struct pm8001_ccb_info);
++pm8001_ha->tags_num;
}
pm8001_ha->flags = PM8001F_INIT_TIME;
/* Initialize tags */
pm8001_tag_init(pm8001_ha);
return 0;
err_out:
return 1;
}
/**
* pm8001_ioremap - remap the pci high physical address to kernal virtual
* address so that we can access them.
* @pm8001_ha:our hba structure.
*/
static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
{
u32 bar;
u32 logicalBar = 0;
struct pci_dev *pdev;
pdev = pm8001_ha->pdev;
/* map pci mem (PMC pci base 0-3)*/
for (bar = 0; bar < 6; bar++) {
/*
** logical BARs for SPC:
** bar 0 and 1 - logical BAR0
** bar 2 and 3 - logical BAR1
** bar4 - logical BAR2
** bar5 - logical BAR3
** Skip the appropriate assignments:
*/
if ((bar == 1) || (bar == 3))
continue;
if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
pm8001_ha->io_mem[logicalBar].membase =
pci_resource_start(pdev, bar);
pm8001_ha->io_mem[logicalBar].membase &=
(u32)PCI_BASE_ADDRESS_MEM_MASK;
pm8001_ha->io_mem[logicalBar].memsize =
pci_resource_len(pdev, bar);
pm8001_ha->io_mem[logicalBar].memvirtaddr =
ioremap(pm8001_ha->io_mem[logicalBar].membase,
pm8001_ha->io_mem[logicalBar].memsize);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("PCI: bar %d, logicalBar %d "
"virt_addr=%lx,len=%d\n", bar, logicalBar,
(unsigned long)
pm8001_ha->io_mem[logicalBar].memvirtaddr,
pm8001_ha->io_mem[logicalBar].memsize));
} else {
pm8001_ha->io_mem[logicalBar].membase = 0;
pm8001_ha->io_mem[logicalBar].memsize = 0;
pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
}
logicalBar++;
}
return 0;
}
/**
* pm8001_pci_alloc - initialize our ha card structure
* @pdev: pci device.
* @ent: ent
* @shost: scsi host struct which has been initialized before.
*/
static struct pm8001_hba_info *__devinit
pm8001_pci_alloc(struct pci_dev *pdev, u32 chip_id, struct Scsi_Host *shost)
{
struct pm8001_hba_info *pm8001_ha;
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
pm8001_ha = sha->lldd_ha;
if (!pm8001_ha)
return NULL;
pm8001_ha->pdev = pdev;
pm8001_ha->dev = &pdev->dev;
pm8001_ha->chip_id = chip_id;
pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
pm8001_ha->irq = pdev->irq;
pm8001_ha->sas = sha;
pm8001_ha->shost = shost;
pm8001_ha->id = pm8001_id++;
INIT_LIST_HEAD(&pm8001_ha->wq_list);
pm8001_ha->logging_level = 0x01;
sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
#ifdef PM8001_USE_TASKLET
tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet,
(unsigned long)pm8001_ha);
#endif
pm8001_ioremap(pm8001_ha);
if (!pm8001_alloc(pm8001_ha))
return pm8001_ha;
pm8001_free(pm8001_ha);
return NULL;
}
/**
* pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
* @pdev: pci device.
*/
static int pci_go_44(struct pci_dev *pdev)
{
int rc;
if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
if (rc) {
rc = pci_set_consistent_dma_mask(pdev,
DMA_BIT_MASK(32));
if (rc) {
dev_printk(KERN_ERR, &pdev->dev,
"44-bit DMA enable failed\n");
return rc;
}
}
} else {
rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
if (rc) {
dev_printk(KERN_ERR, &pdev->dev,
"32-bit DMA enable failed\n");
return rc;
}
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
if (rc) {
dev_printk(KERN_ERR, &pdev->dev,
"32-bit consistent DMA enable failed\n");
return rc;
}
}
return rc;
}
/**
* pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
* @shost: scsi host which has been allocated outside.
* @chip_info: our ha struct.
*/
static int __devinit pm8001_prep_sas_ha_init(struct Scsi_Host * shost,
const struct pm8001_chip_info *chip_info)
{
int phy_nr, port_nr;
struct asd_sas_phy **arr_phy;
struct asd_sas_port **arr_port;
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
phy_nr = chip_info->n_phy;
port_nr = phy_nr;
memset(sha, 0x00, sizeof(*sha));
arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
if (!arr_phy)
goto exit;
arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
if (!arr_port)
goto exit_free2;
sha->sas_phy = arr_phy;
sha->sas_port = arr_port;
sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
if (!sha->lldd_ha)
goto exit_free1;
shost->transportt = pm8001_stt;
shost->max_id = PM8001_MAX_DEVICES;
shost->max_lun = 8;
shost->max_channel = 0;
shost->unique_id = pm8001_id;
shost->max_cmd_len = 16;
shost->can_queue = PM8001_CAN_QUEUE;
shost->cmd_per_lun = 32;
return 0;
exit_free1:
kfree(arr_port);
exit_free2:
kfree(arr_phy);
exit:
return -1;
}
/**
* pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
* @shost: scsi host which has been allocated outside
* @chip_info: our ha struct.
*/
static void __devinit pm8001_post_sas_ha_init(struct Scsi_Host *shost,
const struct pm8001_chip_info *chip_info)
{
int i = 0;
struct pm8001_hba_info *pm8001_ha;
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
pm8001_ha = sha->lldd_ha;
for (i = 0; i < chip_info->n_phy; i++) {
sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
}
sha->sas_ha_name = DRV_NAME;
sha->dev = pm8001_ha->dev;
sha->lldd_module = THIS_MODULE;
sha->sas_addr = &pm8001_ha->sas_addr[0];
sha->num_phys = chip_info->n_phy;
sha->lldd_max_execute_num = 1;
sha->lldd_queue_size = PM8001_CAN_QUEUE;
sha->core.shost = shost;
}
/**
* pm8001_init_sas_add - initialize sas address
* @chip_info: our ha struct.
*
* Currently we just set the fixed SAS address to our HBA,for manufacture,
* it should read from the EEPROM
*/
static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
{
u8 i;
#ifdef PM8001_READ_VPD
DECLARE_COMPLETION_ONSTACK(completion);
pm8001_ha->nvmd_completion = &completion;
PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, 0, 0);
wait_for_completion(&completion);
for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
memcpy(&pm8001_ha->phy[i].dev_sas_addr, pm8001_ha->sas_addr,
SAS_ADDR_SIZE);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("phy %d sas_addr = %x \n", i,
(u64)pm8001_ha->phy[i].dev_sas_addr));
}
#else
for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
pm8001_ha->phy[i].dev_sas_addr = 0x500e004010000004ULL;
pm8001_ha->phy[i].dev_sas_addr =
cpu_to_be64((u64)
(*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
}
memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
SAS_ADDR_SIZE);
#endif
}
#ifdef PM8001_USE_MSIX
/**
* pm8001_setup_msix - enable MSI-X interrupt
* @chip_info: our ha struct.
* @irq_handler: irq_handler
*/
static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha,
irq_handler_t irq_handler)
{
u32 i = 0, j = 0;
u32 number_of_intr = 1;
int flag = 0;
u32 max_entry;
int rc;
max_entry = sizeof(pm8001_ha->msix_entries) /
sizeof(pm8001_ha->msix_entries[0]);
flag |= IRQF_DISABLED;
for (i = 0; i < max_entry ; i++)
pm8001_ha->msix_entries[i].entry = i;
rc = pci_enable_msix(pm8001_ha->pdev, pm8001_ha->msix_entries,
number_of_intr);
pm8001_ha->number_of_intr = number_of_intr;
if (!rc) {
for (i = 0; i < number_of_intr; i++) {
if (request_irq(pm8001_ha->msix_entries[i].vector,
irq_handler, flag, DRV_NAME,
SHOST_TO_SAS_HA(pm8001_ha->shost))) {
for (j = 0; j < i; j++)
free_irq(
pm8001_ha->msix_entries[j].vector,
SHOST_TO_SAS_HA(pm8001_ha->shost));
pci_disable_msix(pm8001_ha->pdev);
break;
}
}
}
return rc;
}
#endif
/**
* pm8001_request_irq - register interrupt
* @chip_info: our ha struct.
*/
static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
{
struct pci_dev *pdev;
irq_handler_t irq_handler = pm8001_interrupt;
u32 rc;
pdev = pm8001_ha->pdev;
#ifdef PM8001_USE_MSIX
if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
return pm8001_setup_msix(pm8001_ha, irq_handler);
else
goto intx;
#endif
intx:
/* intialize the INT-X interrupt */
rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, DRV_NAME,
SHOST_TO_SAS_HA(pm8001_ha->shost));
return rc;
}
/**
* pm8001_pci_probe - probe supported device
* @pdev: pci device which kernel has been prepared for.
* @ent: pci device id
*
* This function is the main initialization function, when register a new
* pci driver it is invoked, all struct an hardware initilization should be done
* here, also, register interrupt
*/
static int __devinit pm8001_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
unsigned int rc;
u32 pci_reg;
struct pm8001_hba_info *pm8001_ha;
struct Scsi_Host *shost = NULL;
const struct pm8001_chip_info *chip;
dev_printk(KERN_INFO, &pdev->dev,
"pm8001: driver version %s\n", DRV_VERSION);
rc = pci_enable_device(pdev);
if (rc)
goto err_out_enable;
pci_set_master(pdev);
/*
* Enable pci slot busmaster by setting pci command register.
* This is required by FW for Cyclone card.
*/
pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
pci_reg |= 0x157;
pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
rc = pci_request_regions(pdev, DRV_NAME);
if (rc)
goto err_out_disable;
rc = pci_go_44(pdev);
if (rc)
goto err_out_regions;
shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
if (!shost) {
rc = -ENOMEM;
goto err_out_regions;
}
chip = &pm8001_chips[ent->driver_data];
SHOST_TO_SAS_HA(shost) =
kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
if (!SHOST_TO_SAS_HA(shost)) {
rc = -ENOMEM;
goto err_out_free_host;
}
rc = pm8001_prep_sas_ha_init(shost, chip);
if (rc) {
rc = -ENOMEM;
goto err_out_free;
}
pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
pm8001_ha = pm8001_pci_alloc(pdev, chip_8001, shost);
if (!pm8001_ha) {
rc = -ENOMEM;
goto err_out_free;
}
list_add_tail(&pm8001_ha->list, &hba_list);
PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd);
rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
if (rc)
goto err_out_ha_free;
rc = scsi_add_host(shost, &pdev->dev);
if (rc)
goto err_out_ha_free;
rc = pm8001_request_irq(pm8001_ha);
if (rc)
goto err_out_shost;
PM8001_CHIP_DISP->interrupt_enable(pm8001_ha);
pm8001_init_sas_add(pm8001_ha);
pm8001_post_sas_ha_init(shost, chip);
rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
if (rc)
goto err_out_shost;
scsi_scan_host(pm8001_ha->shost);
return 0;
err_out_shost:
scsi_remove_host(pm8001_ha->shost);
err_out_ha_free:
pm8001_free(pm8001_ha);
err_out_free:
kfree(SHOST_TO_SAS_HA(shost));
err_out_free_host:
kfree(shost);
err_out_regions:
pci_release_regions(pdev);
err_out_disable:
pci_disable_device(pdev);
err_out_enable:
return rc;
}
static void __devexit pm8001_pci_remove(struct pci_dev *pdev)
{
struct sas_ha_struct *sha = pci_get_drvdata(pdev);
struct pm8001_hba_info *pm8001_ha;
int i;
pm8001_ha = sha->lldd_ha;
pci_set_drvdata(pdev, NULL);
sas_unregister_ha(sha);
sas_remove_host(pm8001_ha->shost);
list_del(&pm8001_ha->list);
scsi_remove_host(pm8001_ha->shost);
PM8001_CHIP_DISP->interrupt_disable(pm8001_ha);
PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd);
#ifdef PM8001_USE_MSIX
for (i = 0; i < pm8001_ha->number_of_intr; i++)
synchronize_irq(pm8001_ha->msix_entries[i].vector);
for (i = 0; i < pm8001_ha->number_of_intr; i++)
free_irq(pm8001_ha->msix_entries[i].vector, sha);
pci_disable_msix(pdev);
#else
free_irq(pm8001_ha->irq, sha);
#endif
#ifdef PM8001_USE_TASKLET
tasklet_kill(&pm8001_ha->tasklet);
#endif
pm8001_free(pm8001_ha);
kfree(sha->sas_phy);
kfree(sha->sas_port);
kfree(sha);
pci_release_regions(pdev);
pci_disable_device(pdev);
}
/**
* pm8001_pci_suspend - power management suspend main entry point
* @pdev: PCI device struct
* @state: PM state change to (usually PCI_D3)
*
* Returns 0 success, anything else error.
*/
static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
{
struct sas_ha_struct *sha = pci_get_drvdata(pdev);
struct pm8001_hba_info *pm8001_ha;
int i , pos;
u32 device_state;
pm8001_ha = sha->lldd_ha;
flush_scheduled_work();
scsi_block_requests(pm8001_ha->shost);
pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
if (pos == 0) {
printk(KERN_ERR " PCI PM not supported\n");
return -ENODEV;
}
PM8001_CHIP_DISP->interrupt_disable(pm8001_ha);
PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd);
#ifdef PM8001_USE_MSIX
for (i = 0; i < pm8001_ha->number_of_intr; i++)
synchronize_irq(pm8001_ha->msix_entries[i].vector);
for (i = 0; i < pm8001_ha->number_of_intr; i++)
free_irq(pm8001_ha->msix_entries[i].vector, sha);
pci_disable_msix(pdev);
#else
free_irq(pm8001_ha->irq, sha);
#endif
#ifdef PM8001_USE_TASKLET
tasklet_kill(&pm8001_ha->tasklet);
#endif
device_state = pci_choose_state(pdev, state);
pm8001_printk("pdev=0x%p, slot=%s, entering "
"operating state [D%d]\n", pdev,
pm8001_ha->name, device_state);
pci_save_state(pdev);
pci_disable_device(pdev);
pci_set_power_state(pdev, device_state);
return 0;
}
/**
* pm8001_pci_resume - power management resume main entry point
* @pdev: PCI device struct
*
* Returns 0 success, anything else error.
*/
static int pm8001_pci_resume(struct pci_dev *pdev)
{
struct sas_ha_struct *sha = pci_get_drvdata(pdev);
struct pm8001_hba_info *pm8001_ha;
int rc;
u32 device_state;
pm8001_ha = sha->lldd_ha;
device_state = pdev->current_state;
pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
"operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
pci_set_power_state(pdev, PCI_D0);
pci_enable_wake(pdev, PCI_D0, 0);
pci_restore_state(pdev);
rc = pci_enable_device(pdev);
if (rc) {
pm8001_printk("slot=%s Enable device failed during resume\n",
pm8001_ha->name);
goto err_out_enable;
}
pci_set_master(pdev);
rc = pci_go_44(pdev);
if (rc)
goto err_out_disable;
PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd);
rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
if (rc)
goto err_out_disable;
PM8001_CHIP_DISP->interrupt_disable(pm8001_ha);
rc = pm8001_request_irq(pm8001_ha);
if (rc)
goto err_out_disable;
#ifdef PM8001_USE_TASKLET
tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet,
(unsigned long)pm8001_ha);
#endif
PM8001_CHIP_DISP->interrupt_enable(pm8001_ha);
scsi_unblock_requests(pm8001_ha->shost);
return 0;
err_out_disable:
scsi_remove_host(pm8001_ha->shost);
pci_disable_device(pdev);
err_out_enable:
return rc;
}
static struct pci_device_id __devinitdata pm8001_pci_table[] = {
{
PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001
},
{
PCI_DEVICE(0x117c, 0x0042),
.driver_data = chip_8001
},
{} /* terminate list */
};
static struct pci_driver pm8001_pci_driver = {
.name = DRV_NAME,
.id_table = pm8001_pci_table,
.probe = pm8001_pci_probe,
.remove = __devexit_p(pm8001_pci_remove),
.suspend = pm8001_pci_suspend,
.resume = pm8001_pci_resume,
};
/**
* pm8001_init - initialize scsi transport template
*/
static int __init pm8001_init(void)
{
int rc;
pm8001_id = 0;
pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
if (!pm8001_stt)
return -ENOMEM;
rc = pci_register_driver(&pm8001_pci_driver);
if (rc)
goto err_out;
return 0;
err_out:
sas_release_transport(pm8001_stt);
return rc;
}
static void __exit pm8001_exit(void)
{
pci_unregister_driver(&pm8001_pci_driver);
sas_release_transport(pm8001_stt);
}
module_init(pm8001_init);
module_exit(pm8001_exit);
MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
MODULE_DESCRIPTION("PMC-Sierra PM8001 SAS/SATA controller driver");
MODULE_VERSION(DRV_VERSION);
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
drivers/scsi/pm8001/pm8001_sas.c 0 → 100644
View file @ dbf9bfe6
/*
* PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
*
* Copyright (c) 2008-2009 USI Co., Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
*/
#include "pm8001_sas.h"
/**
* pm8001_find_tag - from sas task to find out tag that belongs to this task
* @task: the task sent to the LLDD
* @tag: the found tag associated with the task
*/
static int pm8001_find_tag(struct sas_task *task, u32 *tag)
{
if (task->lldd_task) {
struct pm8001_ccb_info *ccb;
ccb = task->lldd_task;
*tag = ccb->ccb_tag;
return 1;
}
return 0;
}
/**
* pm8001_tag_clear - clear the tags bitmap
* @pm8001_ha: our hba struct
* @tag: the found tag associated with the task
*/
static void pm8001_tag_clear(struct pm8001_hba_info *pm8001_ha, u32 tag)
{
void *bitmap = pm8001_ha->tags;
clear_bit(tag, bitmap);
}
static void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag)
{
pm8001_tag_clear(pm8001_ha, tag);
}
static void pm8001_tag_set(struct pm8001_hba_info *pm8001_ha, u32 tag)
{
void *bitmap = pm8001_ha->tags;
set_bit(tag, bitmap);
}
/**
* pm8001_tag_alloc - allocate a empty tag for task used.
* @pm8001_ha: our hba struct
* @tag_out: the found empty tag .
*/
inline int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out)
{
unsigned int index, tag;
void *bitmap = pm8001_ha->tags;
index = find_first_zero_bit(bitmap, pm8001_ha->tags_num);
tag = index;
if (tag >= pm8001_ha->tags_num)
return -SAS_QUEUE_FULL;
pm8001_tag_set(pm8001_ha, tag);
*tag_out = tag;
return 0;
}
void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha)
{
int i;
for (i = 0; i < pm8001_ha->tags_num; ++i)
pm8001_tag_clear(pm8001_ha, i);
}
/**
* pm8001_mem_alloc - allocate memory for pm8001.
* @pdev: pci device.
* @virt_addr: the allocated virtual address
* @pphys_addr_hi: the physical address high byte address.
* @pphys_addr_lo: the physical address low byte address.
* @mem_size: memory size.
*/
int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
dma_addr_t *pphys_addr, u32 *pphys_addr_hi,
u32 *pphys_addr_lo, u32 mem_size, u32 align)
{
caddr_t mem_virt_alloc;
dma_addr_t mem_dma_handle;
u64 phys_align;
u64 align_offset = 0;
if (align)
align_offset = (dma_addr_t)align - 1;
mem_virt_alloc =
pci_alloc_consistent(pdev, mem_size + align, &mem_dma_handle);
if (!mem_virt_alloc) {
pm8001_printk("memory allocation error\n");
return -1;
}
memset((void *)mem_virt_alloc, 0, mem_size+align);
*pphys_addr = mem_dma_handle;
phys_align = (*pphys_addr + align_offset) & ~align_offset;
*virt_addr = (void *)mem_virt_alloc + phys_align - *pphys_addr;
*pphys_addr_hi = upper_32_bits(phys_align);
*pphys_addr_lo = lower_32_bits(phys_align);
return 0;
}
/**
* pm8001_find_ha_by_dev - from domain device which come from sas layer to
* find out our hba struct.
* @dev: the domain device which from sas layer.
*/
static
struct pm8001_hba_info *pm8001_find_ha_by_dev(struct domain_device *dev)
{
struct sas_ha_struct *sha = dev->port->ha;
struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
return pm8001_ha;
}
/**
* pm8001_phy_control - this function should be registered to
* sas_domain_function_template to provide libsas used, note: this is just
* control the HBA phy rather than other expander phy if you want control
* other phy, you should use SMP command.
* @sas_phy: which phy in HBA phys.
* @func: the operation.
* @funcdata: always NULL.
*/
int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
void *funcdata)
{
int rc = 0, phy_id = sas_phy->id;
struct pm8001_hba_info *pm8001_ha = NULL;
struct sas_phy_linkrates *rates;
DECLARE_COMPLETION_ONSTACK(completion);
pm8001_ha = sas_phy->ha->lldd_ha;
pm8001_ha->phy[phy_id].enable_completion = &completion;
switch (func) {
case PHY_FUNC_SET_LINK_RATE:
rates = funcdata;
if (rates->minimum_linkrate) {
pm8001_ha->phy[phy_id].minimum_linkrate =
rates->minimum_linkrate;
}
if (rates->maximum_linkrate) {
pm8001_ha->phy[phy_id].maximum_linkrate =
rates->maximum_linkrate;
}
if (pm8001_ha->phy[phy_id].phy_state == 0) {
PM8001_CHIP_DISP->phy_start_req(pm8001_ha, phy_id);
wait_for_completion(&completion);
}
PM8001_CHIP_DISP->phy_ctl_req(pm8001_ha, phy_id,
PHY_LINK_RESET);
break;
case PHY_FUNC_HARD_RESET:
if (pm8001_ha->phy[phy_id].phy_state == 0) {
PM8001_CHIP_DISP->phy_start_req(pm8001_ha, phy_id);
wait_for_completion(&completion);
}
PM8001_CHIP_DISP->phy_ctl_req(pm8001_ha, phy_id,
PHY_HARD_RESET);
break;
case PHY_FUNC_LINK_RESET:
if (pm8001_ha->phy[phy_id].phy_state == 0) {
PM8001_CHIP_DISP->phy_start_req(pm8001_ha, phy_id);
wait_for_completion(&completion);
}
PM8001_CHIP_DISP->phy_ctl_req(pm8001_ha, phy_id,
PHY_LINK_RESET);
break;
case PHY_FUNC_RELEASE_SPINUP_HOLD:
PM8001_CHIP_DISP->phy_ctl_req(pm8001_ha, phy_id,
PHY_LINK_RESET);
break;
case PHY_FUNC_DISABLE:
PM8001_CHIP_DISP->phy_stop_req(pm8001_ha, phy_id);
break;
default:
rc = -EOPNOTSUPP;
}
msleep(300);
return rc;
}
int pm8001_slave_alloc(struct scsi_device *scsi_dev)
{
struct domain_device *dev = sdev_to_domain_dev(scsi_dev);
if (dev_is_sata(dev)) {
/* We don't need to rescan targets
* if REPORT_LUNS request is failed
*/
if (scsi_dev->lun > 0)
return -ENXIO;
scsi_dev->tagged_supported = 1;
}
return sas_slave_alloc(scsi_dev);
}
/**
* pm8001_scan_start - we should enable all HBA phys by sending the phy_start
* command to HBA.
* @shost: the scsi host data.
*/
void pm8001_scan_start(struct Scsi_Host *shost)
{
int i;
struct pm8001_hba_info *pm8001_ha;
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
pm8001_ha = sha->lldd_ha;
for (i = 0; i < pm8001_ha->chip->n_phy; ++i)
PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
}
int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time)
{
/* give the phy enabling interrupt event time to come in (1s
* is empirically about all it takes) */
if (time < HZ)
return 0;
/* Wait for discovery to finish */
scsi_flush_work(shost);
return 1;
}
/**
* pm8001_task_prep_smp - the dispatcher function, prepare data for smp task
* @pm8001_ha: our hba card information
* @ccb: the ccb which attached to smp task
*/
static int pm8001_task_prep_smp(struct pm8001_hba_info *pm8001_ha,
struct pm8001_ccb_info *ccb)
{
return PM8001_CHIP_DISP->smp_req(pm8001_ha, ccb);
}
u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag)
{
struct ata_queued_cmd *qc = task->uldd_task;
if (qc) {
if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
qc->tf.command == ATA_CMD_FPDMA_READ) {
*tag = qc->tag;
return 1;
}
}
return 0;
}
/**
* pm8001_task_prep_ata - the dispatcher function, prepare data for sata task
* @pm8001_ha: our hba card information
* @ccb: the ccb which attached to sata task
*/
static int pm8001_task_prep_ata(struct pm8001_hba_info *pm8001_ha,
struct pm8001_ccb_info *ccb)
{
return PM8001_CHIP_DISP->sata_req(pm8001_ha, ccb);
}
/**
* pm8001_task_prep_ssp_tm - the dispatcher function, prepare task management data
* @pm8001_ha: our hba card information
* @ccb: the ccb which attached to TM
* @tmf: the task management IU
*/
static int pm8001_task_prep_ssp_tm(struct pm8001_hba_info *pm8001_ha,
struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
{
return PM8001_CHIP_DISP->ssp_tm_req(pm8001_ha, ccb, tmf);
}
/**
* pm8001_task_prep_ssp - the dispatcher function,prepare ssp data for ssp task
* @pm8001_ha: our hba card information
* @ccb: the ccb which attached to ssp task
*/
static int pm8001_task_prep_ssp(struct pm8001_hba_info *pm8001_ha,
struct pm8001_ccb_info *ccb)
{
return PM8001_CHIP_DISP->ssp_io_req(pm8001_ha, ccb);
}
int pm8001_slave_configure(struct scsi_device *sdev)
{
struct domain_device *dev = sdev_to_domain_dev(sdev);
int ret = sas_slave_configure(sdev);
if (ret)
return ret;
if (dev_is_sata(dev)) {
#ifdef PM8001_DISABLE_NCQ
struct ata_port *ap = dev->sata_dev.ap;
struct ata_device *adev = ap->link.device;
adev->flags |= ATA_DFLAG_NCQ_OFF;
scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, 1);
#endif
}
return 0;
}
/**
* pm8001_task_exec -execute the task which come from upper level, send the
* command or data to DMA area and then increase CI,for queuecommand(ssp),
* it is from upper layer and for smp command,it is from libsas,
* for ata command it is from libata.
* @task: the task to be execute.
* @num: if can_queue great than 1, the task can be queued up. for SMP task,
* we always execute one one time.
* @gfp_flags: gfp_flags.
* @is tmf: if it is task management task.
* @tmf: the task management IU
*/
#define DEV_IS_GONE(pm8001_dev) \
((!pm8001_dev || (pm8001_dev->dev_type == NO_DEVICE)))
static int pm8001_task_exec(struct sas_task *task, const int num,
gfp_t gfp_flags, int is_tmf, struct pm8001_tmf_task *tmf)
{
struct domain_device *dev = task->dev;
struct pm8001_hba_info *pm8001_ha;
struct pm8001_device *pm8001_dev;
struct sas_task *t = task;
struct pm8001_ccb_info *ccb;
u32 tag = 0xdeadbeef, rc, n_elem = 0;
u32 n = num;
unsigned long flags = 0;
if (!dev->port) {
struct task_status_struct *tsm = &t->task_status;
tsm->resp = SAS_TASK_UNDELIVERED;
tsm->stat = SAS_PHY_DOWN;
if (dev->dev_type != SATA_DEV)
t->task_done(t);
return 0;
}
pm8001_ha = pm8001_find_ha_by_dev(task->dev);
PM8001_IO_DBG(pm8001_ha, pm8001_printk("pm8001_task_exec device \n "));
spin_lock_irqsave(&pm8001_ha->lock, flags);
do {
dev = t->dev;
pm8001_dev = dev->lldd_dev;
if (DEV_IS_GONE(pm8001_dev)) {
if (pm8001_dev) {
PM8001_IO_DBG(pm8001_ha,
pm8001_printk("device %d not ready.\n",
pm8001_dev->device_id));
} else {
PM8001_IO_DBG(pm8001_ha,
pm8001_printk("device %016llx not "
"ready.\n", SAS_ADDR(dev->sas_addr)));
}
rc = SAS_PHY_DOWN;
goto out_done;
}
rc = pm8001_tag_alloc(pm8001_ha, &tag);
if (rc)
goto err_out;
ccb = &pm8001_ha->ccb_info[tag];
if (!sas_protocol_ata(t->task_proto)) {
if (t->num_scatter) {
n_elem = dma_map_sg(pm8001_ha->dev,
t->scatter,
t->num_scatter,
t->data_dir);
if (!n_elem) {
rc = -ENOMEM;
goto err_out;
}
}
} else {
n_elem = t->num_scatter;
}
t->lldd_task = NULL;
ccb->n_elem = n_elem;
ccb->ccb_tag = tag;
ccb->task = t;
switch (t->task_proto) {
case SAS_PROTOCOL_SMP:
rc = pm8001_task_prep_smp(pm8001_ha, ccb);
break;
case SAS_PROTOCOL_SSP:
if (is_tmf)
rc = pm8001_task_prep_ssp_tm(pm8001_ha,
ccb, tmf);
else
rc = pm8001_task_prep_ssp(pm8001_ha, ccb);
break;
case SAS_PROTOCOL_SATA:
case SAS_PROTOCOL_STP:
case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
rc = pm8001_task_prep_ata(pm8001_ha, ccb);
break;
default:
dev_printk(KERN_ERR, pm8001_ha->dev,
"unknown sas_task proto: 0x%x\n",
t->task_proto);
rc = -EINVAL;
break;
}
if (rc) {
PM8001_IO_DBG(pm8001_ha,
pm8001_printk("rc is %x\n", rc));
goto err_out_tag;
}
t->lldd_task = ccb;
/* TODO: select normal or high priority */
spin_lock(&t->task_state_lock);
t->task_state_flags |= SAS_TASK_AT_INITIATOR;
spin_unlock(&t->task_state_lock);
pm8001_dev->running_req++;
if (n > 1)
t = list_entry(t->list.next, struct sas_task, list);
} while (--n);
rc = 0;
goto out_done;
err_out_tag:
pm8001_tag_free(pm8001_ha, tag);
err_out:
dev_printk(KERN_ERR, pm8001_ha->dev, "pm8001 exec failed[%d]!\n", rc);
if (!sas_protocol_ata(t->task_proto))
if (n_elem)
dma_unmap_sg(pm8001_ha->dev, t->scatter, n_elem,
t->data_dir);
out_done:
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
return rc;
}
/**
* pm8001_queue_command - register for upper layer used, all IO commands sent
* to HBA are from this interface.
* @task: the task to be execute.
* @num: if can_queue great than 1, the task can be queued up. for SMP task,
* we always execute one one time
* @gfp_flags: gfp_flags
*/
int pm8001_queue_command(struct sas_task *task, const int num,
gfp_t gfp_flags)
{
return pm8001_task_exec(task, num, gfp_flags, 0, NULL);
}
void pm8001_ccb_free(struct pm8001_hba_info *pm8001_ha, u32 ccb_idx)
{
pm8001_tag_clear(pm8001_ha, ccb_idx);
}
/**
* pm8001_ccb_task_free - free the sg for ssp and smp command, free the ccb.
* @pm8001_ha: our hba card information
* @ccb: the ccb which attached to ssp task
* @task: the task to be free.
* @ccb_idx: ccb index.
*/
void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx)
{
if (!ccb->task)
return;
if (!sas_protocol_ata(task->task_proto))
if (ccb->n_elem)
dma_unmap_sg(pm8001_ha->dev, task->scatter,
task->num_scatter, task->data_dir);
switch (task->task_proto) {
case SAS_PROTOCOL_SMP:
dma_unmap_sg(pm8001_ha->dev, &task->smp_task.smp_resp, 1,
PCI_DMA_FROMDEVICE);
dma_unmap_sg(pm8001_ha->dev, &task->smp_task.smp_req, 1,
PCI_DMA_TODEVICE);
break;
case SAS_PROTOCOL_SATA:
case SAS_PROTOCOL_STP:
case SAS_PROTOCOL_SSP:
default:
/* do nothing */
break;
}
task->lldd_task = NULL;
ccb->task = NULL;
ccb->ccb_tag = 0xFFFFFFFF;
pm8001_ccb_free(pm8001_ha, ccb_idx);
}
/**
* pm8001_alloc_dev - find the empty pm8001_device structure, allocate and
* return it for use.
* @pm8001_ha: our hba card information
*/
struct pm8001_device *pm8001_alloc_dev(struct pm8001_hba_info *pm8001_ha)
{
u32 dev;
for (dev = 0; dev < PM8001_MAX_DEVICES; dev++) {
if (pm8001_ha->devices[dev].dev_type == NO_DEVICE) {
pm8001_ha->devices[dev].id = dev;
return &pm8001_ha->devices[dev];
}
}
if (dev == PM8001_MAX_DEVICES) {
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("max support %d devices, ignore ..\n",
PM8001_MAX_DEVICES));
}
return NULL;
}
static void pm8001_free_dev(struct pm8001_device *pm8001_dev)
{
u32 id = pm8001_dev->id;
memset(pm8001_dev, 0, sizeof(*pm8001_dev));
pm8001_dev->id = id;
pm8001_dev->dev_type = NO_DEVICE;
pm8001_dev->device_id = PM8001_MAX_DEVICES;
pm8001_dev->sas_device = NULL;
}
/**
* pm8001_dev_found_notify - when libsas find a sas domain device, it should
* tell the LLDD that device is found, and then LLDD register this device to
* HBA FW by the command "OPC_INB_REG_DEV", after that the HBA will assign
* a device ID(according to device's sas address) and returned it to LLDD.from
* now on, we communicate with HBA FW with the device ID which HBA assigned
* rather than sas address. it is the neccessary step for our HBA but it is
* the optional for other HBA driver.
* @dev: the device structure which sas layer used.
*/
static int pm8001_dev_found_notify(struct domain_device *dev)
{
unsigned long flags = 0;
int res = 0;
struct pm8001_hba_info *pm8001_ha = NULL;
struct domain_device *parent_dev = dev->parent;
struct pm8001_device *pm8001_device;
DECLARE_COMPLETION_ONSTACK(completion);
u32 flag = 0;
pm8001_ha = pm8001_find_ha_by_dev(dev);
spin_lock_irqsave(&pm8001_ha->lock, flags);
pm8001_device = pm8001_alloc_dev(pm8001_ha);
pm8001_device->sas_device = dev;
if (!pm8001_device) {
res = -1;
goto found_out;
}
dev->lldd_dev = pm8001_device;
pm8001_device->dev_type = dev->dev_type;
pm8001_device->dcompletion = &completion;
if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
int phy_id;
struct ex_phy *phy;
for (phy_id = 0; phy_id < parent_dev->ex_dev.num_phys;
phy_id++) {
phy = &parent_dev->ex_dev.ex_phy[phy_id];
if (SAS_ADDR(phy->attached_sas_addr)
== SAS_ADDR(dev->sas_addr)) {
pm8001_device->attached_phy = phy_id;
break;
}
}
if (phy_id == parent_dev->ex_dev.num_phys) {
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("Error: no attached dev:%016llx"
" at ex:%016llx.\n", SAS_ADDR(dev->sas_addr),
SAS_ADDR(parent_dev->sas_addr)));
res = -1;
}
} else {
if (dev->dev_type == SATA_DEV) {
pm8001_device->attached_phy =
dev->rphy->identify.phy_identifier;
flag = 1; /* directly sata*/
}
} /*register this device to HBA*/
PM8001_DISC_DBG(pm8001_ha, pm8001_printk("Found device \n"));
PM8001_CHIP_DISP->reg_dev_req(pm8001_ha, pm8001_device, flag);
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
wait_for_completion(&completion);
if (dev->dev_type == SAS_END_DEV)
msleep(50);
pm8001_ha->flags = PM8001F_RUN_TIME ;
return 0;
found_out:
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
return res;
}
int pm8001_dev_found(struct domain_device *dev)
{
return pm8001_dev_found_notify(dev);
}
/**
* pm8001_alloc_task - allocate a task structure for TMF
*/
static struct sas_task *pm8001_alloc_task(void)
{
struct sas_task *task = kzalloc(sizeof(*task), GFP_KERNEL);
if (task) {
INIT_LIST_HEAD(&task->list);
spin_lock_init(&task->task_state_lock);
task->task_state_flags = SAS_TASK_STATE_PENDING;
init_timer(&task->timer);
init_completion(&task->completion);
}
return task;
}
static void pm8001_free_task(struct sas_task *task)
{
if (task) {
BUG_ON(!list_empty(&task->list));
kfree(task);
}
}
static void pm8001_task_done(struct sas_task *task)
{
if (!del_timer(&task->timer))
return;
complete(&task->completion);
}
static void pm8001_tmf_timedout(unsigned long data)
{
struct sas_task *task = (struct sas_task *)data;
task->task_state_flags |= SAS_TASK_STATE_ABORTED;
complete(&task->completion);
}
#define PM8001_TASK_TIMEOUT 20
/**
* pm8001_exec_internal_tmf_task - when errors or exception happened, we may
* want to do something, for example abort issued task which result in this
* execption, this is by calling this function, note it is also with the task
* execute interface.
* @dev: the wanted device.
* @tmf: which task management wanted to be take.
* @para_len: para_len.
* @parameter: ssp task parameter.
*/
static int pm8001_exec_internal_tmf_task(struct domain_device *dev,
void *parameter, u32 para_len, struct pm8001_tmf_task *tmf)
{
int res, retry;
struct sas_task *task = NULL;
struct pm8001_hba_info *pm8001_ha = pm8001_find_ha_by_dev(dev);
for (retry = 0; retry < 3; retry++) {
task = pm8001_alloc_task();
if (!task)
return -ENOMEM;
task->dev = dev;
task->task_proto = dev->tproto;
memcpy(&task->ssp_task, parameter, para_len);
task->task_done = pm8001_task_done;
task->timer.data = (unsigned long)task;
task->timer.function = pm8001_tmf_timedout;
task->timer.expires = jiffies + PM8001_TASK_TIMEOUT*HZ;
add_timer(&task->timer);
res = pm8001_task_exec(task, 1, GFP_KERNEL, 1, tmf);
if (res) {
del_timer(&task->timer);
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("Executing internal task "
"failed\n"));
goto ex_err;
}
wait_for_completion(&task->completion);
res = -TMF_RESP_FUNC_FAILED;
/* Even TMF timed out, return direct. */
if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("TMF task[%x]timeout.\n",
tmf->tmf));
goto ex_err;
}
}
if (task->task_status.resp == SAS_TASK_COMPLETE &&
task->task_status.stat == SAM_GOOD) {
res = TMF_RESP_FUNC_COMPLETE;
break;
}
if (task->task_status.resp == SAS_TASK_COMPLETE &&
task->task_status.stat == SAS_DATA_UNDERRUN) {
/* no error, but return the number of bytes of
* underrun */
res = task->task_status.residual;
break;
}
if (task->task_status.resp == SAS_TASK_COMPLETE &&
task->task_status.stat == SAS_DATA_OVERRUN) {
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("Blocked task error.\n"));
res = -EMSGSIZE;
break;
} else {
PM8001_IO_DBG(pm8001_ha,
pm8001_printk(" Task to dev %016llx response: 0x%x"
"status 0x%x\n",
SAS_ADDR(dev->sas_addr),
task->task_status.resp,
task->task_status.stat));
pm8001_free_task(task);
task = NULL;
}
}
ex_err:
BUG_ON(retry == 3 && task != NULL);
if (task != NULL)
pm8001_free_task(task);
return res;
}
static int
pm8001_exec_internal_task_abort(struct pm8001_hba_info *pm8001_ha,
struct pm8001_device *pm8001_dev, struct domain_device *dev, u32 flag,
u32 task_tag)
{
int res, retry;
u32 rc, ccb_tag;
struct pm8001_ccb_info *ccb;
struct sas_task *task = NULL;
for (retry = 0; retry < 3; retry++) {
task = pm8001_alloc_task();
if (!task)
return -ENOMEM;
task->dev = dev;
task->task_proto = dev->tproto;
task->task_done = pm8001_task_done;
task->timer.data = (unsigned long)task;
task->timer.function = pm8001_tmf_timedout;
task->timer.expires = jiffies + PM8001_TASK_TIMEOUT*HZ;
add_timer(&task->timer);
rc = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
if (rc)
return rc;
ccb = &pm8001_ha->ccb_info[ccb_tag];
ccb->device = pm8001_dev;
ccb->ccb_tag = ccb_tag;
ccb->task = task;
res = PM8001_CHIP_DISP->task_abort(pm8001_ha,
pm8001_dev, flag, task_tag, ccb_tag);
if (res) {
del_timer(&task->timer);
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("Executing internal task "
"failed\n"));
goto ex_err;
}
wait_for_completion(&task->completion);
res = TMF_RESP_FUNC_FAILED;
/* Even TMF timed out, return direct. */
if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("TMF task timeout.\n"));
goto ex_err;
}
}
if (task->task_status.resp == SAS_TASK_COMPLETE &&
task->task_status.stat == SAM_GOOD) {
res = TMF_RESP_FUNC_COMPLETE;
break;
} else {
PM8001_IO_DBG(pm8001_ha,
pm8001_printk(" Task to dev %016llx response: "
"0x%x status 0x%x\n",
SAS_ADDR(dev->sas_addr),
task->task_status.resp,
task->task_status.stat));
pm8001_free_task(task);
task = NULL;
}
}
ex_err:
BUG_ON(retry == 3 && task != NULL);
if (task != NULL)
pm8001_free_task(task);
return res;
}
/**
* pm8001_dev_gone_notify - see the comments for "pm8001_dev_found_notify"
* @dev: the device structure which sas layer used.
*/
static void pm8001_dev_gone_notify(struct domain_device *dev)
{
unsigned long flags = 0;
u32 tag;
struct pm8001_hba_info *pm8001_ha;
struct pm8001_device *pm8001_dev = dev->lldd_dev;
u32 device_id = pm8001_dev->device_id;
pm8001_ha = pm8001_find_ha_by_dev(dev);
spin_lock_irqsave(&pm8001_ha->lock, flags);
pm8001_tag_alloc(pm8001_ha, &tag);
if (pm8001_dev) {
PM8001_DISC_DBG(pm8001_ha,
pm8001_printk("found dev[%d:%x] is gone.\n",
pm8001_dev->device_id, pm8001_dev->dev_type));
if (pm8001_dev->running_req) {
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev ,
dev, 1, 0);
spin_lock_irqsave(&pm8001_ha->lock, flags);
}
PM8001_CHIP_DISP->dereg_dev_req(pm8001_ha, device_id);
pm8001_free_dev(pm8001_dev);
} else {
PM8001_DISC_DBG(pm8001_ha,
pm8001_printk("Found dev has gone.\n"));
}
dev->lldd_dev = NULL;
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
}
void pm8001_dev_gone(struct domain_device *dev)
{
pm8001_dev_gone_notify(dev);
}
static int pm8001_issue_ssp_tmf(struct domain_device *dev,
u8 *lun, struct pm8001_tmf_task *tmf)
{
struct sas_ssp_task ssp_task;
if (!(dev->tproto & SAS_PROTOCOL_SSP))
return TMF_RESP_FUNC_ESUPP;
strncpy((u8 *)&ssp_task.LUN, lun, 8);
return pm8001_exec_internal_tmf_task(dev, &ssp_task, sizeof(ssp_task),
tmf);
}
/**
* Standard mandates link reset for ATA (type 0) and hard reset for
* SSP (type 1) , only for RECOVERY
*/
int pm8001_I_T_nexus_reset(struct domain_device *dev)
{
int rc = TMF_RESP_FUNC_FAILED;
struct pm8001_device *pm8001_dev;
struct pm8001_hba_info *pm8001_ha;
struct sas_phy *phy;
if (!dev || !dev->lldd_dev)
return -1;
pm8001_dev = dev->lldd_dev;
pm8001_ha = pm8001_find_ha_by_dev(dev);
phy = sas_find_local_phy(dev);
if (dev_is_sata(dev)) {
DECLARE_COMPLETION_ONSTACK(completion_setstate);
rc = sas_phy_reset(phy, 1);
msleep(2000);
rc = pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev ,
dev, 1, 0);
pm8001_dev->setds_completion = &completion_setstate;
rc = PM8001_CHIP_DISP->set_dev_state_req(pm8001_ha,
pm8001_dev, 0x01);
wait_for_completion(&completion_setstate);
} else{
rc = sas_phy_reset(phy, 1);
msleep(2000);
}
PM8001_EH_DBG(pm8001_ha, pm8001_printk(" for device[%x]:rc=%d\n",
pm8001_dev->device_id, rc));
return rc;
}
/* mandatory SAM-3, the task reset the specified LUN*/
int pm8001_lu_reset(struct domain_device *dev, u8 *lun)
{
int rc = TMF_RESP_FUNC_FAILED;
struct pm8001_tmf_task tmf_task;
struct pm8001_device *pm8001_dev = dev->lldd_dev;
struct pm8001_hba_info *pm8001_ha = pm8001_find_ha_by_dev(dev);
if (dev_is_sata(dev)) {
struct sas_phy *phy = sas_find_local_phy(dev);
rc = pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev ,
dev, 1, 0);
rc = sas_phy_reset(phy, 1);
rc = PM8001_CHIP_DISP->set_dev_state_req(pm8001_ha,
pm8001_dev, 0x01);
msleep(2000);
} else {
tmf_task.tmf = TMF_LU_RESET;
rc = pm8001_issue_ssp_tmf(dev, lun, &tmf_task);
}
/* If failed, fall-through I_T_Nexus reset */
PM8001_EH_DBG(pm8001_ha, pm8001_printk("for device[%x]:rc=%d\n",
pm8001_dev->device_id, rc));
return rc;
}
/* optional SAM-3 */
int pm8001_query_task(struct sas_task *task)
{
u32 tag = 0xdeadbeef;
int i = 0;
struct scsi_lun lun;
struct pm8001_tmf_task tmf_task;
int rc = TMF_RESP_FUNC_FAILED;
if (unlikely(!task || !task->lldd_task || !task->dev))
return rc;
if (task->task_proto & SAS_PROTOCOL_SSP) {
struct scsi_cmnd *cmnd = task->uldd_task;
struct domain_device *dev = task->dev;
struct pm8001_hba_info *pm8001_ha =
pm8001_find_ha_by_dev(dev);
int_to_scsilun(cmnd->device->lun, &lun);
rc = pm8001_find_tag(task, &tag);
if (rc == 0) {
rc = TMF_RESP_FUNC_FAILED;
return rc;
}
PM8001_EH_DBG(pm8001_ha, pm8001_printk("Query:["));
for (i = 0; i < 16; i++)
printk(KERN_INFO "%02x ", cmnd->cmnd[i]);
printk(KERN_INFO "]\n");
tmf_task.tmf = TMF_QUERY_TASK;
tmf_task.tag_of_task_to_be_managed = tag;
rc = pm8001_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
switch (rc) {
/* The task is still in Lun, release it then */
case TMF_RESP_FUNC_SUCC:
PM8001_EH_DBG(pm8001_ha,
pm8001_printk("The task is still in Lun \n"));
/* The task is not in Lun or failed, reset the phy */
case TMF_RESP_FUNC_FAILED:
case TMF_RESP_FUNC_COMPLETE:
PM8001_EH_DBG(pm8001_ha,
pm8001_printk("The task is not in Lun or failed,"
" reset the phy \n"));
break;
}
}
pm8001_printk(":rc= %d\n", rc);
return rc;
}
/* mandatory SAM-3, still need free task/ccb info, abord the specified task */
int pm8001_abort_task(struct sas_task *task)
{
unsigned long flags;
u32 tag = 0xdeadbeef;
u32 device_id;
struct domain_device *dev ;
struct pm8001_hba_info *pm8001_ha = NULL;
struct pm8001_ccb_info *ccb;
struct scsi_lun lun;
struct pm8001_device *pm8001_dev;
struct pm8001_tmf_task tmf_task;
int rc = TMF_RESP_FUNC_FAILED;
if (unlikely(!task || !task->lldd_task || !task->dev))
return rc;
spin_lock_irqsave(&task->task_state_lock, flags);
if (task->task_state_flags & SAS_TASK_STATE_DONE) {
spin_unlock_irqrestore(&task->task_state_lock, flags);
rc = TMF_RESP_FUNC_COMPLETE;
goto out;
}
spin_unlock_irqrestore(&task->task_state_lock, flags);
if (task->task_proto & SAS_PROTOCOL_SSP) {
struct scsi_cmnd *cmnd = task->uldd_task;
dev = task->dev;
ccb = task->lldd_task;
pm8001_dev = dev->lldd_dev;
pm8001_ha = pm8001_find_ha_by_dev(dev);
int_to_scsilun(cmnd->device->lun, &lun);
rc = pm8001_find_tag(task, &tag);
if (rc == 0) {
printk(KERN_INFO "No such tag in %s\n", __func__);
rc = TMF_RESP_FUNC_FAILED;
return rc;
}
device_id = pm8001_dev->device_id;
PM8001_EH_DBG(pm8001_ha,
pm8001_printk("abort io to device_id = %d\n", device_id));
tmf_task.tmf = TMF_ABORT_TASK;
tmf_task.tag_of_task_to_be_managed = tag;
rc = pm8001_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
rc = pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev,
pm8001_dev->sas_device, 0, tag);
} else if (task->task_proto & SAS_PROTOCOL_SATA ||
task->task_proto & SAS_PROTOCOL_STP) {
dev = task->dev;
pm8001_dev = dev->lldd_dev;
pm8001_ha = pm8001_find_ha_by_dev(dev);
rc = pm8001_find_tag(task, &tag);
if (rc == 0) {
printk(KERN_INFO "No such tag in %s\n", __func__);
rc = TMF_RESP_FUNC_FAILED;
return rc;
}
rc = pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev,
pm8001_dev->sas_device, 0, tag);
} else if (task->task_proto & SAS_PROTOCOL_SMP) {
/* SMP */
dev = task->dev;
pm8001_dev = dev->lldd_dev;
pm8001_ha = pm8001_find_ha_by_dev(dev);
rc = pm8001_find_tag(task, &tag);
if (rc == 0) {
printk(KERN_INFO "No such tag in %s\n", __func__);
rc = TMF_RESP_FUNC_FAILED;
return rc;
}
rc = pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev,
pm8001_dev->sas_device, 0, tag);
}
out:
if (rc != TMF_RESP_FUNC_COMPLETE)
pm8001_printk("rc= %d\n", rc);
return rc;
}
int pm8001_abort_task_set(struct domain_device *dev, u8 *lun)
{
int rc = TMF_RESP_FUNC_FAILED;
struct pm8001_tmf_task tmf_task;
tmf_task.tmf = TMF_ABORT_TASK_SET;
rc = pm8001_issue_ssp_tmf(dev, lun, &tmf_task);
return rc;
}
int pm8001_clear_aca(struct domain_device *dev, u8 *lun)
{
int rc = TMF_RESP_FUNC_FAILED;
struct pm8001_tmf_task tmf_task;
tmf_task.tmf = TMF_CLEAR_ACA;
rc = pm8001_issue_ssp_tmf(dev, lun, &tmf_task);
return rc;
}
int pm8001_clear_task_set(struct domain_device *dev, u8 *lun)
{
int rc = TMF_RESP_FUNC_FAILED;
struct pm8001_tmf_task tmf_task;
struct pm8001_device *pm8001_dev = dev->lldd_dev;
struct pm8001_hba_info *pm8001_ha = pm8001_find_ha_by_dev(dev);
PM8001_EH_DBG(pm8001_ha,
pm8001_printk("I_T_L_Q clear task set[%x]\n",
pm8001_dev->device_id));
tmf_task.tmf = TMF_CLEAR_TASK_SET;
rc = pm8001_issue_ssp_tmf(dev, lun, &tmf_task);
return rc;
}
drivers/scsi/pm8001/pm8001_sas.h 0 → 100644
View file @ dbf9bfe6
/*
* PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
*
* Copyright (c) 2008-2009 USI Co., Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
*/
#ifndef _PM8001_SAS_H_
#define _PM8001_SAS_H_
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/ctype.h>
#include <linux/dma-mapping.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/smp_lock.h>
#include <scsi/libsas.h>
#include <scsi/scsi_tcq.h>
#include <scsi/sas_ata.h>
#include <asm/atomic.h>
#include "pm8001_defs.h"
#define DRV_NAME "pm8001"
#define DRV_VERSION "0.1.36"
#define PM8001_FAIL_LOGGING 0x01 /* libsas EH function logging */
#define PM8001_INIT_LOGGING 0x02 /* driver init logging */
#define PM8001_DISC_LOGGING 0x04 /* discovery layer logging */
#define PM8001_IO_LOGGING 0x08 /* I/O path logging */
#define PM8001_EH_LOGGING 0x10 /* Error message logging */
#define PM8001_IOCTL_LOGGING 0x20 /* IOCTL message logging */
#define PM8001_MSG_LOGGING 0x40 /* misc message logging */
#define pm8001_printk(format, arg...) printk(KERN_INFO "%s %d:" format,\
__func__, __LINE__, ## arg)
#define PM8001_CHECK_LOGGING(HBA, LEVEL, CMD) \
do { \
if (unlikely(HBA->logging_level & LEVEL)) \
do { \
CMD; \
} while (0); \
} while (0);
#define PM8001_EH_DBG(HBA, CMD) \
PM8001_CHECK_LOGGING(HBA, PM8001_EH_LOGGING, CMD)
#define PM8001_INIT_DBG(HBA, CMD) \
PM8001_CHECK_LOGGING(HBA, PM8001_INIT_LOGGING, CMD)
#define PM8001_DISC_DBG(HBA, CMD) \
PM8001_CHECK_LOGGING(HBA, PM8001_DISC_LOGGING, CMD)
#define PM8001_IO_DBG(HBA, CMD) \
PM8001_CHECK_LOGGING(HBA, PM8001_IO_LOGGING, CMD)
#define PM8001_FAIL_DBG(HBA, CMD) \
PM8001_CHECK_LOGGING(HBA, PM8001_FAIL_LOGGING, CMD)
#define PM8001_IOCTL_DBG(HBA, CMD) \
PM8001_CHECK_LOGGING(HBA, PM8001_IOCTL_LOGGING, CMD)
#define PM8001_MSG_DBG(HBA, CMD) \
PM8001_CHECK_LOGGING(HBA, PM8001_MSG_LOGGING, CMD)
#define PM8001_USE_TASKLET
#define PM8001_USE_MSIX
#define DEV_IS_EXPANDER(type) ((type == EDGE_DEV) || (type == FANOUT_DEV))
#define PM8001_NAME_LENGTH 32/* generic length of strings */
extern struct list_head hba_list;
extern const struct pm8001_dispatch pm8001_8001_dispatch;
struct pm8001_hba_info;
struct pm8001_ccb_info;
struct pm8001_device;
struct pm8001_tmf_task;
struct pm8001_dispatch {
char *name;
int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha, u32 signature);
void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
void (*isr)(struct pm8001_hba_info *pm8001_ha);
u32 (*is_our_interupt)(struct pm8001_hba_info *pm8001_ha);
int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha);
void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha);
void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha);
void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
struct pm8001_ccb_info *ccb);
int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
struct pm8001_ccb_info *ccb);
int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
struct pm8001_ccb_info *ccb);
int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
struct pm8001_device *pm8001_dev, u32 flag);
int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
u32 phy_id, u32 phy_op);
int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
u32 cmd_tag);
int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf);
int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
void *payload);
int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
struct pm8001_device *pm8001_dev, u32 state);
int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
u32 state);
int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
u32 state);
};
struct pm8001_chip_info {
u32 n_phy;
const struct pm8001_dispatch *dispatch;
};
#define PM8001_CHIP_DISP (pm8001_ha->chip->dispatch)
struct pm8001_port {
struct asd_sas_port sas_port;
};
struct pm8001_phy {
struct pm8001_hba_info *pm8001_ha;
struct pm8001_port *port;
struct asd_sas_phy sas_phy;
struct sas_identify identify;
struct scsi_device *sdev;
u64 dev_sas_addr;
u32 phy_type;
struct completion *enable_completion;
u32 frame_rcvd_size;
u8 frame_rcvd[32];
u8 phy_attached;
u8 phy_state;
enum sas_linkrate minimum_linkrate;
enum sas_linkrate maximum_linkrate;
};
struct pm8001_device {
enum sas_dev_type dev_type;
struct domain_device *sas_device;
u32 attached_phy;
u32 id;
struct completion *dcompletion;
struct completion *setds_completion;
u32 device_id;
u32 running_req;
};
struct pm8001_prd_imt {
__le32 len;
__le32 e;
};
struct pm8001_prd {
__le64 addr; /* 64-bit buffer address */
struct pm8001_prd_imt im_len; /* 64-bit length */
} __attribute__ ((packed));
/*
* CCB(Command Control Block)
*/
struct pm8001_ccb_info {
struct list_head entry;
struct sas_task *task;
u32 n_elem;
u32 ccb_tag;
dma_addr_t ccb_dma_handle;
struct pm8001_device *device;
struct pm8001_prd buf_prd[PM8001_MAX_DMA_SG];
struct fw_control_ex *fw_control_context;
};
struct mpi_mem {
void *virt_ptr;
dma_addr_t phys_addr;
u32 phys_addr_hi;
u32 phys_addr_lo;
u32 total_len;
u32 num_elements;
u32 element_size;
u32 alignment;
};
struct mpi_mem_req {
/* The number of element in the mpiMemory array */
u32 count;
/* The array of structures that define memroy regions*/
struct mpi_mem region[USI_MAX_MEMCNT];
};
struct main_cfg_table {
u32 signature;
u32 interface_rev;
u32 firmware_rev;
u32 max_out_io;
u32 max_sgl;
u32 ctrl_cap_flag;
u32 gst_offset;
u32 inbound_queue_offset;
u32 outbound_queue_offset;
u32 inbound_q_nppd_hppd;
u32 outbound_hw_event_pid0_3;
u32 outbound_hw_event_pid4_7;
u32 outbound_ncq_event_pid0_3;
u32 outbound_ncq_event_pid4_7;
u32 outbound_tgt_ITNexus_event_pid0_3;
u32 outbound_tgt_ITNexus_event_pid4_7;
u32 outbound_tgt_ssp_event_pid0_3;
u32 outbound_tgt_ssp_event_pid4_7;
u32 outbound_tgt_smp_event_pid0_3;
u32 outbound_tgt_smp_event_pid4_7;
u32 upper_event_log_addr;
u32 lower_event_log_addr;
u32 event_log_size;
u32 event_log_option;
u32 upper_iop_event_log_addr;
u32 lower_iop_event_log_addr;
u32 iop_event_log_size;
u32 iop_event_log_option;
u32 fatal_err_interrupt;
u32 fatal_err_dump_offset0;
u32 fatal_err_dump_length0;
u32 fatal_err_dump_offset1;
u32 fatal_err_dump_length1;
u32 hda_mode_flag;
u32 anolog_setup_table_offset;
};
struct general_status_table {
u32 gst_len_mpistate;
u32 iq_freeze_state0;
u32 iq_freeze_state1;
u32 msgu_tcnt;
u32 iop_tcnt;
u32 reserved;
u32 phy_state[8];
u32 reserved1;
u32 reserved2;
u32 reserved3;
u32 recover_err_info[8];
};
struct inbound_queue_table {
u32 element_pri_size_cnt;
u32 upper_base_addr;
u32 lower_base_addr;
u32 ci_upper_base_addr;
u32 ci_lower_base_addr;
u32 pi_pci_bar;
u32 pi_offset;
u32 total_length;
void *base_virt;
void *ci_virt;
u32 reserved;
__le32 consumer_index;
u32 producer_idx;
};
struct outbound_queue_table {
u32 element_size_cnt;
u32 upper_base_addr;
u32 lower_base_addr;
void *base_virt;
u32 pi_upper_base_addr;
u32 pi_lower_base_addr;
u32 ci_pci_bar;
u32 ci_offset;
u32 total_length;
void *pi_virt;
u32 interrup_vec_cnt_delay;
u32 dinterrup_to_pci_offset;
__le32 producer_index;
u32 consumer_idx;
};
struct pm8001_hba_memspace {
void __iomem *memvirtaddr;
u64 membase;
u32 memsize;
};
struct pm8001_hba_info {
char name[PM8001_NAME_LENGTH];
struct list_head list;
unsigned long flags;
spinlock_t lock;/* host-wide lock */
struct pci_dev *pdev;/* our device */
struct device *dev;
struct pm8001_hba_memspace io_mem[6];
struct mpi_mem_req memoryMap;
void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/
void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/
void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/
void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
struct main_cfg_table main_cfg_tbl;
struct general_status_table gs_tbl;
struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_INB_NUM];
struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_OUTB_NUM];
u8 sas_addr[SAS_ADDR_SIZE];
struct sas_ha_struct *sas;/* SCSI/SAS glue */
struct Scsi_Host *shost;
u32 chip_id;
const struct pm8001_chip_info *chip;
struct completion *nvmd_completion;
int tags_num;
unsigned long *tags;
struct pm8001_phy phy[PM8001_MAX_PHYS];
struct pm8001_port port[PM8001_MAX_PHYS];
u32 id;
u32 irq;
struct pm8001_device *devices;
struct pm8001_ccb_info *ccb_info;
#ifdef PM8001_USE_MSIX
struct msix_entry msix_entries[16];/*for msi-x interrupt*/
int number_of_intr;/*will be used in remove()*/
#endif
#ifdef PM8001_USE_TASKLET
struct tasklet_struct tasklet;
#endif
struct list_head wq_list;
u32 logging_level;
u32 fw_status;
const struct firmware *fw_image;
};
struct pm8001_wq {
struct delayed_work work_q;
struct pm8001_hba_info *pm8001_ha;
void *data;
int handler;
struct list_head entry;
};
struct pm8001_fw_image_header {
u8 vender_id[8];
u8 product_id;
u8 hardware_rev;
u8 dest_partition;
u8 reserved;
u8 fw_rev[4];
__be32 image_length;
__be32 image_crc;
__be32 startup_entry;
} __attribute__((packed, aligned(4)));
/* define task management IU */
struct pm8001_tmf_task {
u8 tmf;
u32 tag_of_task_to_be_managed;
};
/**
* FW Flash Update status values
*/
#define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00
#define FLASH_UPDATE_IN_PROGRESS 0x01
#define FLASH_UPDATE_HDR_ERR 0x02
#define FLASH_UPDATE_OFFSET_ERR 0x03
#define FLASH_UPDATE_CRC_ERR 0x04
#define FLASH_UPDATE_LENGTH_ERR 0x05
#define FLASH_UPDATE_HW_ERR 0x06
#define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
#define FLASH_UPDATE_DISABLED 0x11
/**
* brief param structure for firmware flash update.
*/
struct fw_flash_updata_info {
u32 cur_image_offset;
u32 cur_image_len;
u32 total_image_len;
struct pm8001_prd sgl;
};
struct fw_control_info {
u32 retcode;/*ret code (status)*/
u32 phase;/*ret code phase*/
u32 phaseCmplt;/*percent complete for the current
update phase */
u32 version;/*Hex encoded firmware version number*/
u32 offset;/*Used for downloading firmware */
u32 len; /*len of buffer*/
u32 size;/* Used in OS VPD and Trace get size
operations.*/
u32 reserved;/* padding required for 64 bit
alignment */
u8 buffer[1];/* Start of buffer */
};
struct fw_control_ex {
struct fw_control_info *fw_control;
void *buffer;/* keep buffer pointer to be
freed when the responce comes*/
void *virtAddr;/* keep virtual address of the data */
void *usrAddr;/* keep virtual address of the
user data */
dma_addr_t phys_addr;
u32 len; /* len of buffer */
void *payload; /* pointer to IOCTL Payload */
u8 inProgress;/*if 1 - the IOCTL request is in
progress */
void *param1;
void *param2;
void *param3;
};
/******************** function prototype *********************/
int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha);
u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
void pm8001_ccb_free(struct pm8001_hba_info *pm8001_ha, u32 ccb_idx);
void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
void *funcdata);
int pm8001_slave_alloc(struct scsi_device *scsi_dev);
int pm8001_slave_configure(struct scsi_device *sdev);
void pm8001_scan_start(struct Scsi_Host *shost);
int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
int pm8001_queue_command(struct sas_task *task, const int num,
gfp_t gfp_flags);
int pm8001_abort_task(struct sas_task *task);
int pm8001_abort_task_set(struct domain_device *dev, u8 *lun);
int pm8001_clear_aca(struct domain_device *dev, u8 *lun);
int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
int pm8001_dev_found(struct domain_device *dev);
void pm8001_dev_gone(struct domain_device *dev);
int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
int pm8001_I_T_nexus_reset(struct domain_device *dev);
int pm8001_query_task(struct sas_task *task);
int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
u32 mem_size, u32 align);
/* ctl shared API */
extern struct device_attribute *pm8001_host_attrs[];
#endif
include/linux/pci_ids.h
View file @ dbf9bfe6
...@@ -1586,6 +1586,8 @@ ...@@ -1586,6 +1586,8 @@
#define PCI_VENDOR_ID_COMPEX 0x11f6 #define PCI_VENDOR_ID_COMPEX 0x11f6
#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 #define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112
#define PCI_VENDOR_ID_PMC_Sierra 0x11f8
#define PCI_VENDOR_ID_RP 0x11fe #define PCI_VENDOR_ID_RP 0x11fe
#define PCI_DEVICE_ID_RP32INTF 0x0001 #define PCI_DEVICE_ID_RP32INTF 0x0001
#define PCI_DEVICE_ID_RP8INTF 0x0002 #define PCI_DEVICE_ID_RP8INTF 0x0002
......
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