Skip to content

L
linux
Commit dc26aec2 authored by Michael Hennerich's avatar Michael Hennerich Committed by Bryan Wu
Browse files
Options

Blackfin arch: BF538/9 Linux kernel Support 

Add supporing for Blackfin BF538 and BF539 processors.
Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent f940260a
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 10587 additions and 16 deletions
arch/blackfin/Kconfig
View file @ dc26aec2
...@@ -137,6 +137,16 @@ config BF537 ...@@ -137,6 +137,16 @@ config BF537
help help
BF537 Processor Support. BF537 Processor Support.
config BF538
bool "BF538"
help
BF538 Processor Support.
config BF539
bool "BF539"
help
BF539 Processor Support.
config BF542 config BF542
bool "BF542" bool "BF542"
help help
...@@ -174,12 +184,13 @@ config BF_REV_MIN ...@@ -174,12 +184,13 @@ config BF_REV_MIN
default 0 if (BF52x || BF54x) default 0 if (BF52x || BF54x)
default 2 if (BF537 || BF536 || BF534) default 2 if (BF537 || BF536 || BF534)
default 3 if (BF561 ||BF533 || BF532 || BF531) default 3 if (BF561 ||BF533 || BF532 || BF531)
default 4 if (BF538 || BF539)
config BF_REV_MAX config BF_REV_MAX
int int
default 2 if (BF52x || BF54x) default 2 if (BF52x || BF54x)
default 3 if (BF537 || BF536 || BF534) default 3 if (BF537 || BF536 || BF534)
default 5 if (BF561) default 5 if (BF561|| BF538 || BF539)
default 6 if (BF533 || BF532 || BF531) default 6 if (BF533 || BF532 || BF531)
choice choice
...@@ -206,11 +217,11 @@ config BF_REV_0_3 ...@@ -206,11 +217,11 @@ config BF_REV_0_3
config BF_REV_0_4 config BF_REV_0_4
bool "0.4" bool "0.4"
depends on (BF561 || BF533 || BF532 || BF531) depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
config BF_REV_0_5 config BF_REV_0_5
bool "0.5" bool "0.5"
depends on (BF561 || BF533 || BF532 || BF531) depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
config BF_REV_0_6 config BF_REV_0_6
bool "0.6" bool "0.6"
...@@ -258,7 +269,7 @@ config MEM_MT48LC16M16A2TG_75 ...@@ -258,7 +269,7 @@ config MEM_MT48LC16M16A2TG_75
config MEM_MT48LC32M8A2_75 config MEM_MT48LC32M8A2_75
bool bool
depends on (BFIN537_STAMP || PNAV10) depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
default y default y
config MEM_MT48LC8M32B2B5_7 config MEM_MT48LC8M32B2B5_7
...@@ -275,6 +286,7 @@ source "arch/blackfin/mach-bf527/Kconfig" ...@@ -275,6 +286,7 @@ source "arch/blackfin/mach-bf527/Kconfig"
source "arch/blackfin/mach-bf533/Kconfig" source "arch/blackfin/mach-bf533/Kconfig"
source "arch/blackfin/mach-bf561/Kconfig" source "arch/blackfin/mach-bf561/Kconfig"
source "arch/blackfin/mach-bf537/Kconfig" source "arch/blackfin/mach-bf537/Kconfig"
source "arch/blackfin/mach-bf538/Kconfig"
source "arch/blackfin/mach-bf548/Kconfig" source "arch/blackfin/mach-bf548/Kconfig"
menu "Board customizations" menu "Board customizations"
...@@ -318,7 +330,7 @@ config CLKIN_HZ ...@@ -318,7 +330,7 @@ config CLKIN_HZ
int "Frequency of the crystal on the board in Hz" int "Frequency of the crystal on the board in Hz"
default "11059200" if BFIN533_STAMP default "11059200" if BFIN533_STAMP
default "27000000" if BFIN533_EZKIT default "27000000" if BFIN533_EZKIT
default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT)
default "30000000" if BFIN561_EZKIT default "30000000" if BFIN561_EZKIT
default "24576000" if PNAV10 default "24576000" if PNAV10
default "10000000" if BFIN532_IP0X default "10000000" if BFIN532_IP0X
...@@ -354,7 +366,7 @@ config VCO_MULT ...@@ -354,7 +366,7 @@ config VCO_MULT
range 1 64 range 1 64
default "22" if BFIN533_EZKIT default "22" if BFIN533_EZKIT
default "45" if BFIN533_STAMP default "45" if BFIN533_STAMP
default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
default "22" if BFIN533_BLUETECHNIX_CM default "22" if BFIN533_BLUETECHNIX_CM
default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
default "20" if BFIN561_EZKIT default "20" if BFIN561_EZKIT
...@@ -716,7 +728,7 @@ config BFIN_GPTIMERS ...@@ -716,7 +728,7 @@ config BFIN_GPTIMERS
config BFIN_DMA_5XX config BFIN_DMA_5XX
bool "Enable DMA Support" bool "Enable DMA Support"
depends on (BF52x || BF53x || BF561 || BF54x) depends on (BF52x || BF53x || BF561 || BF54x || BF538 || BF539)
default y default y
help help
DMA driver for BF5xx. DMA driver for BF5xx.
......
arch/blackfin/Makefile
View file @ dc26aec2
...@@ -33,6 +33,8 @@ machine-$(CONFIG_BF533) := bf533 ...@@ -33,6 +33,8 @@ machine-$(CONFIG_BF533) := bf533
machine-$(CONFIG_BF534) := bf537 machine-$(CONFIG_BF534) := bf537
machine-$(CONFIG_BF536) := bf537 machine-$(CONFIG_BF536) := bf537
machine-$(CONFIG_BF537) := bf537 machine-$(CONFIG_BF537) := bf537
machine-$(CONFIG_BF538) := bf538
machine-$(CONFIG_BF539) := bf538
machine-$(CONFIG_BF542) := bf548 machine-$(CONFIG_BF542) := bf548
machine-$(CONFIG_BF544) := bf548 machine-$(CONFIG_BF544) := bf548
machine-$(CONFIG_BF547) := bf548 machine-$(CONFIG_BF547) := bf548
...@@ -54,6 +56,8 @@ cpu-$(CONFIG_BF533) := bf533 ...@@ -54,6 +56,8 @@ cpu-$(CONFIG_BF533) := bf533
cpu-$(CONFIG_BF534) := bf534 cpu-$(CONFIG_BF534) := bf534
cpu-$(CONFIG_BF536) := bf536 cpu-$(CONFIG_BF536) := bf536
cpu-$(CONFIG_BF537) := bf537 cpu-$(CONFIG_BF537) := bf537
cpu-$(CONFIG_BF538) := bf538
cpu-$(CONFIG_BF539) := bf539
cpu-$(CONFIG_BF542) := bf542 cpu-$(CONFIG_BF542) := bf542
cpu-$(CONFIG_BF544) := bf544 cpu-$(CONFIG_BF544) := bf544
cpu-$(CONFIG_BF547) := bf547 cpu-$(CONFIG_BF547) := bf547
......
arch/blackfin/configs/BF538-EZKIT_defconfig 0 → 100644
View file @ dc26aec2
This diff is collapsed.
arch/blackfin/include/asm/gpio.h
View file @ dc26aec2
...@@ -165,6 +165,74 @@ ...@@ -165,6 +165,74 @@
#endif #endif
#if defined(BF538_FAMILY)
/* FIXME:
* For now only support PORTF GPIOs.
* PORT C,D and E are for peripheral usage only
*/
#define MAX_BLACKFIN_GPIOS 16
#define GPIO_PF0 0 /* PF */
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PC0 16 /* PC */
#define GPIO_PC1 17
#define GPIO_PC4 20
#define GPIO_PC5 21
#define GPIO_PC6 22
#define GPIO_PC7 23
#define GPIO_PC8 24
#define GPIO_PC9 25
#define GPIO_PD0 32 /* PD */
#define GPIO_PD1 33
#define GPIO_PD2 34
#define GPIO_PD3 35
#define GPIO_PD4 36
#define GPIO_PD5 37
#define GPIO_PD6 38
#define GPIO_PD7 39
#define GPIO_PD8 40
#define GPIO_PD9 41
#define GPIO_PD10 42
#define GPIO_PD11 43
#define GPIO_PD12 44
#define GPIO_PD13 45
#define GPIO_PE0 48 /* PE */
#define GPIO_PE1 49
#define GPIO_PE2 50
#define GPIO_PE3 51
#define GPIO_PE4 52
#define GPIO_PE5 53
#define GPIO_PE6 54
#define GPIO_PE7 55
#define GPIO_PE8 56
#define GPIO_PE9 57
#define GPIO_PE10 58
#define GPIO_PE11 59
#define GPIO_PE12 60
#define GPIO_PE13 61
#define GPIO_PE14 62
#define GPIO_PE15 63
#define PORT_F GPIO_PF0
#define PORT_C GPIO_PC0
#define PORT_D GPIO_PD0
#define PORT_E GPIO_PE0
#endif
#if defined(BF527_FAMILY) || defined(BF537_FAMILY) #if defined(BF527_FAMILY) || defined(BF537_FAMILY)
#define MAX_BLACKFIN_GPIOS 48 #define MAX_BLACKFIN_GPIOS 48
......
arch/blackfin/kernel/bfin_gpio.c
View file @ dc26aec2
...@@ -119,7 +119,7 @@ enum { ...@@ -119,7 +119,7 @@ enum {
#define AWA_DUMMY_READ(...) do { } while (0) #define AWA_DUMMY_READ(...) do { } while (0)
#endif #endif
#ifdef BF533_FAMILY #if defined(BF533_FAMILY) || defined(BF538_FAMILY)
static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = { static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
(struct gpio_port_t *) FIO_FLAG_D, (struct gpio_port_t *) FIO_FLAG_D,
}; };
...@@ -202,6 +202,10 @@ static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB ...@@ -202,6 +202,10 @@ static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB
static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX}; static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
#endif #endif
#ifdef BF538_FAMILY
static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB};
#endif
#ifdef BF527_FAMILY #ifdef BF527_FAMILY
static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB}; static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB};
#endif #endif
......
arch/blackfin/mach-bf538/Kconfig 0 → 100644
View file @ dc26aec2
if (BF538 || BF539)
source "arch/blackfin/mach-bf538/boards/Kconfig"
menu "BF538 Specific Configuration"
comment "Interrupt Priority Assignment"
menu "Priority"
config IRQ_PLL_WAKEUP
int "IRQ_PLL_WAKEUP"
default 7
config IRQ_DMA0_ERROR
int "IRQ_DMA0_ERROR"
default 7
config IRQ_PPI_ERROR
int "IRQ_PPI_ERROR"
default 7
config IRQ_SPORT0_ERROR
int "IRQ_SPORT0_ERROR"
default 7
config IRQ_SPORT1_ERROR
int "IRQ_SPORT1_ERROR"
default 7
config IRQ_SPI0_ERROR
int "IRQ_SPI0_ERROR"
default 7
config IRQ_UART0_ERROR
int "IRQ_UART0_ERROR"
default 7
config IRQ_RTC
int "IRQ_RTC"
default 8
config IRQ_PPI
int "IRQ_PPI"
default 8
config IRQ_SPORT0_RX
int "IRQ_SPORT0_RX"
default 9
config IRQ_SPORT0_TX
int "IRQ_SPORT0_TX"
default 9
config IRQ_SPORT1_RX
int "IRQ_SPORT1_RX"
default 9
config IRQ_SPORT1_TX
int "IRQ_SPORT1_TX"
default 9
config IRQ_SPI0
int "IRQ_SPI0"
default 10
config IRQ_UART0_RX
int "IRQ_UART0_RX"
default 10
config IRQ_UART0_TX
int "IRQ_UART0_TX"
default 10
config IRQ_TMR0
int "IRQ_TMR0"
default 11
config IRQ_TMR1
int "IRQ_TMR1"
default 11
config IRQ_TMR2
int "IRQ_TMR2"
default 11
config IRQ_PORTF_INTA
int "IRQ_PORTF_INTA"
default 12
config IRQ_PORTF_INTB
int "IRQ_PORTF_INTB"
default 12
config IRQ_MEM0_DMA0
int "IRQ_MEM0_DMA0"
default 13
config IRQ_MEM0_DMA1
int "IRQ_MEM0_DMA1"
default 13
config IRQ_WATCH
int "IRQ_WATCH"
default 13
config IRQ_DMA1_ERROR
int "IRQ_DMA1_ERROR"
default 7
config IRQ_SPORT2_ERROR
int "IRQ_SPORT2_ERROR"
default 7
config IRQ_SPORT3_ERROR
int "IRQ_SPORT3_ERROR"
default 7
config IRQ_SPI1_ERROR
int "IRQ_SPI1_ERROR"
default 7
config IRQ_SPI2_ERROR
int "IRQ_SPI2_ERROR"
default 7
config IRQ_UART1_ERROR
int "IRQ_UART1_ERROR"
default 7
config IRQ_UART2_ERROR
int "IRQ_UART2_ERROR"
default 7
config IRQ_CAN_ERROR
int "IRQ_CAN_ERROR"
default 7
config IRQ_SPORT2_RX
int "IRQ_SPORT2_RX"
default 9
config IRQ_SPORT2_TX
int "IRQ_SPORT2_TX"
default 9
config IRQ_SPORT3_RX
int "IRQ_SPORT3_RX"
default 9
config IRQ_SPORT3_TX
int "IRQ_SPORT3_TX"
default 9
config IRQ_SPI1
int "IRQ_SPI1"
default 10
config IRQ_SPI2
int "IRQ_SPI2"
default 10
config IRQ_UART1_RX
int "IRQ_UART1_RX"
default 10
config IRQ_UART1_TX
int "IRQ_UART1_TX"
default 10
config IRQ_UART2_RX
int "IRQ_UART2_RX"
default 10
config IRQ_UART2_TX
int "IRQ_UART2_TX"
default 10
config IRQ_TWI0
int "IRQ_TWI0"
default 11
config IRQ_TWI1
int "IRQ_TWI1"
default 11
config IRQ_CAN_RX
int "IRQ_CAN_RX"
default 11
config IRQ_CAN_TX
int "IRQ_CAN_TX"
default 11
config IRQ_MEM1_DMA0
int "IRQ_MEM1_DMA0"
default 13
config IRQ_MEM1_DMA1
int "IRQ_MEM1_DMA1"
default 13
help
Enter the priority numbers between 7-13 ONLY. Others are Reserved.
This applies to all the above. It is not recommended to assign the
highest priority number 7 to UART or any other device.
endmenu
endmenu
endif
arch/blackfin/mach-bf538/Makefile 0 → 100644
View file @ dc26aec2
#
# arch/blackfin/mach-bf538/Makefile
#
extra-y := head.o
obj-y := ints-priority.o dma.o
arch/blackfin/mach-bf538/boards/Kconfig 0 → 100644
View file @ dc26aec2
choice
prompt "System type"
default BFIN538_EZKIT
help
Select your board!
config BFIN538_EZKIT
bool "BF538-EZKIT"
help
BF538-EZKIT-LITE board support.
endchoice
arch/blackfin/mach-bf538/boards/Makefile 0 → 100644
View file @ dc26aec2
#
# arch/blackfin/mach-bf538/boards/Makefile
#
obj-$(CONFIG_BFIN538_EZKIT) += ezkit.o
arch/blackfin/mach-bf538/boards/ezkit.c 0 → 100644
View file @ dc26aec2
This diff is collapsed.
arch/blackfin/mach-bf538/dma.c 0 → 100644
View file @ dc26aec2
/*
* File: arch/blackfin/mach-bf538/dma.c
* Based on:
* Author:
*
* Created:
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Modified:
* Copyright 2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,
(struct dma_register *) DMA3_NEXT_DESC_PTR,
(struct dma_register *) DMA4_NEXT_DESC_PTR,
(struct dma_register *) DMA5_NEXT_DESC_PTR,
(struct dma_register *) DMA6_NEXT_DESC_PTR,
(struct dma_register *) DMA7_NEXT_DESC_PTR,
(struct dma_register *) DMA8_NEXT_DESC_PTR,
(struct dma_register *) DMA9_NEXT_DESC_PTR,
(struct dma_register *) DMA10_NEXT_DESC_PTR,
(struct dma_register *) DMA11_NEXT_DESC_PTR,
(struct dma_register *) DMA12_NEXT_DESC_PTR,
(struct dma_register *) DMA13_NEXT_DESC_PTR,
(struct dma_register *) DMA14_NEXT_DESC_PTR,
(struct dma_register *) DMA15_NEXT_DESC_PTR,
(struct dma_register *) DMA16_NEXT_DESC_PTR,
(struct dma_register *) DMA17_NEXT_DESC_PTR,
(struct dma_register *) DMA18_NEXT_DESC_PTR,
(struct dma_register *) DMA19_NEXT_DESC_PTR,
(struct dma_register *) MDMA0_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA0_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA0_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA0_S1_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
};
EXPORT_SYMBOL(dma_io_base_addr);
int channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_PPI:
ret_irq = IRQ_PPI;
break;
case CH_UART0_RX:
ret_irq = IRQ_UART0_RX;
break;
case CH_UART0_TX:
ret_irq = IRQ_UART0_TX;
break;
case CH_UART1_RX:
ret_irq = IRQ_UART1_RX;
break;
case CH_UART1_TX:
ret_irq = IRQ_UART1_TX;
break;
case CH_UART2_RX:
ret_irq = IRQ_UART2_RX;
break;
case CH_UART2_TX:
ret_irq = IRQ_UART2_TX;
break;
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
break;
case CH_SPORT2_RX:
ret_irq = IRQ_SPORT2_RX;
break;
case CH_SPORT2_TX:
ret_irq = IRQ_SPORT2_TX;
break;
case CH_SPORT3_RX:
ret_irq = IRQ_SPORT3_RX;
break;
case CH_SPORT3_TX:
ret_irq = IRQ_SPORT3_TX;
break;
case CH_SPI0:
ret_irq = IRQ_SPI0;
break;
case CH_SPI1:
ret_irq = IRQ_SPI1;
break;
case CH_SPI2:
ret_irq = IRQ_SPI2;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MEM0_DMA0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MEM0_DMA1;
break;
case CH_MEM_STREAM2_SRC:
case CH_MEM_STREAM2_DEST:
ret_irq = IRQ_MEM1_DMA0;
break;
case CH_MEM_STREAM3_SRC:
case CH_MEM_STREAM3_DEST:
ret_irq = IRQ_MEM1_DMA1;
break;
}
return ret_irq;
}
arch/blackfin/mach-bf538/head.S 0 → 100644
View file @ dc26aec2
/*
* File: arch/blackfin/mach-bf538/head.S
* Based on:
* Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
*
* Created: 1998
* Description: bf533 startup file
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/blackfin.h>
#ifdef CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif
.section .l1.text
#ifdef CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)
p0.h = hi(SIC_IWR0);
p0.l = lo(SIC_IWR0);
r0.l = 0x1;
r0.h = 0x0;
[p0] = r0;
SSYNC;
/*
* Set PLL_CTL
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
* - [7] = output delay (add 200ps of delay to mem signals)
* - [6] = input delay (add 200ps of input delay to mem signals)
* - [5] = PDWN : 1=All Clocks off
* - [3] = STOPCK : 1=Core Clock off
* - [1] = PLL_OFF : 1=Disable Power to PLL
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
* all other bits set to zero
*/
p0.h = hi(PLL_LOCKCNT);
p0.l = lo(PLL_LOCKCNT);
r0 = 0x300(Z);
w[p0] = r0.l;
ssync;
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
[P2] = R0;
SSYNC;
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over, */
r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
r0 = r1 | r0;
r1 = PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
#ifdef ANOMALY_05000265
BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
#endif
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */
cli r2; /* Disable interrupts */
ssync;
w[p0] = r0.l; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2; /* Enable interrupts */
.Lcheck_again:
p0.h = hi(PLL_STAT);
p0.l = lo(PLL_STAT);
R0 = W[P0](Z);
CC = BITTST(R0,5);
if ! CC jump .Lcheck_again;
/* Configure SCLK & CCLK Dividers */
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
p0.h = hi(PLL_DIV);
p0.l = lo(PLL_DIV);
w[p0] = r0.l;
ssync;
p0.l = lo(EBIU_SDRRC);
p0.h = hi(EBIU_SDRRC);
r0 = mem_SDRRC;
w[p0] = r0.l;
ssync;
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITCLR (R0, 24);
p0.h = hi(EBIU_SDSTAT);
p0.l = lo(EBIU_SDSTAT);
r2.l = w[p0];
cc = bittst(r2,3);
if !cc jump .Lskip;
NOP;
BITSET (R0, 23);
.Lskip:
[P2] = R0;
SSYNC;
R0.L = lo(mem_SDGCTL);
R0.H = hi(mem_SDGCTL);
R1 = [p2];
R1 = R1 | R0;
[P2] = R1;
SSYNC;
RTS;
ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
arch/blackfin/mach-bf538/include/mach/anomaly.h 0 → 100644
View file @ dc26aec2
/*
* File: include/asm-blackfin/mach-bf538/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
* - Revision F, 06/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List
* - Revision K, 06/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
#if __SILICON_REVISION__ < 4
# error will not work on BF538 silicon version 0.0, 0.1, 0.2 or 0.3
#endif
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
#define ANOMALY_05000166 (1)
/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
#define ANOMALY_05000179 (1)
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
#define ANOMALY_05000180 (1)
/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
#define ANOMALY_05000193 (1)
/* Current DMA Address Shows Wrong Value During Carry Fix */
#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
/* NMI Event at Boot Time Results in Unpredictable State */
#define ANOMALY_05000219 (1)
/* SPI Slave Boot Mode Modifies Registers from Reset Value */
#define ANOMALY_05000229 (1)
/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
#define ANOMALY_05000233 (1)
/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Maximum External Clock Speed for Timers */
#define ANOMALY_05000253 (1)
/* DCPLB_FAULT_ADDR MMR register may be corrupted */
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
/* Writes to Synchronous SDRAM Memory May Be Lost */
#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
/* False Hardware Error Exception when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
/* Hibernate Leakage Current Is Higher Than Specified */
#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
#define ANOMALY_05000294 (1)
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
/* PPI Is Level-Sensitive on First Transfer */
#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
#define ANOMALY_05000318 (__SILICON_REVISION__ < 4)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
/* New Feature: Open-Drain GPIO Outputs on PC1 and PC4 (Not Available on Older Silicon) */
#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ < 4)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000230 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000363 (0)
#endif
arch/blackfin/mach-bf538/include/mach/bf538.h 0 → 100644
View file @ dc26aec2
/*
* File: include/asm-blackfin/mach-bf538/bf538.h
* Based on: include/asm-blackfin/mach-bf537/bf537.h
* Author: Michael Hennerich (michael.hennerich@analog.com)
*
* Created:
* Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF527
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MACH_BF538_H__
#define __MACH_BF538_H__
#define OFFSET_(x) ((x) & 0x0000FFFF)
/*some misc defines*/
#define IMASK_IVG15 0x8000
#define IMASK_IVG14 0x4000
#define IMASK_IVG13 0x2000
#define IMASK_IVG12 0x1000
#define IMASK_IVG11 0x0800
#define IMASK_IVG10 0x0400
#define IMASK_IVG9 0x0200
#define IMASK_IVG8 0x0100
#define IMASK_IVG7 0x0080
#define IMASK_IVGTMR 0x0040
#define IMASK_IVGHW 0x0020
/***************************/
#define BFIN_DSUBBANKS 4
#define BFIN_DWAYS 2
#define BFIN_DLINES 64
#define BFIN_ISUBBANKS 4
#define BFIN_IWAYS 4
#define BFIN_ILINES 32
#define WAY0_L 0x1
#define WAY1_L 0x2
#define WAY01_L 0x3
#define WAY2_L 0x4
#define WAY02_L 0x5
#define WAY12_L 0x6
#define WAY012_L 0x7
#define WAY3_L 0x8
#define WAY03_L 0x9
#define WAY13_L 0xA
#define WAY013_L 0xB
#define WAY32_L 0xC
#define WAY320_L 0xD
#define WAY321_L 0xE
#define WAYALL_L 0xF
#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
/********************************* EBIU Settings ************************************/
#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
#ifdef CONFIG_C_AMBEN_ALL
#define V_AMBEN AMBEN_ALL
#endif
#ifdef CONFIG_C_AMBEN
#define V_AMBEN 0x0
#endif
#ifdef CONFIG_C_AMBEN_B0
#define V_AMBEN AMBEN_B0
#endif
#ifdef CONFIG_C_AMBEN_B0_B1
#define V_AMBEN AMBEN_B0_B1
#endif
#ifdef CONFIG_C_AMBEN_B0_B1_B2
#define V_AMBEN AMBEN_B0_B1_B2
#endif
#ifdef CONFIG_C_AMCKEN
#define V_AMCKEN AMCKEN
#else
#define V_AMCKEN 0x0
#endif
#ifdef CONFIG_C_CDPRIO
#define V_CDPRIO 0x100
#else
#define V_CDPRIO 0x0
#endif
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
#ifdef CONFIG_BF538
#define CPU "BF538"
#define CPUID 0x27C4
#endif
#ifdef CONFIG_BF539
#define CPU "BF539"
#define CPUID 0x27C4 /* FXIME:? */
#endif
#ifndef CPU
#error Unknown CPU type - This kernel doesn't seem to be configured properly
#endif
#endif /* __MACH_BF538_H__ */
arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h 0 → 100644
View file @ dc26aec2
/*
* file: include/asm-blackfin/mach-bf538/bfin_serial_5xx.h
* based on:
* author:
*
* created:
* description:
* blackfin serial driver header files
* rev:
*
* modified:
*
*
* bugs: enter bugs at http://blackfin.uclinux.org/
*
* this program is free software; you can redistribute it and/or modify
* it under the terms of the gnu general public license as published by
* the free software foundation; either version 2, or (at your option)
* any later version.
*
* this program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose. see the
* gnu general public license for more details.
*
* you should have received a copy of the gnu general public license
* along with this program; see the file copying.
* if not, write to the free software foundation,
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
*/
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
# define CONFIG_UART0_CTS_PIN -1
# endif
# ifndef CONFIG_UART0_RTS_PIN
# define CONFIG_UART0_RTS_PIN -1
# endif
# ifndef CONFIG_UART1_CTS_PIN
# define CONFIG_UART1_CTS_PIN -1
# endif
# ifndef CONFIG_UART1_RTS_PIN
# define CONFIG_UART1_RTS_PIN -1
# endif
#endif
#define BFIN_UART_TX_FIFO_SIZE 2
/*
* The pin configuration is different from schematic
*/
struct bfin_serial_port {
struct uart_port port;
unsigned int old_status;
unsigned int lsr;
#ifdef CONFIG_SERIAL_BFIN_DMA
int tx_done;
int tx_count;
struct circ_buf rx_dma_buf;
struct timer_list rx_dma_timer;
int rx_dma_nrows;
unsigned int tx_dma_channel;
unsigned int rx_dma_channel;
struct work_struct tx_dma_workqueue;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
struct timer_list cts_timer;
int cts_pin;
int rts_pin;
#endif
};
/* The hardware clears the LSR bits upon read, so we need to cache
* some of the more fun bits in software so they don't get lost
* when checking the LSR in other code paths (TX).
*/
static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
{
unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
uart->lsr |= (lsr & (BI|FE|PE|OE));
return lsr | uart->lsr;
}
static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
{
uart->lsr = 0;
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
#ifdef CONFIG_SERIAL_BFIN_DMA
unsigned int uart_tx_dma_channel;
unsigned int uart_rx_dma_channel;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
int uart_cts_pin;
int uart_rts_pin;
#endif
};
struct bfin_serial_res bfin_serial_resource[] = {
#ifdef CONFIG_SERIAL_BFIN_UART0
{
0xFFC00400,
IRQ_UART0_RX,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART0_TX,
CH_UART0_RX,
#endif
#ifdef CONFIG_BFIN_UART0_CTSRTS
CONFIG_UART0_CTS_PIN,
CONFIG_UART0_RTS_PIN,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
{
0xFFC02000,
IRQ_UART1_RX,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART1_TX,
CH_UART1_RX,
#endif
#ifdef CONFIG_BFIN_UART1_CTSRTS
CONFIG_UART1_CTS_PIN,
CONFIG_UART1_RTS_PIN,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART2
{
0xFFC02100,
IRQ_UART2_RX,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART2_TX,
CH_UART2_RX,
#endif
#ifdef CONFIG_BFIN_UART2_CTSRTS
CONFIG_UART2_CTS_PIN,
CONFIG_UART2_RTS_PIN,
#endif
},
#endif
};
#define DRIVER_NAME "bfin-uart"
arch/blackfin/mach-bf538/include/mach/bfin_sir.h 0 → 100644
View file @ dc26aec2
/*
* Blackfin Infra-red Driver
*
* Copyright 2006-2008 Analog Devices Inc.
*
* Enter bugs at http://blackfin.uclinux.org/
*
* Licensed under the GPL-2 or later.
*
*/
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
#ifdef CONFIG_SIR_BFIN_DMA
struct dma_rx_buf {
char *buf;
int head;
int tail;
};
#endif /* CONFIG_SIR_BFIN_DMA */
struct bfin_sir_port {
unsigned char __iomem *membase;
unsigned int irq;
unsigned int lsr;
unsigned long clk;
struct net_device *dev;
#ifdef CONFIG_SIR_BFIN_DMA
int tx_done;
struct dma_rx_buf rx_dma_buf;
struct timer_list rx_dma_timer;
int rx_dma_nrows;
#endif /* CONFIG_SIR_BFIN_DMA */
unsigned int tx_dma_channel;
unsigned int rx_dma_channel;
};
struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
struct bfin_sir_port_res {
unsigned long base_addr;
int irq;
unsigned int rx_dma_channel;
unsigned int tx_dma_channel;
};
struct bfin_sir_port_res bfin_sir_port_resource[] = {
#ifdef CONFIG_BFIN_SIR0
{
0xFFC00400,
IRQ_UART0_RX,
CH_UART0_RX,
CH_UART0_TX,
},
#endif
#ifdef CONFIG_BFIN_SIR1
{
0xFFC02000,
IRQ_UART1_RX,
CH_UART1_RX,
CH_UART1_TX,
},
#endif
#ifdef CONFIG_BFIN_SIR2
{
0xFFC02100,
IRQ_UART2_RX,
CH_UART2_RX,
CH_UART2_TX,
},
#endif
};
int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
struct bfin_sir_self {
struct bfin_sir_port *sir_port;
spinlock_t lock;
unsigned int open;
int speed;
int newspeed;
struct sk_buff *txskb;
struct sk_buff *rxskb;
struct net_device_stats stats;
struct device *dev;
struct irlap_cb *irlap;
struct qos_info qos;
iobuff_t tx_buff;
iobuff_t rx_buff;
struct work_struct work;
int mtt;
};
static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
{
unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
port->lsr |= (lsr & (BI|FE|PE|OE));
return lsr | port->lsr;
}
static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
{
port->lsr = 0;
bfin_read16(port->membase + OFFSET_LSR);
}
#define DRIVER_NAME "bfin_sir"
static int bfin_sir_hw_init(void)
{
int ret = -ENODEV;
#ifdef CONFIG_BFIN_SIR0
ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
if (ret)
return ret;
ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
if (ret)
return ret;
#endif
#ifdef CONFIG_BFIN_SIR1
ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
if (ret)
return ret;
ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
if (ret)
return ret;
#endif
#ifdef CONFIG_BFIN_SIR2
ret = peripheral_request(P_UART2_TX, DRIVER_NAME);
if (ret)
return ret;
ret = peripheral_request(P_UART2_RX, DRIVER_NAME);
if (ret)
return ret;
#endif
return ret;
}
arch/blackfin/mach-bf538/include/mach/blackfin.h 0 → 100644
View file @ dc26aec2
/*
* File: include/asm-blackfin/mach-bf538/blackfin.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _MACH_BLACKFIN_H_
#define _MACH_BLACKFIN_H_
#define BF538_FAMILY
#include "bf538.h"
#include "mem_map.h"
#include "defBF539.h"
#include "anomaly.h"
#if !defined(__ASSEMBLY__)
#include "cdefBF538.h"
#if defined(CONFIG_BF539)
#include "cdefBF539.h"
#endif
#endif
/* UART_IIR Register */
#define STATUS(x) ((x << 1) & 0x06)
#define STATUS_P1 0x02
#define STATUS_P0 0x01
#define BFIN_UART_NR_PORTS 3
#define OFFSET_THR 0x00 /* Transmit Holding register */
#define OFFSET_RBR 0x00 /* Receive Buffer register */
#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
#define OFFSET_IER 0x04 /* Interrupt Enable Register */
#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
#define OFFSET_LCR 0x0C /* Line Control Register */
#define OFFSET_MCR 0x10 /* Modem Control Register */
#define OFFSET_LSR 0x14 /* Line Status Register */
#define OFFSET_MSR 0x18 /* Modem Status Register */
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
#define OFFSET_GCTL 0x24 /* Global Control Register */
#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_D0_IRQ_STATUS
#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_D0_START_ADDR
#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_S0_START_ADDR
#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_D0_X_COUNT
#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_S0_X_COUNT
#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_D0_Y_COUNT
#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_S0_Y_COUNT
#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_D0_X_MODIFY
#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_S0_X_MODIFY
#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_D0_Y_MODIFY
#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_S0_Y_MODIFY
#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_S0_CONFIG
#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_D0_CONFIG
#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_D0_IRQ_STATUS
#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_S0_IRQ_STATUS
/* DPMC*/
#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
#define STOPCK_OFF STOPCK
/* PLL_DIV Masks */
#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
#endif
arch/blackfin/mach-bf538/include/mach/cdefBF538.h 0 → 100644
View file @ dc26aec2
This diff is collapsed.
arch/blackfin/mach-bf538/include/mach/cdefBF539.h 0 → 100644
View file @ dc26aec2
This diff is collapsed.
arch/blackfin/mach-bf538/include/mach/defBF539.h 0 → 100644
View file @ dc26aec2
This diff is collapsed.
arch/blackfin/mach-bf538/include/mach/dma.h 0 → 100644
View file @ dc26aec2
/*
* file: include/asm-blackfin/mach-bf538/dma.h
* based on:
* author:
*
* created:
* description:
* system mmr register map
* rev:
*
* modified:
*
*
* bugs: enter bugs at http://blackfin.uclinux.org/
*
* this program is free software; you can redistribute it and/or modify
* it under the terms of the gnu general public license as published by
* the free software foundation; either version 2, or (at your option)
* any later version.
*
* this program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose. see the
* gnu general public license for more details.
*
* you should have received a copy of the gnu general public license
* along with this program; see the file copying.
* if not, write to the free software foundation,
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
*/
#ifndef _MACH_DMA_H_
#define _MACH_DMA_H_
#define CH_PPI 0
#define CH_SPORT0_RX 1
#define CH_SPORT0_TX 2
#define CH_SPORT1_RX 3
#define CH_SPORT1_TX 4
#define CH_SPI0 5
#define CH_UART0_RX 6
#define CH_UART0_TX 7
#define CH_SPORT2_RX 8
#define CH_SPORT2_TX 9
#define CH_SPORT3_RX 10
#define CH_SPORT3_TX 11
#define CH_SPI1 14
#define CH_SPI2 15
#define CH_UART1_RX 16
#define CH_UART1_TX 17
#define CH_UART2_RX 18
#define CH_UART2_TX 19
#define CH_MEM_STREAM0_DEST 20
#define CH_MEM_STREAM0_SRC 21
#define CH_MEM_STREAM1_DEST 22
#define CH_MEM_STREAM1_SRC 23
#define CH_MEM_STREAM2_DEST 24
#define CH_MEM_STREAM2_SRC 25
#define CH_MEM_STREAM3_DEST 26
#define CH_MEM_STREAM3_SRC 27
#define MAX_BLACKFIN_DMA_CHANNEL 28
#endif
arch/blackfin/mach-bf538/include/mach/irq.h 0 → 100644
View file @ dc26aec2
/*
* file: include/asm-blackfin/mach-bf538/irq.h
* based on: include/asm-blackfin/mach-bf537/irq.h
* author: Michael Hennerich (michael.hennerich@analog.com)
*
* created:
* description:
* system mmr register map
* rev:
*
* modified:
*
*
* bugs: enter bugs at http://blackfin.uclinux.org/
*
* this program is free software; you can redistribute it and/or modify
* it under the terms of the gnu general public license as published by
* the free software foundation; either version 2, or (at your option)
* any later version.
*
* this program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose. see the
* gnu general public license for more details.
*
* you should have received a copy of the gnu general public license
* along with this program; see the file copying.
* if not, write to the free software foundation,
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
*/
#ifndef _BF538_IRQ_H_
#define _BF538_IRQ_H_
/*
* Interrupt source definitions
Event Source Core Event Name
Core Emulation **
Events (highest priority) EMU 0
Reset RST 1
NMI NMI 2
Exception EVX 3
Reserved -- 4
Hardware Error IVHW 5
Core Timer IVTMR 6 *
.....
Software Interrupt 1 IVG14 31
Software Interrupt 2 --
(lowest priority) IVG15 32 *
*/
#define NR_PERI_INTS (2 * 32)
/* The ABSTRACT IRQ definitions */
/** the first seven of the following are fixed, the rest you change if you need to **/
#define IRQ_EMU 0 /* Emulation */
#define IRQ_RST 1 /* reset */
#define IRQ_NMI 2 /* Non Maskable */
#define IRQ_EVX 3 /* Exception */
#define IRQ_UNUSED 4 /* - unused interrupt */
#define IRQ_HWERR 5 /* Hardware Error */
#define IRQ_CORETMR 6 /* Core timer */
#define BFIN_IRQ(x) ((x) + 7)
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */
#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */
#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */
#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */
#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */
#define IRQ_RTC BFIN_IRQ(7) /* RTC */
#define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */
#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */
#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */
#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */
#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */
#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */
#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */
#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */
#define IRQ_TMR0 BFIN_IRQ(16) /* Timer 0 */
#define IRQ_TMR1 BFIN_IRQ(17) /* Timer 1 */
#define IRQ_TMR2 BFIN_IRQ(18) /* Timer 2 */
#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */
#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */
#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */
#define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */
#define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */
#define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */
#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */
#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */
#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */
#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */
#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */
#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */
#define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */
#define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */
#define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */
#define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */
#define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */
#define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */
#define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */
#define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */
#define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */
#define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */
#define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */
#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */
#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */
#define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */
#define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */
#define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */
#define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
#define IRQ_PF0 71
#define IRQ_PF1 72
#define IRQ_PF2 73
#define IRQ_PF3 74
#define IRQ_PF4 75
#define IRQ_PF5 76
#define IRQ_PF6 77
#define IRQ_PF7 78
#define IRQ_PF8 79
#define IRQ_PF9 80
#define IRQ_PF10 81
#define IRQ_PF11 82
#define IRQ_PF12 83
#define IRQ_PF13 84
#define IRQ_PF14 85
#define IRQ_PF15 86
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_IRQS (IRQ_PF15+1)
#define IVG7 7
#define IVG8 8
#define IVG9 9
#define IVG10 10
#define IVG11 11
#define IVG12 12
#define IVG13 13
#define IVG14 14
#define IVG15 15
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#define IRQ_DMA0_ERROR_POS 4
#define IRQ_PPI_ERROR_POS 8
#define IRQ_SPORT0_ERROR_POS 12
#define IRQ_SPORT1_ERROR_POS 16
#define IRQ_SPI0_ERROR_POS 20
#define IRQ_UART0_ERROR_POS 24
#define IRQ_RTC_POS 28
/* IAR1 BIT FIELDS */
#define IRQ_PPI_POS 0
#define IRQ_SPORT0_RX_POS 4
#define IRQ_SPORT0_TX_POS 8
#define IRQ_SPORT1_RX_POS 12
#define IRQ_SPORT1_TX_POS 16
#define IRQ_SPI0_POS 20
#define IRQ_UART0_RX_POS 24
#define IRQ_UART0_TX_POS 28
/* IAR2 BIT FIELDS */
#define IRQ_TMR0_POS 0
#define IRQ_TMR1_POS 4
#define IRQ_TMR2_POS 8
#define IRQ_PORTF_INTA_POS 12
#define IRQ_PORTF_INTB_POS 16
#define IRQ_MEM0_DMA0_POS 20
#define IRQ_MEM0_DMA1_POS 24
#define IRQ_WATCH_POS 28
/* IAR3 BIT FIELDS */
#define IRQ_DMA1_ERROR_POS 0
#define IRQ_SPORT2_ERROR_POS 4
#define IRQ_SPORT3_ERROR_POS 8
#define IRQ_SPI1_ERROR_POS 16
#define IRQ_SPI2_ERROR_POS 20
#define IRQ_UART1_ERROR_POS 24
#define IRQ_UART2_ERROR_POS 28
/* IAR4 BIT FIELDS */
#define IRQ_CAN_ERROR_POS 0
#define IRQ_SPORT2_RX_POS 4
#define IRQ_SPORT2_TX_POS 8
#define IRQ_SPORT3_RX_POS 12
#define IRQ_SPORT3_TX_POS 16
#define IRQ_SPI1_POS 28
/* IAR5 BIT FIELDS */
#define IRQ_SPI2_POS 0
#define IRQ_UART1_RX_POS 4
#define IRQ_UART1_TX_POS 8
#define IRQ_UART2_RX_POS 12
#define IRQ_UART2_TX_POS 16
#define IRQ_TWI0_POS 20
#define IRQ_TWI1_POS 24
#define IRQ_CAN_RX_POS 28
/* IAR6 BIT FIELDS */
#define IRQ_CAN_TX_POS 0
#define IRQ_MEM1_DMA0_POS 4
#define IRQ_MEM1_DMA1_POS 8
#endif /* _BF538_IRQ_H_ */
arch/blackfin/mach-bf538/include/mach/mem_init.h 0 → 100644
View file @ dc26aec2
/*
* File: include/asm-blackfin/mach-bf538/mem_init.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75)
#if (CONFIG_SCLK_HZ > 119402985)
#define SDRAM_tRP TRP_2
#define SDRAM_tRP_num 2
#define SDRAM_tRAS TRAS_7
#define SDRAM_tRAS_num 7
#define SDRAM_tRCD TRCD_2
#define SDRAM_tWR TWR_2
#endif
#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
#define SDRAM_tRP TRP_2
#define SDRAM_tRP_num 2
#define SDRAM_tRAS TRAS_6
#define SDRAM_tRAS_num 6
#define SDRAM_tRCD TRCD_2
#define SDRAM_tWR TWR_2
#endif
#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
#define SDRAM_tRP TRP_2
#define SDRAM_tRP_num 2
#define SDRAM_tRAS TRAS_5
#define SDRAM_tRAS_num 5
#define SDRAM_tRCD TRCD_2
#define SDRAM_tWR TWR_2
#endif
#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
#define SDRAM_tRP TRP_2
#define SDRAM_tRP_num 2
#define SDRAM_tRAS TRAS_4
#define SDRAM_tRAS_num 4
#define SDRAM_tRCD TRCD_2
#define SDRAM_tWR TWR_2
#endif
#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
#define SDRAM_tRP TRP_2
#define SDRAM_tRP_num 2
#define SDRAM_tRAS TRAS_3
#define SDRAM_tRAS_num 3
#define SDRAM_tRCD TRCD_2
#define SDRAM_tWR TWR_2
#endif
#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
#define SDRAM_tRP TRP_1
#define SDRAM_tRP_num 1
#define SDRAM_tRAS TRAS_4
#define SDRAM_tRAS_num 3
#define SDRAM_tRCD TRCD_1
#define SDRAM_tWR TWR_2
#endif
#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
#define SDRAM_tRP TRP_1
#define SDRAM_tRP_num 1
#define SDRAM_tRAS TRAS_3
#define SDRAM_tRAS_num 3
#define SDRAM_tRCD TRCD_1
#define SDRAM_tWR TWR_2
#endif
#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
#define SDRAM_tRP TRP_1
#define SDRAM_tRP_num 1
#define SDRAM_tRAS TRAS_2
#define SDRAM_tRAS_num 2
#define SDRAM_tRCD TRCD_1
#define SDRAM_tWR TWR_2
#endif
#if (CONFIG_SCLK_HZ <= 29850746)
#define SDRAM_tRP TRP_1
#define SDRAM_tRP_num 1
#define SDRAM_tRAS TRAS_1
#define SDRAM_tRAS_num 1
#define SDRAM_tRCD TRCD_1
#define SDRAM_tWR TWR_2
#endif
#endif
#if (CONFIG_MEM_MT48LC16M16A2TG_75)
/*SDRAM INFORMATION: */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_MT48LC16M8A2TG_75)
/*SDRAM INFORMATION: */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_MT48LC32M8A2_75)
/*SDRAM INFORMATION: */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
/*SDRAM INFORMATION: */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_GENERIC_BOARD)
/*SDRAM INFORMATION: Modify this for your board */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif
/* Equation from section 17 (p17-46) of BF533 HRM */
#define mem_SDRRC ((((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num))
/* Enable SCLK Out */
#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
#if defined CONFIG_CLKIN_HALF
#define CLKIN_HALF 1
#else
#define CLKIN_HALF 0
#endif
#if defined CONFIG_PLL_BYPASS
#define PLL_BYPASS 1
#else
#define PLL_BYPASS 0
#endif
/***************************************Currently Not Being Used *********************************/
#define flash_EBIU_AMBCTL_WAT (((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1)
#define flash_EBIU_AMBCTL_RAT (((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1)
#define flash_EBIU_AMBCTL_HT (((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)))
#define flash_EBIU_AMBCTL_ST (((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1)
#define flash_EBIU_AMBCTL_TT (((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1)
#if (flash_EBIU_AMBCTL_TT > 3)
#define flash_EBIU_AMBCTL0_TT B0TT_4
#endif
#if (flash_EBIU_AMBCTL_TT == 3)
#define flash_EBIU_AMBCTL0_TT B0TT_3
#endif
#if (flash_EBIU_AMBCTL_TT == 2)
#define flash_EBIU_AMBCTL0_TT B0TT_2
#endif
#if (flash_EBIU_AMBCTL_TT < 2)
#define flash_EBIU_AMBCTL0_TT B0TT_1
#endif
#if (flash_EBIU_AMBCTL_ST > 3)
#define flash_EBIU_AMBCTL0_ST B0ST_4
#endif
#if (flash_EBIU_AMBCTL_ST == 3)
#define flash_EBIU_AMBCTL0_ST B0ST_3
#endif
#if (flash_EBIU_AMBCTL_ST == 2)
#define flash_EBIU_AMBCTL0_ST B0ST_2
#endif
#if (flash_EBIU_AMBCTL_ST < 2)
#define flash_EBIU_AMBCTL0_ST B0ST_1
#endif
#if (flash_EBIU_AMBCTL_HT > 2)
#define flash_EBIU_AMBCTL0_HT B0HT_3
#endif
#if (flash_EBIU_AMBCTL_HT == 2)
#define flash_EBIU_AMBCTL0_HT B0HT_2
#endif
#if (flash_EBIU_AMBCTL_HT == 1)
#define flash_EBIU_AMBCTL0_HT B0HT_1
#endif
#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
#define flash_EBIU_AMBCTL0_HT B0HT_0
#endif
#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
#define flash_EBIU_AMBCTL0_HT B0HT_1
#endif
#if (flash_EBIU_AMBCTL_WAT > 14)
#define flash_EBIU_AMBCTL0_WAT B0WAT_15
#endif
#if (flash_EBIU_AMBCTL_WAT == 14)
#define flash_EBIU_AMBCTL0_WAT B0WAT_14
#endif
#if (flash_EBIU_AMBCTL_WAT == 13)
#define flash_EBIU_AMBCTL0_WAT B0WAT_13
#endif
#if (flash_EBIU_AMBCTL_WAT == 12)
#define flash_EBIU_AMBCTL0_WAT B0WAT_12
#endif
#if (flash_EBIU_AMBCTL_WAT == 11)
#define flash_EBIU_AMBCTL0_WAT B0WAT_11
#endif
#if (flash_EBIU_AMBCTL_WAT == 10)
#define flash_EBIU_AMBCTL0_WAT B0WAT_10
#endif
#if (flash_EBIU_AMBCTL_WAT == 9)
#define flash_EBIU_AMBCTL0_WAT B0WAT_9
#endif
#if (flash_EBIU_AMBCTL_WAT == 8)
#define flash_EBIU_AMBCTL0_WAT B0WAT_8
#endif
#if (flash_EBIU_AMBCTL_WAT == 7)
#define flash_EBIU_AMBCTL0_WAT B0WAT_7
#endif
#if (flash_EBIU_AMBCTL_WAT == 6)
#define flash_EBIU_AMBCTL0_WAT B0WAT_6
#endif
#if (flash_EBIU_AMBCTL_WAT == 5)
#define flash_EBIU_AMBCTL0_WAT B0WAT_5
#endif
#if (flash_EBIU_AMBCTL_WAT == 4)
#define flash_EBIU_AMBCTL0_WAT B0WAT_4
#endif
#if (flash_EBIU_AMBCTL_WAT == 3)
#define flash_EBIU_AMBCTL0_WAT B0WAT_3
#endif
#if (flash_EBIU_AMBCTL_WAT == 2)
#define flash_EBIU_AMBCTL0_WAT B0WAT_2
#endif
#if (flash_EBIU_AMBCTL_WAT == 1)
#define flash_EBIU_AMBCTL0_WAT B0WAT_1
#endif
#if (flash_EBIU_AMBCTL_RAT > 14)
#define flash_EBIU_AMBCTL0_RAT B0RAT_15
#endif
#if (flash_EBIU_AMBCTL_RAT == 14)
#define flash_EBIU_AMBCTL0_RAT B0RAT_14
#endif
#if (flash_EBIU_AMBCTL_RAT == 13)
#define flash_EBIU_AMBCTL0_RAT B0RAT_13
#endif
#if (flash_EBIU_AMBCTL_RAT == 12)
#define flash_EBIU_AMBCTL0_RAT B0RAT_12
#endif
#if (flash_EBIU_AMBCTL_RAT == 11)
#define flash_EBIU_AMBCTL0_RAT B0RAT_11
#endif
#if (flash_EBIU_AMBCTL_RAT == 10)
#define flash_EBIU_AMBCTL0_RAT B0RAT_10
#endif
#if (flash_EBIU_AMBCTL_RAT == 9)
#define flash_EBIU_AMBCTL0_RAT B0RAT_9
#endif
#if (flash_EBIU_AMBCTL_RAT == 8)
#define flash_EBIU_AMBCTL0_RAT B0RAT_8
#endif
#if (flash_EBIU_AMBCTL_RAT == 7)
#define flash_EBIU_AMBCTL0_RAT B0RAT_7
#endif
#if (flash_EBIU_AMBCTL_RAT == 6)
#define flash_EBIU_AMBCTL0_RAT B0RAT_6
#endif
#if (flash_EBIU_AMBCTL_RAT == 5)
#define flash_EBIU_AMBCTL0_RAT B0RAT_5
#endif
#if (flash_EBIU_AMBCTL_RAT == 4)
#define flash_EBIU_AMBCTL0_RAT B0RAT_4
#endif
#if (flash_EBIU_AMBCTL_RAT == 3)
#define flash_EBIU_AMBCTL0_RAT B0RAT_3
#endif
#if (flash_EBIU_AMBCTL_RAT == 2)
#define flash_EBIU_AMBCTL0_RAT B0RAT_2
#endif
#if (flash_EBIU_AMBCTL_RAT == 1)
#define flash_EBIU_AMBCTL0_RAT B0RAT_1
#endif
#define flash_EBIU_AMBCTL0 \
(flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
arch/blackfin/mach-bf538/include/mach/mem_map.h 0 → 100644
View file @ dc26aec2
/*
* File: include/asm-blackfin/mach-bf538/mem_map.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _MEM_MAP_538_H_
#define _MEM_MAP_538_H_
#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
/* Async Memory Banks */
#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
/* Boot ROM Memory */
#define BOOT_ROM_START 0xEF000000
#define BOOT_ROM_LENGTH 0x400
/* Level 1 Memory */
#ifdef CONFIG_BFIN_ICACHE
#define BFIN_ICACHESIZE (16*1024)
#else
#define BFIN_ICACHESIZE (0*1024)
#endif
/* Memory Map for ADSP-BF538/9 processors */
#define L1_CODE_START 0xFFA00000
#define L1_DATA_A_START 0xFF800000
#define L1_DATA_B_START 0xFF900000
#ifdef CONFIG_BFIN_ICACHE
#define L1_CODE_LENGTH (0x14000 - 0x4000)
#else
#define L1_CODE_LENGTH 0x14000
#endif
#ifdef CONFIG_BFIN_DCACHE
#ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH 0x8000
#define BFIN_DCACHESIZE (16*1024)
#define BFIN_DSUPBANKS 1
#else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
#define BFIN_DCACHESIZE (32*1024)
#define BFIN_DSUPBANKS 2
#endif
#else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x8000
#define L1_DATA_B_LENGTH 0x8000
#define BFIN_DCACHESIZE (0*1024)
#define BFIN_DSUPBANKS 0
#endif /*CONFIG_BFIN_DCACHE*/
/* Level 2 Memory - none */
#define L2_START 0
#define L2_LENGTH 0
/* Scratch Pad Memory */
#define L1_SCRATCH_START 0xFFB00000
#define L1_SCRATCH_LENGTH 0x1000
#endif /* _MEM_MAP_538_H_ */
arch/blackfin/mach-bf538/include/mach/portmux.h 0 → 100644
View file @ dc26aec2
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define P_TMR2 (P_DONTCARE)
#define P_TMR1 (P_DONTCARE)
#define P_TMR0 (P_DONTCARE)
#define P_TMRCLK (P_DONTCARE)
#define P_PPI0_CLK (P_DONTCARE)
#define P_PPI0_FS1 (P_DONTCARE)
#define P_PPI0_FS2 (P_DONTCARE)
#define P_TWI0_SCL (P_DONTCARE)
#define P_TWI0_SDA (P_DONTCARE)
#define P_TWI1_SCL (P_DONTCARE)
#define P_TWI1_SDA (P_DONTCARE)
#define P_SPORT1_TSCLK (P_DONTCARE)
#define P_SPORT1_RSCLK (P_DONTCARE)
#define P_SPORT0_TSCLK (P_DONTCARE)
#define P_SPORT0_RSCLK (P_DONTCARE)
#define P_SPORT1_DRSEC (P_DONTCARE)
#define P_SPORT1_RFS (P_DONTCARE)
#define P_SPORT1_DTPRI (P_DONTCARE)
#define P_SPORT1_DTSEC (P_DONTCARE)
#define P_SPORT1_TFS (P_DONTCARE)
#define P_SPORT1_DRPRI (P_DONTCARE)
#define P_SPORT0_DRSEC (P_DONTCARE)
#define P_SPORT0_RFS (P_DONTCARE)
#define P_SPORT0_DTPRI (P_DONTCARE)
#define P_SPORT0_DTSEC (P_DONTCARE)
#define P_SPORT0_TFS (P_DONTCARE)
#define P_SPORT0_DRPRI (P_DONTCARE)
#define P_UART0_RX (P_DONTCARE)
#define P_UART0_TX (P_DONTCARE)
#define P_SPI0_MOSI (P_DONTCARE)
#define P_SPI0_MISO (P_DONTCARE)
#define P_SPI0_SCK (P_DONTCARE)
#define P_PPI0_D0 (P_DONTCARE)
#define P_PPI0_D1 (P_DONTCARE)
#define P_PPI0_D2 (P_DONTCARE)
#define P_PPI0_D3 (P_DONTCARE)
#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0))
#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1))
#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0))
#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1))
#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2))
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3))
#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4))
#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5))
#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6))
#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7))
#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8))
#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9))
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10))
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11))
#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12))
#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13))
#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0))
#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1))
#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2))
#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3))
#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4))
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5))
#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6))
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7))
#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8))
#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9))
#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10))
#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11))
#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12))
#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13))
#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14))
#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15))
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
#endif /* _MACH_PORTMUX_H_ */
arch/blackfin/mach-bf538/ints-priority.c 0 → 100644
View file @ dc26aec2
/*
* File: arch/blackfin/mach-bf538/ints-priority.c
* Based on: arch/blackfin/mach-bf533/ints-priority.c
* Author: Michael Hennerich
*
* Created:
* Description: Set up the interrupt priorities
*
* Modified:
* Copyright 2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/blackfin.h>
void __init program_IAR(void)
{
/* Program the IAR0 Register with the configured priority */
bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) |
((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
bfin_write_SIC_IAR2(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) |
((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) |
((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) |
((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) |
((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) |
((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS));
bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) |
((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) |
((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) |
((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) |
((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS));
SSYNC();
}
arch/blackfin/mach-common/dpmc_modes.S
View file @ dc26aec2
...@@ -247,7 +247,8 @@ ENTRY(_unset_dram_srfs) ...@@ -247,7 +247,8 @@ ENTRY(_unset_dram_srfs)
ENDPROC(_unset_dram_srfs) ENDPROC(_unset_dram_srfs)
ENTRY(_set_sic_iwr) ENTRY(_set_sic_iwr)
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
defined(CONFIG_BF538) || defined(CONFIG_BF539)
P0.H = hi(SIC_IWR0); P0.H = hi(SIC_IWR0);
P0.L = lo(SIC_IWR0); P0.L = lo(SIC_IWR0);
P1.H = hi(SIC_IWR1); P1.H = hi(SIC_IWR1);
......
arch/blackfin/mach-common/ints-priority.c
View file @ dc26aec2
...@@ -103,12 +103,13 @@ static void __init search_IAR(void) ...@@ -103,12 +103,13 @@ static void __init search_IAR(void)
for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
int iar_shift = (irqn & 7) * 4; int iar_shift = (irqn & 7) * 4;
if (ivg == (0xf & if (ivg == (0xf &
#ifndef CONFIG_BF52x #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) || defined(CONFIG_BF539)
bfin_read32((unsigned long *)SIC_IAR0 + bfin_read32((unsigned long *)SIC_IAR0 +
(irqn >> 3)) >> iar_shift)) { ((irqn % 32) >> 3) + ((irqn / 32) *
((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
#else #else
bfin_read32((unsigned long *)SIC_IAR0 + bfin_read32((unsigned long *)SIC_IAR0 +
((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) { (irqn >> 3)) >> iar_shift)) {
#endif #endif
ivg_table[irq_pos].irqno = IVG7 + irqn; ivg_table[irq_pos].irqno = IVG7 + irqn;
ivg_table[irq_pos].isrflag = 1 << (irqn % 32); ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
...@@ -537,6 +538,10 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq, ...@@ -537,6 +538,10 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
irq = IRQ_PH0; irq = IRQ_PH0;
break; break;
# endif # endif
#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
case IRQ_PORTF_INTA:
irq = IRQ_PF0;
break;
#elif defined(CONFIG_BF52x) #elif defined(CONFIG_BF52x)
case IRQ_PORTF_INTA: case IRQ_PORTF_INTA:
irq = IRQ_PF0; irq = IRQ_PF0;
...@@ -984,7 +989,7 @@ int __init init_arch_irq(void) ...@@ -984,7 +989,7 @@ int __init init_arch_irq(void)
int irq; int irq;
unsigned long ilat = 0; unsigned long ilat = 0;
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */ /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY)
bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
# ifdef CONFIG_BF54x # ifdef CONFIG_BF54x
...@@ -1037,7 +1042,10 @@ int __init init_arch_irq(void) ...@@ -1037,7 +1042,10 @@ int __init init_arch_irq(void)
case IRQ_PROG0_INTA: case IRQ_PROG0_INTA:
case IRQ_PROG1_INTA: case IRQ_PROG1_INTA:
case IRQ_PROG2_INTA: case IRQ_PROG2_INTA:
#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
case IRQ_PORTF_INTA:
#endif #endif
set_irq_chained_handler(irq, set_irq_chained_handler(irq,
bfin_demux_gpio_irq); bfin_demux_gpio_irq);
break; break;
...@@ -1085,7 +1093,7 @@ int __init init_arch_irq(void) ...@@ -1085,7 +1093,7 @@ int __init init_arch_irq(void)
IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY)
bfin_write_SIC_IWR0(IWR_DISABLE_ALL); bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
#if defined(CONFIG_BF52x) #if defined(CONFIG_BF52x)
/* BF52x system reset does not properly reset SIC_IWR1 which /* BF52x system reset does not properly reset SIC_IWR1 which
...@@ -1117,7 +1125,7 @@ void do_irq(int vec, struct pt_regs *fp) ...@@ -1117,7 +1125,7 @@ void do_irq(int vec, struct pt_regs *fp)
} else { } else {
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY)
unsigned long sic_status[3]; unsigned long sic_status[3];
sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
......
arch/blackfin/mach-common/pm.c
View file @ dc26aec2
...@@ -82,7 +82,8 @@ void bfin_pm_suspend_standby_enter(void) ...@@ -82,7 +82,8 @@ void bfin_pm_suspend_standby_enter(void)
bfin_pm_standby_restore(); bfin_pm_standby_restore();
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
defined(CONFIG_BF538) || defined(CONFIG_BF539)
bfin_write_SIC_IWR0(IWR_DISABLE_ALL); bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
#if defined(CONFIG_BF52x) #if defined(CONFIG_BF52x)
/* BF52x system reset does not properly reset SIC_IWR1 which /* BF52x system reset does not properly reset SIC_IWR1 which
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7