Commit dc30c35b authored by Andrew Lunn's avatar Andrew Lunn Committed by David S. Miller

net: dsa: mv88e6xxx: Implement interrupt support.

The switch can have up to two interrupt controllers. One of these
contains the interrupts from the integrated PHYs, so is useful to
export. The Marvell PHY driver can then be used in interrupt mode,
rather than polling, speeding up PHY handling and reducing load on the
MDIO bus.
Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 9c7cbcf5
...@@ -20,16 +20,35 @@ Required properties: ...@@ -20,16 +20,35 @@ Required properties:
Optional properties: Optional properties:
- reset-gpios : Should be a gpio specifier for a reset line - reset-gpios : Should be a gpio specifier for a reset line
- interrupt-parent : Parent interrupt controller
- interrupts : Interrupt from the switch
- interrupt-controller : Indicates the switch is itself an interrupt
controller. This is used for the PHY interrupts.
#interrupt-cells = <2> : Controller uses two cells, number and flag
- mdio : container of PHY and devices on the switches MDIO
bus
Example: Example:
mdio { mdio {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupt-parent = <&gpio0>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
switch0: switch@0 { switch0: switch@0 {
compatible = "marvell,mv88e6085"; compatible = "marvell,mv88e6085";
reg = <0>; reg = <0>;
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
}; };
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch1phy0: switch1phy0@0 {
reg = <0>;
interrupt-parent = <&switch0>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
};
}; };
This diff is collapsed.
/* /*
* Marvell 88E6xxx Switch Global 2 Registers support (device address 0x1C) * Marvell 88E6xxx Switch Global 2 Registers support (device address
* 0x1C)
* *
* Copyright (c) 2008 Marvell Semiconductor * Copyright (c) 2008 Marvell Semiconductor
* *
...@@ -11,6 +12,7 @@ ...@@ -11,6 +12,7 @@
* (at your option) any later version. * (at your option) any later version.
*/ */
#include <linux/irqdomain.h>
#include "mv88e6xxx.h" #include "mv88e6xxx.h"
#include "global2.h" #include "global2.h"
...@@ -417,6 +419,141 @@ int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr, int reg, ...@@ -417,6 +419,141 @@ int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr, int reg,
return mv88e6xxx_g2_smi_phy_cmd(chip, cmd); return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
} }
static void mv88e6xxx_g2_irq_mask(struct irq_data *d)
{
struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
unsigned int n = d->hwirq;
chip->g2_irq.masked |= (1 << n);
}
static void mv88e6xxx_g2_irq_unmask(struct irq_data *d)
{
struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
unsigned int n = d->hwirq;
chip->g2_irq.masked &= ~(1 << n);
}
static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id)
{
struct mv88e6xxx_chip *chip = dev_id;
unsigned int nhandled = 0;
unsigned int sub_irq;
unsigned int n;
int err;
u16 reg;
mutex_lock(&chip->reg_lock);
err = mv88e6xxx_g2_read(chip, GLOBAL2_INT_SOURCE, &reg);
mutex_unlock(&chip->reg_lock);
if (err)
goto out;
for (n = 0; n < 16; ++n) {
if (reg & (1 << n)) {
sub_irq = irq_find_mapping(chip->g2_irq.domain, n);
handle_nested_irq(sub_irq);
++nhandled;
}
}
out:
return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
}
static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d)
{
struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
mutex_lock(&chip->reg_lock);
}
static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d)
{
struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
mv88e6xxx_g2_write(chip, GLOBAL2_INT_MASK, ~chip->g2_irq.masked);
mutex_unlock(&chip->reg_lock);
}
static struct irq_chip mv88e6xxx_g2_irq_chip = {
.name = "mv88e6xxx-g2",
.irq_mask = mv88e6xxx_g2_irq_mask,
.irq_unmask = mv88e6xxx_g2_irq_unmask,
.irq_bus_lock = mv88e6xxx_g2_irq_bus_lock,
.irq_bus_sync_unlock = mv88e6xxx_g2_irq_bus_sync_unlock,
};
static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d,
unsigned int irq,
irq_hw_number_t hwirq)
{
struct mv88e6xxx_chip *chip = d->host_data;
irq_set_chip_data(irq, d->host_data);
irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq);
irq_set_noprobe(irq);
return 0;
}
static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = {
.map = mv88e6xxx_g2_irq_domain_map,
.xlate = irq_domain_xlate_twocell,
};
void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
{
int irq, virq;
for (irq = 0; irq < 16; irq++) {
virq = irq_find_mapping(chip->g2_irq.domain, irq);
irq_dispose_mapping(virq);
}
irq_domain_remove(chip->g2_irq.domain);
}
int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
{
int device_irq;
int err, irq;
if (!chip->dev->of_node)
return -EINVAL;
chip->g2_irq.domain = irq_domain_add_simple(
chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
if (!chip->g2_irq.domain)
return -ENOMEM;
for (irq = 0; irq < 16; irq++)
irq_create_mapping(chip->g2_irq.domain, irq);
chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
chip->g2_irq.masked = ~0;
device_irq = irq_find_mapping(chip->g1_irq.domain,
GLOBAL_STATUS_IRQ_DEVICE);
if (device_irq < 0) {
err = device_irq;
goto out;
}
err = devm_request_threaded_irq(chip->dev, device_irq, NULL,
mv88e6xxx_g2_irq_thread_fn,
IRQF_ONESHOT, "mv88e6xxx-g1", chip);
if (err)
goto out;
return 0;
out:
mv88e6xxx_g2_irq_free(chip);
return err;
}
int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip) int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
{ {
u16 reg; u16 reg;
......
...@@ -33,6 +33,8 @@ int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, ...@@ -33,6 +33,8 @@ int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
struct ethtool_eeprom *eeprom, u8 *data); struct ethtool_eeprom *eeprom, u8 *data);
int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip); int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip);
int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);
void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);
#else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
...@@ -83,6 +85,15 @@ static inline int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip) ...@@ -83,6 +85,15 @@ static inline int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
{
return -EOPNOTSUPP;
}
static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
{
}
#endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
#endif /* _MV88E6XXX_GLOBAL2_H */ #endif /* _MV88E6XXX_GLOBAL2_H */
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#define __MV88E6XXX_H #define __MV88E6XXX_H
#include <linux/if_vlan.h> #include <linux/if_vlan.h>
#include <linux/irq.h>
#include <linux/gpio/consumer.h> #include <linux/gpio/consumer.h>
#ifndef UINT64_MAX #ifndef UINT64_MAX
...@@ -167,6 +168,15 @@ ...@@ -167,6 +168,15 @@
#define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14) #define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14)
#define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14) #define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14)
#define GLOBAL_STATUS_PPU_POLLING (0x3 << 14) #define GLOBAL_STATUS_PPU_POLLING (0x3 << 14)
#define GLOBAL_STATUS_IRQ_AVB 8
#define GLOBAL_STATUS_IRQ_DEVICE 7
#define GLOBAL_STATUS_IRQ_STATS 6
#define GLOBAL_STATUS_IRQ_VTU_PROBLEM 5
#define GLOBAL_STATUS_IRQ_VTU_DONE 4
#define GLOBAL_STATUS_IRQ_ATU_PROBLEM 3
#define GLOBAL_STATUS_IRQ_ATU_DONE 2
#define GLOBAL_STATUS_IRQ_TCAM_DONE 1
#define GLOBAL_STATUS_IRQ_EEPROM_DONE 0
#define GLOBAL_MAC_01 0x01 #define GLOBAL_MAC_01 0x01
#define GLOBAL_MAC_23 0x02 #define GLOBAL_MAC_23 0x02
#define GLOBAL_MAC_45 0x03 #define GLOBAL_MAC_45 0x03
...@@ -417,6 +427,7 @@ enum mv88e6xxx_cap { ...@@ -417,6 +427,7 @@ enum mv88e6xxx_cap {
* The device contains a second set of global 16-bit registers. * The device contains a second set of global 16-bit registers.
*/ */
MV88E6XXX_CAP_GLOBAL2, MV88E6XXX_CAP_GLOBAL2,
MV88E6XXX_CAP_G2_INT, /* (0x00) Interrupt Status */
MV88E6XXX_CAP_G2_MGMT_EN_2X, /* (0x02) MGMT Enable Register 2x */ MV88E6XXX_CAP_G2_MGMT_EN_2X, /* (0x02) MGMT Enable Register 2x */
MV88E6XXX_CAP_G2_MGMT_EN_0X, /* (0x03) MGMT Enable Register 0x */ MV88E6XXX_CAP_G2_MGMT_EN_0X, /* (0x03) MGMT Enable Register 0x */
MV88E6XXX_CAP_G2_IRL_CMD, /* (0x09) Ingress Rate Command */ MV88E6XXX_CAP_G2_IRL_CMD, /* (0x09) Ingress Rate Command */
...@@ -464,6 +475,7 @@ enum mv88e6xxx_cap { ...@@ -464,6 +475,7 @@ enum mv88e6xxx_cap {
#define MV88E6XXX_FLAG_G1_VTU_FID BIT_ULL(MV88E6XXX_CAP_G1_VTU_FID) #define MV88E6XXX_FLAG_G1_VTU_FID BIT_ULL(MV88E6XXX_CAP_G1_VTU_FID)
#define MV88E6XXX_FLAG_GLOBAL2 BIT_ULL(MV88E6XXX_CAP_GLOBAL2) #define MV88E6XXX_FLAG_GLOBAL2 BIT_ULL(MV88E6XXX_CAP_GLOBAL2)
#define MV88E6XXX_FLAG_G2_INT BIT_ULL(MV88E6XXX_CAP_G2_INT)
#define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_2X) #define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_2X)
#define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_0X) #define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_0X)
#define MV88E6XXX_FLAG_G2_IRL_CMD BIT_ULL(MV88E6XXX_CAP_G2_IRL_CMD) #define MV88E6XXX_FLAG_G2_IRL_CMD BIT_ULL(MV88E6XXX_CAP_G2_IRL_CMD)
...@@ -524,6 +536,7 @@ enum mv88e6xxx_cap { ...@@ -524,6 +536,7 @@ enum mv88e6xxx_cap {
(MV88E6XXX_FLAG_G1_ATU_FID | \ (MV88E6XXX_FLAG_G1_ATU_FID | \
MV88E6XXX_FLAG_G1_VTU_FID | \ MV88E6XXX_FLAG_G1_VTU_FID | \
MV88E6XXX_FLAG_GLOBAL2 | \ MV88E6XXX_FLAG_GLOBAL2 | \
MV88E6XXX_FLAG_G2_INT | \
MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
MV88E6XXX_FLAG_G2_POT | \ MV88E6XXX_FLAG_G2_POT | \
...@@ -536,6 +549,7 @@ enum mv88e6xxx_cap { ...@@ -536,6 +549,7 @@ enum mv88e6xxx_cap {
#define MV88E6XXX_FLAGS_FAMILY_6185 \ #define MV88E6XXX_FLAGS_FAMILY_6185 \
(MV88E6XXX_FLAG_GLOBAL2 | \ (MV88E6XXX_FLAG_GLOBAL2 | \
MV88E6XXX_FLAG_G2_INT | \
MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
MV88E6XXX_FLAGS_MULTI_CHIP | \ MV88E6XXX_FLAGS_MULTI_CHIP | \
MV88E6XXX_FLAG_PPU | \ MV88E6XXX_FLAG_PPU | \
...@@ -561,6 +575,7 @@ enum mv88e6xxx_cap { ...@@ -561,6 +575,7 @@ enum mv88e6xxx_cap {
MV88E6XXX_FLAG_G1_ATU_FID | \ MV88E6XXX_FLAG_G1_ATU_FID | \
MV88E6XXX_FLAG_G1_VTU_FID | \ MV88E6XXX_FLAG_G1_VTU_FID | \
MV88E6XXX_FLAG_GLOBAL2 | \ MV88E6XXX_FLAG_GLOBAL2 | \
MV88E6XXX_FLAG_G2_INT | \
MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
MV88E6XXX_FLAG_G2_POT | \ MV88E6XXX_FLAG_G2_POT | \
...@@ -578,6 +593,7 @@ enum mv88e6xxx_cap { ...@@ -578,6 +593,7 @@ enum mv88e6xxx_cap {
MV88E6XXX_FLAG_G1_ATU_FID | \ MV88E6XXX_FLAG_G1_ATU_FID | \
MV88E6XXX_FLAG_G1_VTU_FID | \ MV88E6XXX_FLAG_G1_VTU_FID | \
MV88E6XXX_FLAG_GLOBAL2 | \ MV88E6XXX_FLAG_GLOBAL2 | \
MV88E6XXX_FLAG_G2_INT | \
MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
MV88E6XXX_FLAG_G2_POT | \ MV88E6XXX_FLAG_G2_POT | \
...@@ -602,6 +618,7 @@ struct mv88e6xxx_info { ...@@ -602,6 +618,7 @@ struct mv88e6xxx_info {
unsigned int port_base_addr; unsigned int port_base_addr;
unsigned int global1_addr; unsigned int global1_addr;
unsigned int age_time_coeff; unsigned int age_time_coeff;
unsigned int g1_irqs;
unsigned long long flags; unsigned long long flags;
const struct mv88e6xxx_ops *ops; const struct mv88e6xxx_ops *ops;
}; };
...@@ -628,6 +645,13 @@ struct mv88e6xxx_priv_port { ...@@ -628,6 +645,13 @@ struct mv88e6xxx_priv_port {
struct net_device *bridge_dev; struct net_device *bridge_dev;
}; };
struct mv88e6xxx_irq {
u16 masked;
struct irq_chip chip;
struct irq_domain *domain;
unsigned int nirqs;
};
struct mv88e6xxx_chip { struct mv88e6xxx_chip {
const struct mv88e6xxx_info *info; const struct mv88e6xxx_info *info;
...@@ -677,6 +701,13 @@ struct mv88e6xxx_chip { ...@@ -677,6 +701,13 @@ struct mv88e6xxx_chip {
/* And the MDIO bus itself */ /* And the MDIO bus itself */
struct mii_bus *mdio_bus; struct mii_bus *mdio_bus;
/* There can be two interrupt controllers, which are chained
* off a GPIO as interrupt source
*/
struct mv88e6xxx_irq g1_irq;
struct mv88e6xxx_irq g2_irq;
int irq;
}; };
struct mv88e6xxx_bus_ops { struct mv88e6xxx_bus_ops {
......
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