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Commit ddc5d5ef authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://kernel.bkbits.net/jgarzik/net-drivers-2.5 

into home.osdl.org:/home/torvalds/v2.5/linux
parents 19665252 e3dec99d
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Showing with 198 additions and 109 deletions
drivers/net/8139too.c
View file @ ddc5d5ef
......@@ -2070,7 +2070,7 @@ static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
RTL_W16 (IntrStatus, ackstat);
DPRINTK ("%s: interrupt status=%#4.4x ackstat=%#4.4x new intstat=%#4.4x.\n",
dev->name, ackstat, status, RTL_R16 (IntrStatus));
dev->name, status, ackstat, RTL_R16 (IntrStatus));
if (netif_running (dev) && (status & RxAckBits))
rtl8139_rx_interrupt (dev, tp, ioaddr);
......
drivers/net/e1000/e1000.h
View file @ ddc5d5ef
......@@ -224,6 +224,5 @@ struct e1000_adapter {
uint32_t pci_state[16];
char ifname[IFNAMSIZ];
};
#endif /* _E1000_H_ */
drivers/net/e1000/e1000_ethtool.c
View file @ ddc5d5ef
......@@ -1112,8 +1112,9 @@ e1000_ethtool_test(struct e1000_adapter *adapter,
if(if_running)
e1000_down(adapter);
else
e1000_reset(adapter);
if(e1000_reg_test(adapter, &data[0]))
eth_test->flags |= ETH_TEST_FL_FAILED;
......
drivers/net/e1000/e1000_hw.c
View file @ ddc5d5ef
......@@ -135,6 +135,41 @@ e1000_phy_init_script(struct e1000_hw *hw)
e1000_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x0000);
e1000_write_phy_reg(hw,0x0000,0x3300);
if(hw->mac_type == e1000_82547) {
uint16_t fused, fine, coarse;
/* Move to analog registers page */
e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
IGP01E1000_ANALOG_REGS_PAGE);
e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
} else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
(fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
(coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
}
/* Return to first page of registers */
e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
IGP01E1000_IEEE_REGS_PAGE);
}
}
}
......@@ -259,10 +294,20 @@ e1000_reset_hw(struct e1000_hw *hw)
msec_delay(5);
}
if(hw->mac_type > e1000_82543)
switch(hw->mac_type) {
case e1000_82544:
case e1000_82540:
case e1000_82545:
case e1000_82546:
case e1000_82541:
/* These controllers can't ack the 64-bit write when issuing the
* reset, so use IO-mapping as a workaround to issue the reset */
E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
else
break;
default:
E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
break;
}
/* Force a reload from the EEPROM if necessary */
if(hw->mac_type < e1000_82540) {
......@@ -687,7 +732,8 @@ e1000_setup_fiber_link(struct e1000_hw *hw)
static int32_t
e1000_setup_copper_link(struct e1000_hw *hw)
{
uint32_t ctrl, led_ctrl;
uint32_t ctrl;
uint32_t led_ctrl;
int32_t ret_val;
uint16_t i;
uint16_t phy_data;
......@@ -2249,7 +2295,8 @@ e1000_write_phy_reg(struct e1000_hw *hw,
void
e1000_phy_hw_reset(struct e1000_hw *hw)
{
uint32_t ctrl, ctrl_ext, led_ctrl;
uint32_t ctrl, ctrl_ext;
uint32_t led_ctrl;
DEBUGFUNC("e1000_phy_hw_reset");
......
drivers/net/e1000/e1000_hw.h
View file @ ddc5d5ef
......@@ -1668,6 +1668,7 @@ struct e1000_hw {
#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
#define IGP01E1000_IEEE_REGS_PAGE 0x0000
/* IGP01E1000 Specific Registers */
#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
......@@ -1690,6 +1691,7 @@ struct e1000_hw {
* speed = 1000 Mbps. */
#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
......@@ -1980,6 +1982,22 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
* on Link-Up */
#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
/* IGP01E1000 Analog Register */
#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x0011
#define IGP01E1000_ANALOG_FUSE_STATUS 0x0010
#define IGP01E1000_ANALOG_FUSE_CONTROL 0x001C
#define IGP01E1000_ANALOG_FUSE_BYPASS 0x001E
#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
/* Bit definitions for valid PHY IDs. */
#define M88E1000_E_PHY_ID 0x01410C50
......
drivers/net/e1000/e1000_main.c
View file @ ddc5d5ef
This diff is collapsed.
drivers/net/via-rhine.c
View file @ ddc5d5ef
......@@ -2,6 +2,8 @@
/*
Written 1998-2001 by Donald Becker.
Current Maintainer: Roger Luethi <rl@hellgate.ch>
This software may be used and distributed according to the terms of
the GNU General Public License (GPL), incorporated herein by reference.
Drivers based on or derived from this code fall under the GPL and must
......@@ -10,7 +12,8 @@
system is licensed under the GPL.
This driver is designed for the VIA VT86C100A Rhine-I.
It also works with the 6102 Rhine-II, and 6105/6105M Rhine-III.
It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
and management NIC 6105M).
The author may be reached as becker@scyld.com, or C/O
Scyld Computing Corporation
......@@ -115,11 +118,15 @@
- Force flushing for PCI posted writes
- More reset code changes
LK1.1.18 (Roger Luethi)
- No filtering multicast in promisc mode (Edward Peng)
- Fix for Rhine-I Tx timeouts
*/
#define DRV_NAME "via-rhine"
#define DRV_VERSION "1.1.17"
#define DRV_RELDATE "March-1-2003"
#define DRV_VERSION "1.1.18-2.5"
#define DRV_RELDATE "July-4-2003"
/* A few user-configurable values.
......@@ -395,7 +402,7 @@ static struct pci_device_id via_rhine_pci_tbl[] __devinitdata =
{
{0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VT86C100A},
{0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VT6102},
{0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VT6105},
{0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VT6105}, /* 6105{,L,LOM} */
{0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VT6105M},
{0,} /* terminate list */
};
......@@ -441,7 +448,7 @@ enum intr_status_bits {
IntrRxWakeUp=0x8000,
IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
IntrTxErrSummary=0x082210,
IntrTxErrSummary=0x082218,
};
/* The Rx and Tx buffer descriptors. */
......@@ -1655,7 +1662,14 @@ static void via_rhine_error(struct net_device *dev, int intr_status)
printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
dev->name);
}
if (intr_status & ( IntrTxAborted | IntrTxUnderrun | IntrTxDescRace ))
if ((intr_status & IntrTxError) && ~( IntrTxAborted | IntrTxUnderrun |
IntrTxDescRace )) {
if (debug > 2)
printk(KERN_INFO "%s: Unspecified error.\n",
dev->name);
}
if (intr_status & ( IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
IntrTxError ))
via_rhine_restart_tx(dev);
if (intr_status & ~( IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
......
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