Commit e0ab9578 authored by Chunming Zhou's avatar Chunming Zhou Committed by Alex Deucher

drm/amdgpu/soc15: add Raven golden setting

Add the common golden settings for Raven.
Signed-off-by: default avatarChunming Zhou <David1.Zhou@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1023b797
...@@ -206,6 +206,10 @@ static const u32 vega10_golden_init[] = ...@@ -206,6 +206,10 @@ static const u32 vega10_golden_init[] =
{ {
}; };
static const u32 raven_golden_init[] =
{
};
static void soc15_init_golden_registers(struct amdgpu_device *adev) static void soc15_init_golden_registers(struct amdgpu_device *adev)
{ {
/* Some of the registers might be dependent on GRBM_GFX_INDEX */ /* Some of the registers might be dependent on GRBM_GFX_INDEX */
...@@ -217,6 +221,11 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev) ...@@ -217,6 +221,11 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
vega10_golden_init, vega10_golden_init,
(const u32)ARRAY_SIZE(vega10_golden_init)); (const u32)ARRAY_SIZE(vega10_golden_init));
break; break;
case CHIP_RAVEN:
amdgpu_program_register_sequence(adev,
raven_golden_init,
(const u32)ARRAY_SIZE(raven_golden_init));
break;
default: default:
break; break;
} }
......
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