Commit e110cc69 authored by Peter Huewe's avatar Peter Huewe Committed by Jarkko Sakkinen

tpm_tis_spi: Check correct byte for wait state indicator

Wait states are signaled in the last byte received from the TPM in
response to the header, not the first byte. Check rx_buf[3] instead of
rx_buf[0].

Cc: <stable@vger.kernel.org>
Fixes: 0edbfea5 ("tpm/tpm_tis_spi: Add support for spi phy")
Signed-off-by: default avatarAlexander Steffen <Alexander.Steffen@infineon.com>
Signed-off-by: default avatarPeter Huewe <peter.huewe@infineon.com>
Reviewed-by: default avatarJarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Tested-by: default avatarBenoit Houyere <benoit.houyere@st.com>
Signed-off-by: default avatarJarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
parent 975094dd
...@@ -85,25 +85,25 @@ static int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len, ...@@ -85,25 +85,25 @@ static int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len,
if (ret < 0) if (ret < 0)
goto exit; goto exit;
phy->tx_buf[0] = 0; if ((phy->rx_buf[3] & 0x01) == 0) {
// handle SPI wait states
/* According to TCG PTP specification, if there is no TPM present at phy->tx_buf[0] = 0;
* all, then the design has a weak pull-up on MISO. If a TPM is not
* present, a pull-up on MISO means that the SB controller sees a 1, for (i = 0; i < TPM_RETRY; i++) {
* and will latch in 0xFF on the read. spi_xfer.len = 1;
*/ spi_message_init(&m);
for (i = 0; (phy->rx_buf[0] & 0x01) == 0 && i < TPM_RETRY; i++) { spi_message_add_tail(&spi_xfer, &m);
spi_xfer.len = 1; ret = spi_sync_locked(phy->spi_device, &m);
spi_message_init(&m); if (ret < 0)
spi_message_add_tail(&spi_xfer, &m); goto exit;
ret = spi_sync_locked(phy->spi_device, &m); if (phy->rx_buf[0] & 0x01)
if (ret < 0) break;
}
if (i == TPM_RETRY) {
ret = -ETIMEDOUT;
goto exit; goto exit;
} }
if (i == TPM_RETRY) {
ret = -ETIMEDOUT;
goto exit;
} }
spi_xfer.cs_change = 0; spi_xfer.cs_change = 0;
......
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