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nexedi
linux
Commits
e3828811
Commit
e3828811
authored
Mar 08, 2007
by
Chris Leech
Committed by
Dan Williams
Jul 11, 2007
Browse files
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Plain Diff
ioatdma: Remove the wrappers around read(bwl)/write(bwl) in ioatdma
Signed-off-by:
Chris Leech
<
christopher.leech@intel.com
>
parent
ff487fb7
Changes
2
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
28 additions
and
150 deletions
+28
-150
drivers/dma/ioatdma.c
drivers/dma/ioatdma.c
+28
-32
drivers/dma/ioatdma_io.h
drivers/dma/ioatdma_io.h
+0
-118
No files found.
drivers/dma/ioatdma.c
View file @
e3828811
...
@@ -32,7 +32,6 @@
...
@@ -32,7 +32,6 @@
#include <linux/delay.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dma-mapping.h>
#include "ioatdma.h"
#include "ioatdma.h"
#include "ioatdma_io.h"
#include "ioatdma_registers.h"
#include "ioatdma_registers.h"
#include "ioatdma_hw.h"
#include "ioatdma_hw.h"
...
@@ -51,8 +50,8 @@ static int enumerate_dma_channels(struct ioat_device *device)
...
@@ -51,8 +50,8 @@ static int enumerate_dma_channels(struct ioat_device *device)
int
i
;
int
i
;
struct
ioat_dma_chan
*
ioat_chan
;
struct
ioat_dma_chan
*
ioat_chan
;
device
->
common
.
chancnt
=
ioatdma_read8
(
device
,
IOAT_CHANCNT_OFFSET
);
device
->
common
.
chancnt
=
readb
(
device
->
reg_base
+
IOAT_CHANCNT_OFFSET
);
xfercap_scale
=
ioatdma_read8
(
device
,
IOAT_XFERCAP_OFFSET
);
xfercap_scale
=
readb
(
device
->
reg_base
+
IOAT_XFERCAP_OFFSET
);
xfercap
=
(
xfercap_scale
==
0
?
-
1
:
(
1UL
<<
xfercap_scale
));
xfercap
=
(
xfercap_scale
==
0
?
-
1
:
(
1UL
<<
xfercap_scale
));
for
(
i
=
0
;
i
<
device
->
common
.
chancnt
;
i
++
)
{
for
(
i
=
0
;
i
<
device
->
common
.
chancnt
;
i
++
)
{
...
@@ -123,7 +122,7 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
...
@@ -123,7 +122,7 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
* In-use bit automatically set by reading chanctrl
* In-use bit automatically set by reading chanctrl
* If 0, we got it, if 1, someone else did
* If 0, we got it, if 1, someone else did
*/
*/
chanctrl
=
ioatdma_chan_read16
(
ioat_chan
,
IOAT_CHANCTRL_OFFSET
);
chanctrl
=
readw
(
ioat_chan
->
reg_base
+
IOAT_CHANCTRL_OFFSET
);
if
(
chanctrl
&
IOAT_CHANCTRL_CHANNEL_IN_USE
)
if
(
chanctrl
&
IOAT_CHANCTRL_CHANNEL_IN_USE
)
return
-
EBUSY
;
return
-
EBUSY
;
...
@@ -132,12 +131,12 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
...
@@ -132,12 +131,12 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
IOAT_CHANCTRL_ERR_INT_EN
|
IOAT_CHANCTRL_ERR_INT_EN
|
IOAT_CHANCTRL_ANY_ERR_ABORT_EN
|
IOAT_CHANCTRL_ANY_ERR_ABORT_EN
|
IOAT_CHANCTRL_ERR_COMPLETION_EN
;
IOAT_CHANCTRL_ERR_COMPLETION_EN
;
ioatdma_chan_write16
(
ioat_chan
,
IOAT_CHANCTRL_OFFSET
,
chanctrl
);
writew
(
chanctrl
,
ioat_chan
->
reg_base
+
IOAT_CHANCTRL_OFFSET
);
chanerr
=
ioatdma_chan_read32
(
ioat_chan
,
IOAT_CHANERR_OFFSET
);
chanerr
=
readl
(
ioat_chan
->
reg_base
+
IOAT_CHANERR_OFFSET
);
if
(
chanerr
)
{
if
(
chanerr
)
{
printk
(
"IOAT: CHANERR = %x, clearing
\n
"
,
chanerr
);
printk
(
"IOAT: CHANERR = %x, clearing
\n
"
,
chanerr
);
ioatdma_chan_write32
(
ioat_chan
,
IOAT_CHANERR_OFFSET
,
chanerr
);
writel
(
chanerr
,
ioat_chan
->
reg_base
+
IOAT_CHANERR_OFFSET
);
}
}
/* Allocate descriptors */
/* Allocate descriptors */
...
@@ -161,10 +160,10 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
...
@@ -161,10 +160,10 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
&
ioat_chan
->
completion_addr
);
&
ioat_chan
->
completion_addr
);
memset
(
ioat_chan
->
completion_virt
,
0
,
memset
(
ioat_chan
->
completion_virt
,
0
,
sizeof
(
*
ioat_chan
->
completion_virt
));
sizeof
(
*
ioat_chan
->
completion_virt
));
ioatdma_chan_write32
(
ioat_chan
,
IOAT_CHANCMP_OFFSET_LOW
,
writel
(((
u64
)
ioat_chan
->
completion_addr
)
&
0x00000000FFFFFFFF
,
((
u64
)
ioat_chan
->
completion_addr
)
&
0x00000000FFFFFFFF
);
ioat_chan
->
reg_base
+
IOAT_CHANCMP_OFFSET_LOW
);
ioatdma_chan_write32
(
ioat_chan
,
IOAT_CHANCMP_OFFSET_HIGH
,
writel
(((
u64
)
ioat_chan
->
completion_addr
)
>>
32
,
((
u64
)
ioat_chan
->
completion_addr
)
>>
32
);
ioat_chan
->
reg_base
+
IOAT_CHANCMP_OFFSET_HIGH
);
ioat_start_null_desc
(
ioat_chan
);
ioat_start_null_desc
(
ioat_chan
);
return
i
;
return
i
;
...
@@ -182,7 +181,7 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan)
...
@@ -182,7 +181,7 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan)
ioat_dma_memcpy_cleanup
(
ioat_chan
);
ioat_dma_memcpy_cleanup
(
ioat_chan
);
ioatdma_chan_write8
(
ioat_chan
,
IOAT_CHANCMD_OFFSET
,
IOAT_CHANCMD_RE
SET
);
writeb
(
IOAT_CHANCMD_RESET
,
ioat_chan
->
reg_base
+
IOAT_CHANCMD_OFF
SET
);
spin_lock_bh
(
&
ioat_chan
->
desc_lock
);
spin_lock_bh
(
&
ioat_chan
->
desc_lock
);
list_for_each_entry_safe
(
desc
,
_desc
,
&
ioat_chan
->
used_desc
,
node
)
{
list_for_each_entry_safe
(
desc
,
_desc
,
&
ioat_chan
->
used_desc
,
node
)
{
...
@@ -210,9 +209,9 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan)
...
@@ -210,9 +209,9 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan)
ioat_chan
->
last_completion
=
ioat_chan
->
completion_addr
=
0
;
ioat_chan
->
last_completion
=
ioat_chan
->
completion_addr
=
0
;
/* Tell hw the chan is free */
/* Tell hw the chan is free */
chanctrl
=
ioatdma_chan_read16
(
ioat_chan
,
IOAT_CHANCTRL_OFFSET
);
chanctrl
=
readw
(
ioat_chan
->
reg_base
+
IOAT_CHANCTRL_OFFSET
);
chanctrl
&=
~
IOAT_CHANCTRL_CHANNEL_IN_USE
;
chanctrl
&=
~
IOAT_CHANCTRL_CHANNEL_IN_USE
;
ioatdma_chan_write16
(
ioat_chan
,
IOAT_CHANCTRL_OFFSET
,
chanctrl
);
writew
(
chanctrl
,
ioat_chan
->
reg_base
+
IOAT_CHANCTRL_OFFSET
);
}
}
/**
/**
...
@@ -318,9 +317,8 @@ static dma_cookie_t do_ioat_dma_memcpy(struct ioat_dma_chan *ioat_chan,
...
@@ -318,9 +317,8 @@ static dma_cookie_t do_ioat_dma_memcpy(struct ioat_dma_chan *ioat_chan,
spin_unlock_bh
(
&
ioat_chan
->
desc_lock
);
spin_unlock_bh
(
&
ioat_chan
->
desc_lock
);
if
(
append
)
if
(
append
)
ioatdma_chan_write8
(
ioat_chan
,
writeb
(
IOAT_CHANCMD_APPEND
,
IOAT_CHANCMD_OFFSET
,
ioat_chan
->
reg_base
+
IOAT_CHANCMD_OFFSET
);
IOAT_CHANCMD_APPEND
);
return
cookie
;
return
cookie
;
}
}
...
@@ -417,9 +415,8 @@ static void ioat_dma_memcpy_issue_pending(struct dma_chan *chan)
...
@@ -417,9 +415,8 @@ static void ioat_dma_memcpy_issue_pending(struct dma_chan *chan)
if
(
ioat_chan
->
pending
!=
0
)
{
if
(
ioat_chan
->
pending
!=
0
)
{
ioat_chan
->
pending
=
0
;
ioat_chan
->
pending
=
0
;
ioatdma_chan_write8
(
ioat_chan
,
writeb
(
IOAT_CHANCMD_APPEND
,
IOAT_CHANCMD_OFFSET
,
ioat_chan
->
reg_base
+
IOAT_CHANCMD_OFFSET
);
IOAT_CHANCMD_APPEND
);
}
}
}
}
...
@@ -449,7 +446,7 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *chan)
...
@@ -449,7 +446,7 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *chan)
if
((
chan
->
completion_virt
->
full
&
IOAT_CHANSTS_DMA_TRANSFER_STATUS
)
==
if
((
chan
->
completion_virt
->
full
&
IOAT_CHANSTS_DMA_TRANSFER_STATUS
)
==
IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED
)
{
IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED
)
{
printk
(
"IOAT: Channel halted, chanerr = %x
\n
"
,
printk
(
"IOAT: Channel halted, chanerr = %x
\n
"
,
ioatdma_chan_read32
(
chan
,
IOAT_CHANERR_OFFSET
));
readl
(
chan
->
reg_base
+
IOAT_CHANERR_OFFSET
));
/* TODO do something to salvage the situation */
/* TODO do something to salvage the situation */
}
}
...
@@ -569,21 +566,21 @@ static irqreturn_t ioat_do_interrupt(int irq, void *data)
...
@@ -569,21 +566,21 @@ static irqreturn_t ioat_do_interrupt(int irq, void *data)
unsigned
long
attnstatus
;
unsigned
long
attnstatus
;
u8
intrctrl
;
u8
intrctrl
;
intrctrl
=
ioatdma_read8
(
instance
,
IOAT_INTRCTRL_OFFSET
);
intrctrl
=
readb
(
instance
->
reg_base
+
IOAT_INTRCTRL_OFFSET
);
if
(
!
(
intrctrl
&
IOAT_INTRCTRL_MASTER_INT_EN
))
if
(
!
(
intrctrl
&
IOAT_INTRCTRL_MASTER_INT_EN
))
return
IRQ_NONE
;
return
IRQ_NONE
;
if
(
!
(
intrctrl
&
IOAT_INTRCTRL_INT_STATUS
))
{
if
(
!
(
intrctrl
&
IOAT_INTRCTRL_INT_STATUS
))
{
ioatdma_write8
(
instance
,
IOAT_INTRCTRL_OFFSET
,
intrctrl
);
writeb
(
intrctrl
,
instance
->
reg_base
+
IOAT_INTRCTRL_OFFSET
);
return
IRQ_NONE
;
return
IRQ_NONE
;
}
}
attnstatus
=
ioatdma_read32
(
instance
,
IOAT_ATTNSTATUS_OFFSET
);
attnstatus
=
readl
(
instance
->
reg_base
+
IOAT_ATTNSTATUS_OFFSET
);
printk
(
KERN_ERR
"ioatdma error: interrupt! status %lx
\n
"
,
attnstatus
);
printk
(
KERN_ERR
"ioatdma error: interrupt! status %lx
\n
"
,
attnstatus
);
ioatdma_write8
(
instance
,
IOAT_INTRCTRL_OFFSET
,
intrctrl
);
writeb
(
intrctrl
,
instance
->
reg_base
+
IOAT_INTRCTRL_OFFSET
);
return
IRQ_HANDLED
;
return
IRQ_HANDLED
;
}
}
...
@@ -612,14 +609,13 @@ static void ioat_start_null_desc(struct ioat_dma_chan *ioat_chan)
...
@@ -612,14 +609,13 @@ static void ioat_start_null_desc(struct ioat_dma_chan *ioat_chan)
spin_unlock_bh
(
&
ioat_chan
->
desc_lock
);
spin_unlock_bh
(
&
ioat_chan
->
desc_lock
);
#if (BITS_PER_LONG == 64)
#if (BITS_PER_LONG == 64)
ioatdma_chan_write64
(
ioat_chan
,
IOAT_CHAINADDR_OFFSET
,
desc
->
phys
);
writeq
(
desc
->
phys
,
ioat_chan
->
reg_base
+
IOAT_CHAINADDR_OFFSET
);
#else
#else
ioatdma_chan_write32
(
ioat_chan
,
writel
((
u32
)
desc
->
phys
,
IOAT_CHAINADDR_OFFSET_LOW
,
ioat_chan
->
reg_base
+
IOAT_CHAINADDR_OFFSET_LOW
);
(
u32
)
desc
->
phys
);
writel
(
0
,
ioat_chan
->
reg_base
+
IOAT_CHAINADDR_OFFSET_HIGH
);
ioatdma_chan_write32
(
ioat_chan
,
IOAT_CHAINADDR_OFFSET_HIGH
,
0
);
#endif
#endif
ioatdma_chan_write8
(
ioat_chan
,
IOAT_CHANCMD_OFFSET
,
IOAT_CHANCMD_STAR
T
);
writeb
(
IOAT_CHANCMD_START
,
ioat_chan
->
reg_base
+
IOAT_CHANCMD_OFFSE
T
);
}
}
/*
/*
...
@@ -748,7 +744,7 @@ static int __devinit ioat_probe(struct pci_dev *pdev,
...
@@ -748,7 +744,7 @@ static int __devinit ioat_probe(struct pci_dev *pdev,
device
->
reg_base
=
reg_base
;
device
->
reg_base
=
reg_base
;
ioatdma_write8
(
device
,
IOAT_INTRCTRL_OFFSET
,
IOAT_INTRCTRL_MASTER_INT_EN
);
writeb
(
IOAT_INTRCTRL_MASTER_INT_EN
,
device
->
reg_base
+
IOAT_INTRCTRL_OFFSET
);
pci_set_master
(
pdev
);
pci_set_master
(
pdev
);
INIT_LIST_HEAD
(
&
device
->
common
.
channels
);
INIT_LIST_HEAD
(
&
device
->
common
.
channels
);
...
...
drivers/dma/ioatdma_io.h
deleted
100644 → 0
View file @
ff487fb7
/*
* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* The full GNU General Public License is included in this distribution in the
* file called COPYING.
*/
#ifndef IOATDMA_IO_H
#define IOATDMA_IO_H
#include <asm/io.h>
/*
* device and per-channel MMIO register read and write functions
* this is a lot of anoying inline functions, but it's typesafe
*/
static
inline
u8
ioatdma_read8
(
struct
ioat_device
*
device
,
unsigned
int
offset
)
{
return
readb
(
device
->
reg_base
+
offset
);
}
static
inline
u16
ioatdma_read16
(
struct
ioat_device
*
device
,
unsigned
int
offset
)
{
return
readw
(
device
->
reg_base
+
offset
);
}
static
inline
u32
ioatdma_read32
(
struct
ioat_device
*
device
,
unsigned
int
offset
)
{
return
readl
(
device
->
reg_base
+
offset
);
}
static
inline
void
ioatdma_write8
(
struct
ioat_device
*
device
,
unsigned
int
offset
,
u8
value
)
{
writeb
(
value
,
device
->
reg_base
+
offset
);
}
static
inline
void
ioatdma_write16
(
struct
ioat_device
*
device
,
unsigned
int
offset
,
u16
value
)
{
writew
(
value
,
device
->
reg_base
+
offset
);
}
static
inline
void
ioatdma_write32
(
struct
ioat_device
*
device
,
unsigned
int
offset
,
u32
value
)
{
writel
(
value
,
device
->
reg_base
+
offset
);
}
static
inline
u8
ioatdma_chan_read8
(
struct
ioat_dma_chan
*
chan
,
unsigned
int
offset
)
{
return
readb
(
chan
->
reg_base
+
offset
);
}
static
inline
u16
ioatdma_chan_read16
(
struct
ioat_dma_chan
*
chan
,
unsigned
int
offset
)
{
return
readw
(
chan
->
reg_base
+
offset
);
}
static
inline
u32
ioatdma_chan_read32
(
struct
ioat_dma_chan
*
chan
,
unsigned
int
offset
)
{
return
readl
(
chan
->
reg_base
+
offset
);
}
static
inline
void
ioatdma_chan_write8
(
struct
ioat_dma_chan
*
chan
,
unsigned
int
offset
,
u8
value
)
{
writeb
(
value
,
chan
->
reg_base
+
offset
);
}
static
inline
void
ioatdma_chan_write16
(
struct
ioat_dma_chan
*
chan
,
unsigned
int
offset
,
u16
value
)
{
writew
(
value
,
chan
->
reg_base
+
offset
);
}
static
inline
void
ioatdma_chan_write32
(
struct
ioat_dma_chan
*
chan
,
unsigned
int
offset
,
u32
value
)
{
writel
(
value
,
chan
->
reg_base
+
offset
);
}
#if (BITS_PER_LONG == 64)
static
inline
u64
ioatdma_chan_read64
(
struct
ioat_dma_chan
*
chan
,
unsigned
int
offset
)
{
return
readq
(
chan
->
reg_base
+
offset
);
}
static
inline
void
ioatdma_chan_write64
(
struct
ioat_dma_chan
*
chan
,
unsigned
int
offset
,
u64
value
)
{
writeq
(
value
,
chan
->
reg_base
+
offset
);
}
#endif
#endif
/* IOATDMA_IO_H */
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