Commit e3eff6fe authored by Ingo Molnar's avatar Ingo Molnar

Merge branch 'clockevents/4.0-rc1' of...

Merge branch 'clockevents/4.0-rc1' of git://git.linaro.org/people/daniel.lezcano/linux into timers/urgent

Pull clockevents driver fixes from Daniel Lezcano:

  - Fix the Kconfig to prevent the asm9260 timer to be compiled with
    allyesconfig with sparc/sparc64 (Daniel Lezcano)

  - Reorder the mtk driver init sequence in order to prevent a potential race
    when the clock is registered before the irq handler is set (Matthias Brugger)

  - Fix a section mismatch for the pxa driver (Robert Jarzmik)
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents b24e2bdd 6f2116eb
......@@ -2,5 +2,7 @@ config MACH_ASM9260
bool "Alphascale ASM9260"
depends on ARCH_MULTI_V5
select CPU_ARM926T
select ASM9260_TIMER
select GENERIC_CLOCKEVENTS
help
Support for Alphascale ASM9260 based platform.
......@@ -63,6 +63,11 @@ config VT8500_TIMER
config CADENCE_TTC_TIMER
bool
config ASM9260_TIMER
bool
select CLKSRC_MMIO
select CLKSRC_OF
config CLKSRC_NOMADIK_MTU
bool
depends on (ARCH_NOMADIK || ARCH_U8500)
......@@ -245,15 +250,4 @@ config CLKSRC_PXA
help
This enables OST0 support available on PXA and SA-11x0
platforms.
config ASM9260_TIMER
bool "Alphascale ASM9260 timer driver"
depends on GENERIC_CLOCKEVENTS
select CLKSRC_MMIO
select CLKSRC_OF
default y if MACH_ASM9260
help
This enables build of a clocksource and clockevent driver for
the 32-bit System Timer hardware available on a Alphascale ASM9260.
endmenu
......@@ -224,6 +224,8 @@ static void __init mtk_timer_init(struct device_node *node)
}
rate = clk_get_rate(clk);
mtk_timer_global_reset(evt);
if (request_irq(evt->dev.irq, mtk_timer_interrupt,
IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
pr_warn("failed to setup irq %d\n", evt->dev.irq);
......@@ -232,8 +234,6 @@ static void __init mtk_timer_init(struct device_node *node)
evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
mtk_timer_global_reset(evt);
/* Configure clock source */
mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
......@@ -241,10 +241,11 @@ static void __init mtk_timer_init(struct device_node *node)
/* Configure clock event */
mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
mtk_timer_enable_irq(evt, GPT_CLK_EVT);
clockevents_config_and_register(&evt->dev, rate, 0x3,
0xffffffff);
mtk_timer_enable_irq(evt, GPT_CLK_EVT);
return;
err_clk_disable:
......
......@@ -163,7 +163,7 @@ static struct irqaction pxa_ost0_irq = {
.dev_id = &ckevt_pxa_osmr0,
};
static void pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
static void __init pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
{
timer_writel(0, OIER);
timer_writel(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
......
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