[PATCH] Another x86-64 fix for problems from the recent merge

From: Andi Kleen <ak@suse.de>,
      From Suresh.B.Siddha

Fix another bug caused by the recent IA32e merge.  The full L1 cache size
padding of the GDT didn't work with smaller cache line sizes.  Just revert
that.

I must admit I still don't understand why it didn't work, but it's better
to have a working system for now.

arch/x86_64/kernel/head.S

@@ -358,7 +358,7 @@ gdt_end:
 	/* asm/segment.h:GDT_ENTRIES must match this */	
 	/* This should be a multiple of the cache line size */
 	/* GDTs of other CPUs: */	
-	.fill (L1_CACHE_BYTES * NR_CPUS) - (gdt_end - cpu_gdt_table) 
+	.fill (GDT_SIZE * NR_CPUS) - (gdt_end - cpu_gdt_table)
 
 	.align  L1_CACHE_BYTES
 ENTRY(idt_table)	

include/asm-x86_64/segment.h

@@ -40,7 +40,7 @@
 #define FS_TLS_SEL ((GDT_ENTRY_TLS_MIN+FS_TLS)*8 + 3)
 
 #define IDT_ENTRIES 256
-#define GDT_ENTRIES (L1_CACHE_BYTES / 8) 
+#define GDT_ENTRIES 16
 #define GDT_SIZE (GDT_ENTRIES * 8)
 #define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)