Commit e5cae659 authored by Michał Winiarski's avatar Michał Winiarski Committed by Chris Wilson

drm/i915/guc: Disable rpm wakeref asserts in GuC irq handler

We're seeing "RPM wakelock ref not held during HW access" warning
otherwise. Since IRQs are synced for runtime suspend we can just disable
the wakeref asserts.
Reported-by: default avatarMarta Löfstedt <marta.lofstedt@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105710Signed-off-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180714173703.7894-1-chris@chris-wilson.co.ukReviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 60a94324
...@@ -466,11 +466,13 @@ void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc) ...@@ -466,11 +466,13 @@ void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc)
* could happen that GuC sets the bit for 2nd interrupt but Host * could happen that GuC sets the bit for 2nd interrupt but Host
* clears out the bit on handling the 1st interrupt. * clears out the bit on handling the 1st interrupt.
*/ */
disable_rpm_wakeref_asserts(dev_priv);
spin_lock(&guc->irq_lock); spin_lock(&guc->irq_lock);
val = I915_READ(SOFT_SCRATCH(15)); val = I915_READ(SOFT_SCRATCH(15));
msg = val & guc->msg_enabled_mask; msg = val & guc->msg_enabled_mask;
I915_WRITE(SOFT_SCRATCH(15), val & ~msg); I915_WRITE(SOFT_SCRATCH(15), val & ~msg);
spin_unlock(&guc->irq_lock); spin_unlock(&guc->irq_lock);
enable_rpm_wakeref_asserts(dev_priv);
intel_guc_to_host_process_recv_msg(guc, msg); intel_guc_to_host_process_recv_msg(guc, msg);
} }
......
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