Commit e6cbf998 authored by Maxime Ripard's avatar Maxime Ripard Committed by Stephen Boyd

clk: fixed-factor: Allow for a few clocks to change the parent rate

The only way for a fixed factor clock to change its rate would be to change
its parent rate.

Since passing blindly CLK_SET_RATE_PARENT might break a lot of platforms
that were relying on the fact that the parent rate wouldn't change,
introduce a compatible-based whitelist that will allow clocks to opt-in
that flag.
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 6db8c762
...@@ -14,6 +14,10 @@ Required properties: ...@@ -14,6 +14,10 @@ Required properties:
Optional properties: Optional properties:
- clock-output-names : From common clock binding. - clock-output-names : From common clock binding.
Some clocks that require special treatments are also handled by that
driver, with the compatibles:
- allwinner,sun4i-a10-pll3-2x-clk
Example: Example:
clock { clock {
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
......
...@@ -142,6 +142,11 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw) ...@@ -142,6 +142,11 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw)
EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor); EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);
#ifdef CONFIG_OF #ifdef CONFIG_OF
static const struct of_device_id set_rate_parent_matches[] = {
{ .compatible = "allwinner,sun4i-a10-pll3-2x-clk" },
{ /* Sentinel */ },
};
/** /**
* of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock
*/ */
...@@ -150,6 +155,7 @@ void __init of_fixed_factor_clk_setup(struct device_node *node) ...@@ -150,6 +155,7 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
struct clk *clk; struct clk *clk;
const char *clk_name = node->name; const char *clk_name = node->name;
const char *parent_name; const char *parent_name;
unsigned long flags = 0;
u32 div, mult; u32 div, mult;
if (of_property_read_u32(node, "clock-div", &div)) { if (of_property_read_u32(node, "clock-div", &div)) {
...@@ -167,7 +173,10 @@ void __init of_fixed_factor_clk_setup(struct device_node *node) ...@@ -167,7 +173,10 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
of_property_read_string(node, "clock-output-names", &clk_name); of_property_read_string(node, "clock-output-names", &clk_name);
parent_name = of_clk_get_parent_name(node, 0); parent_name = of_clk_get_parent_name(node, 0);
clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, if (of_match_node(set_rate_parent_matches, node))
flags |= CLK_SET_RATE_PARENT;
clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
mult, div); mult, div);
if (!IS_ERR(clk)) if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk); of_clk_add_provider(node, of_clk_src_simple_get, clk);
......
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