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Commit e6d4f08a authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
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intel_idle: Use ACPI _CST on server systems 

In many cases, especially on server systems, it is desirable to avoid
enabling C-states that have been disabled in the platform firmware
(BIOS) setup, except for C1E.

As a rule, the C-states disabled this way are not listed by ACPI
_CST, so if that is used by intel_idle along with the specific
table of C-states that it has for the given processor, the C-states
disabled through the platform firmware will not be enabled by default
by intel_idle.

Accordingly, set the use_acpi flag (introduced previously) in all
server processor profiles defined in intel_idle (so as to make it use
ACPI _CST to decide which C-states to enable by default) and set
the CPUIDLE_FLAG_ALWAYS_ENABLE flag (also introduced previously)
for C1E in all C-states tables in intel_idle that contain C1 too
(so that C1E is enabled regardless of whether or not it is listed
by ACPI _CST).
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 4ec32d9e
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Showing with 50 additions and 20 deletions
drivers/idle/intel_idle.c
View file @ e6d4f08a
...@@ -131,7 +131,7 @@ static struct cpuidle_state nehalem_cstates[] = { ...@@ -131,7 +131,7 @@ static struct cpuidle_state nehalem_cstates[] = {
{ {
.name = "C1E", .name = "C1E",
.desc = "MWAIT 0x01", .desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01), .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
.exit_latency = 10, .exit_latency = 10,
.target_residency = 20, .target_residency = 20,
.enter = &intel_idle, .enter = &intel_idle,
...@@ -168,7 +168,7 @@ static struct cpuidle_state snb_cstates[] = { ...@@ -168,7 +168,7 @@ static struct cpuidle_state snb_cstates[] = {
{ {
.name = "C1E", .name = "C1E",
.desc = "MWAIT 0x01", .desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01), .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
.exit_latency = 10, .exit_latency = 10,
.target_residency = 20, .target_residency = 20,
.enter = &intel_idle, .enter = &intel_idle,
...@@ -303,7 +303,7 @@ static struct cpuidle_state ivb_cstates[] = { ...@@ -303,7 +303,7 @@ static struct cpuidle_state ivb_cstates[] = {
{ {
.name = "C1E", .name = "C1E",
.desc = "MWAIT 0x01", .desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01), .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
.exit_latency = 10, .exit_latency = 10,
.target_residency = 20, .target_residency = 20,
.enter = &intel_idle, .enter = &intel_idle,
...@@ -348,7 +348,7 @@ static struct cpuidle_state ivt_cstates[] = { ...@@ -348,7 +348,7 @@ static struct cpuidle_state ivt_cstates[] = {
{ {
.name = "C1E", .name = "C1E",
.desc = "MWAIT 0x01", .desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01), .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
.exit_latency = 10, .exit_latency = 10,
.target_residency = 80, .target_residency = 80,
.enter = &intel_idle, .enter = &intel_idle,
...@@ -385,7 +385,7 @@ static struct cpuidle_state ivt_cstates_4s[] = { ...@@ -385,7 +385,7 @@ static struct cpuidle_state ivt_cstates_4s[] = {
{ {
.name = "C1E", .name = "C1E",
.desc = "MWAIT 0x01", .desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01), .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
.exit_latency = 10, .exit_latency = 10,
.target_residency = 250, .target_residency = 250,
.enter = &intel_idle, .enter = &intel_idle,
...@@ -422,7 +422,7 @@ static struct cpuidle_state ivt_cstates_8s[] = { ...@@ -422,7 +422,7 @@ static struct cpuidle_state ivt_cstates_8s[] = {
{ {
.name = "C1E", .name = "C1E",
.desc = "MWAIT 0x01", .desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01), .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
.exit_latency = 10, .exit_latency = 10,
.target_residency = 500, .target_residency = 500,
.enter = &intel_idle, .enter = &intel_idle,
...@@ -459,7 +459,7 @@ static struct cpuidle_state hsw_cstates[] = { ...@@ -459,7 +459,7 @@ static struct cpuidle_state hsw_cstates[] = {
{ {
.name = "C1E", .name = "C1E",
.desc = "MWAIT 0x01", .desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01), .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
.exit_latency = 10, .exit_latency = 10,
.target_residency = 20, .target_residency = 20,
.enter = &intel_idle, .enter = &intel_idle,
...@@ -527,7 +527,7 @@ static struct cpuidle_state bdw_cstates[] = { ...@@ -527,7 +527,7 @@ static struct cpuidle_state bdw_cstates[] = {
{ {
.name = "C1E", .name = "C1E",
.desc = "MWAIT 0x01", .desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01), .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
.exit_latency = 10, .exit_latency = 10,
.target_residency = 20, .target_residency = 20,
.enter = &intel_idle, .enter = &intel_idle,
...@@ -596,7 +596,7 @@ static struct cpuidle_state skl_cstates[] = { ...@@ -596,7 +596,7 @@ static struct cpuidle_state skl_cstates[] = {
{ {
.name = "C1E", .name = "C1E",
.desc = "MWAIT 0x01", .desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01), .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
.exit_latency = 10, .exit_latency = 10,
.target_residency = 20, .target_residency = 20,
.enter = &intel_idle, .enter = &intel_idle,
...@@ -665,7 +665,7 @@ static struct cpuidle_state skx_cstates[] = { ...@@ -665,7 +665,7 @@ static struct cpuidle_state skx_cstates[] = {
{ {
.name = "C1E", .name = "C1E",
.desc = "MWAIT 0x01", .desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01), .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
.exit_latency = 10, .exit_latency = 10,
.target_residency = 20, .target_residency = 20,
.enter = &intel_idle, .enter = &intel_idle,
...@@ -815,7 +815,7 @@ static struct cpuidle_state bxt_cstates[] = { ...@@ -815,7 +815,7 @@ static struct cpuidle_state bxt_cstates[] = {
{ {
.name = "C1E", .name = "C1E",
.desc = "MWAIT 0x01", .desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01), .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
.exit_latency = 10, .exit_latency = 10,
.target_residency = 20, .target_residency = 20,
.enter = &intel_idle, .enter = &intel_idle,
...@@ -876,7 +876,7 @@ static struct cpuidle_state dnv_cstates[] = { ...@@ -876,7 +876,7 @@ static struct cpuidle_state dnv_cstates[] = {
{ {
.name = "C1E", .name = "C1E",
.desc = "MWAIT 0x01", .desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01), .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
.exit_latency = 10, .exit_latency = 10,
.target_residency = 20, .target_residency = 20,
.enter = &intel_idle, .enter = &intel_idle,
...@@ -998,6 +998,13 @@ static const struct idle_cpu idle_cpu_nehalem = { ...@@ -998,6 +998,13 @@ static const struct idle_cpu idle_cpu_nehalem = {
.disable_promotion_to_c1e = true, .disable_promotion_to_c1e = true,
}; };
static const struct idle_cpu idle_cpu_nhx = {
.state_table = nehalem_cstates,
.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
.disable_promotion_to_c1e = true,
.use_acpi = true,
};
static const struct idle_cpu idle_cpu_atom = { static const struct idle_cpu idle_cpu_atom = {
.state_table = atom_cstates, .state_table = atom_cstates,
}; };
...@@ -1016,6 +1023,12 @@ static const struct idle_cpu idle_cpu_snb = { ...@@ -1016,6 +1023,12 @@ static const struct idle_cpu idle_cpu_snb = {
.disable_promotion_to_c1e = true, .disable_promotion_to_c1e = true,
}; };
static const struct idle_cpu idle_cpu_snx = {
.state_table = snb_cstates,
.disable_promotion_to_c1e = true,
.use_acpi = true,
};
static const struct idle_cpu idle_cpu_byt = { static const struct idle_cpu idle_cpu_byt = {
.state_table = byt_cstates, .state_table = byt_cstates,
.disable_promotion_to_c1e = true, .disable_promotion_to_c1e = true,
...@@ -1036,6 +1049,7 @@ static const struct idle_cpu idle_cpu_ivb = { ...@@ -1036,6 +1049,7 @@ static const struct idle_cpu idle_cpu_ivb = {
static const struct idle_cpu idle_cpu_ivt = { static const struct idle_cpu idle_cpu_ivt = {
.state_table = ivt_cstates, .state_table = ivt_cstates,
.disable_promotion_to_c1e = true, .disable_promotion_to_c1e = true,
.use_acpi = true,
}; };
static const struct idle_cpu idle_cpu_hsw = { static const struct idle_cpu idle_cpu_hsw = {
...@@ -1043,11 +1057,23 @@ static const struct idle_cpu idle_cpu_hsw = { ...@@ -1043,11 +1057,23 @@ static const struct idle_cpu idle_cpu_hsw = {
.disable_promotion_to_c1e = true, .disable_promotion_to_c1e = true,
}; };
static const struct idle_cpu idle_cpu_hsx = {
.state_table = hsw_cstates,
.disable_promotion_to_c1e = true,
.use_acpi = true,
};
static const struct idle_cpu idle_cpu_bdw = { static const struct idle_cpu idle_cpu_bdw = {
.state_table = bdw_cstates, .state_table = bdw_cstates,
.disable_promotion_to_c1e = true, .disable_promotion_to_c1e = true,
}; };
static const struct idle_cpu idle_cpu_bdx = {
.state_table = bdw_cstates,
.disable_promotion_to_c1e = true,
.use_acpi = true,
};
static const struct idle_cpu idle_cpu_skl = { static const struct idle_cpu idle_cpu_skl = {
.state_table = skl_cstates, .state_table = skl_cstates,
.disable_promotion_to_c1e = true, .disable_promotion_to_c1e = true,
...@@ -1056,15 +1082,18 @@ static const struct idle_cpu idle_cpu_skl = { ...@@ -1056,15 +1082,18 @@ static const struct idle_cpu idle_cpu_skl = {
static const struct idle_cpu idle_cpu_skx = { static const struct idle_cpu idle_cpu_skx = {
.state_table = skx_cstates, .state_table = skx_cstates,
.disable_promotion_to_c1e = true, .disable_promotion_to_c1e = true,
.use_acpi = true,
}; };
static const struct idle_cpu idle_cpu_avn = { static const struct idle_cpu idle_cpu_avn = {
.state_table = avn_cstates, .state_table = avn_cstates,
.disable_promotion_to_c1e = true, .disable_promotion_to_c1e = true,
.use_acpi = true,
}; };
static const struct idle_cpu idle_cpu_knl = { static const struct idle_cpu idle_cpu_knl = {
.state_table = knl_cstates, .state_table = knl_cstates,
.use_acpi = true,
}; };
static const struct idle_cpu idle_cpu_bxt = { static const struct idle_cpu idle_cpu_bxt = {
...@@ -1075,20 +1104,21 @@ static const struct idle_cpu idle_cpu_bxt = { ...@@ -1075,20 +1104,21 @@ static const struct idle_cpu idle_cpu_bxt = {
static const struct idle_cpu idle_cpu_dnv = { static const struct idle_cpu idle_cpu_dnv = {
.state_table = dnv_cstates, .state_table = dnv_cstates,
.disable_promotion_to_c1e = true, .disable_promotion_to_c1e = true,
.use_acpi = true,
}; };
static const struct x86_cpu_id intel_idle_ids[] __initconst = { static const struct x86_cpu_id intel_idle_ids[] __initconst = {
INTEL_CPU_FAM6(NEHALEM_EP, idle_cpu_nehalem), INTEL_CPU_FAM6(NEHALEM_EP, idle_cpu_nhx),
INTEL_CPU_FAM6(NEHALEM, idle_cpu_nehalem), INTEL_CPU_FAM6(NEHALEM, idle_cpu_nehalem),
INTEL_CPU_FAM6(NEHALEM_G, idle_cpu_nehalem), INTEL_CPU_FAM6(NEHALEM_G, idle_cpu_nehalem),
INTEL_CPU_FAM6(WESTMERE, idle_cpu_nehalem), INTEL_CPU_FAM6(WESTMERE, idle_cpu_nehalem),
INTEL_CPU_FAM6(WESTMERE_EP, idle_cpu_nehalem), INTEL_CPU_FAM6(WESTMERE_EP, idle_cpu_nhx),
INTEL_CPU_FAM6(NEHALEM_EX, idle_cpu_nehalem), INTEL_CPU_FAM6(NEHALEM_EX, idle_cpu_nhx),
INTEL_CPU_FAM6(ATOM_BONNELL, idle_cpu_atom), INTEL_CPU_FAM6(ATOM_BONNELL, idle_cpu_atom),
INTEL_CPU_FAM6(ATOM_BONNELL_MID, idle_cpu_lincroft), INTEL_CPU_FAM6(ATOM_BONNELL_MID, idle_cpu_lincroft),
INTEL_CPU_FAM6(WESTMERE_EX, idle_cpu_nehalem), INTEL_CPU_FAM6(WESTMERE_EX, idle_cpu_nhx),
INTEL_CPU_FAM6(SANDYBRIDGE, idle_cpu_snb), INTEL_CPU_FAM6(SANDYBRIDGE, idle_cpu_snb),
INTEL_CPU_FAM6(SANDYBRIDGE_X, idle_cpu_snb), INTEL_CPU_FAM6(SANDYBRIDGE_X, idle_cpu_snx),
INTEL_CPU_FAM6(ATOM_SALTWELL, idle_cpu_atom), INTEL_CPU_FAM6(ATOM_SALTWELL, idle_cpu_atom),
INTEL_CPU_FAM6(ATOM_SILVERMONT, idle_cpu_byt), INTEL_CPU_FAM6(ATOM_SILVERMONT, idle_cpu_byt),
INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, idle_cpu_tangier), INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, idle_cpu_tangier),
...@@ -1096,14 +1126,14 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = { ...@@ -1096,14 +1126,14 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
INTEL_CPU_FAM6(IVYBRIDGE, idle_cpu_ivb), INTEL_CPU_FAM6(IVYBRIDGE, idle_cpu_ivb),
INTEL_CPU_FAM6(IVYBRIDGE_X, idle_cpu_ivt), INTEL_CPU_FAM6(IVYBRIDGE_X, idle_cpu_ivt),
INTEL_CPU_FAM6(HASWELL, idle_cpu_hsw), INTEL_CPU_FAM6(HASWELL, idle_cpu_hsw),
INTEL_CPU_FAM6(HASWELL_X, idle_cpu_hsw), INTEL_CPU_FAM6(HASWELL_X, idle_cpu_hsx),
INTEL_CPU_FAM6(HASWELL_L, idle_cpu_hsw), INTEL_CPU_FAM6(HASWELL_L, idle_cpu_hsw),
INTEL_CPU_FAM6(HASWELL_G, idle_cpu_hsw), INTEL_CPU_FAM6(HASWELL_G, idle_cpu_hsw),
INTEL_CPU_FAM6(ATOM_SILVERMONT_D, idle_cpu_avn), INTEL_CPU_FAM6(ATOM_SILVERMONT_D, idle_cpu_avn),
INTEL_CPU_FAM6(BROADWELL, idle_cpu_bdw), INTEL_CPU_FAM6(BROADWELL, idle_cpu_bdw),
INTEL_CPU_FAM6(BROADWELL_G, idle_cpu_bdw), INTEL_CPU_FAM6(BROADWELL_G, idle_cpu_bdw),
INTEL_CPU_FAM6(BROADWELL_X, idle_cpu_bdw), INTEL_CPU_FAM6(BROADWELL_X, idle_cpu_bdx),
INTEL_CPU_FAM6(BROADWELL_D, idle_cpu_bdw), INTEL_CPU_FAM6(BROADWELL_D, idle_cpu_bdx),
INTEL_CPU_FAM6(SKYLAKE_L, idle_cpu_skl), INTEL_CPU_FAM6(SKYLAKE_L, idle_cpu_skl),
INTEL_CPU_FAM6(SKYLAKE, idle_cpu_skl), INTEL_CPU_FAM6(SKYLAKE, idle_cpu_skl),
INTEL_CPU_FAM6(KABYLAKE_L, idle_cpu_skl), INTEL_CPU_FAM6(KABYLAKE_L, idle_cpu_skl),
......
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