iwlegacy: indentions and whitespaces

Process iwlegacy source files using:

indent -npro -l500 -nhnl
indent -npro -kr -i8 -ts8 -sob -l80 -nbbo -ss -ncs -cp1 -il0 -psl

Plus manual compilation fixes.
Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>

drivers/net/wireless/iwlegacy/3945.h

@@ -27,7 +27,7 @@
 #ifndef __il_3945_h__
 #define __il_3945_h__
 
-#include <linux/pci.h> /* for struct pci_device_id */
+#include <linux/pci.h>		/* for struct pci_device_id */
 #include <linux/kernel.h>
 #include <net/ieee80211_radiotap.h>
 
@@ -93,7 +93,6 @@ struct il3945_rs_sta {
 	int last_txrate_idx;
 };
 
-
 /*
  * The common struct MUST be first because it is shared between
  * 3945 and 4965!
@@ -186,7 +185,6 @@ struct il3945_ibss_seq {
 #define IL_RX_STATS(x) (&x->u.rx_frame.stats)
 #define IL_RX_DATA(x) (IL_RX_HDR(x)->payload)
 
-
 /******************************************************************************
  *
  * Functions implemented in iwl3945-base.c which are forward declared here
@@ -197,9 +195,10 @@ extern int il3945_calc_db_from_ratio(int sig_ratio);
 extern void il3945_rx_replenish(void *data);
 extern void il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
 extern unsigned int il3945_fill_beacon_frame(struct il_priv *il,
-					struct ieee80211_hdr *hdr, int left);
+					     struct ieee80211_hdr *hdr,
+					     int left);
 extern int il3945_dump_nic_event_log(struct il_priv *il, bool full_log,
-				       char **buf, bool display);
+				     char **buf, bool display);
 extern void il3945_dump_nic_error_log(struct il_priv *il);
 
 /******************************************************************************
@@ -229,34 +228,29 @@ extern void il3945_hw_txq_ctx_free(struct il_priv *il);
 extern void il3945_hw_txq_ctx_stop(struct il_priv *il);
 extern int il3945_hw_nic_reset(struct il_priv *il);
 extern int il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il,
-					    struct il_tx_queue *txq,
-					    dma_addr_t addr, u16 len,
-					    u8 reset, u8 pad);
-extern void il3945_hw_txq_free_tfd(struct il_priv *il,
-				    struct il_tx_queue *txq);
+					   struct il_tx_queue *txq,
+					   dma_addr_t addr, u16 len, u8 reset,
+					   u8 pad);
+extern void il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
 extern int il3945_hw_get_temperature(struct il_priv *il);
-extern int il3945_hw_tx_queue_init(struct il_priv *il,
-				struct il_tx_queue *txq);
+extern int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);
 extern unsigned int il3945_hw_get_beacon_cmd(struct il_priv *il,
-				 struct il3945_frame *frame, u8 rate);
-void il3945_hw_build_tx_cmd_rate(struct il_priv *il,
-				  struct il_device_cmd *cmd,
-				  struct ieee80211_tx_info *info,
-				  struct ieee80211_hdr *hdr,
-				  int sta_id, int tx_id);
+					     struct il3945_frame *frame,
+					     u8 rate);
+void il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
+				 struct ieee80211_tx_info *info,
+				 struct ieee80211_hdr *hdr, int sta_id,
+				 int tx_id);
 extern int il3945_hw_reg_send_txpower(struct il_priv *il);
 extern int il3945_hw_reg_set_txpower(struct il_priv *il, s8 power);
-extern void il3945_hdl_stats(struct il_priv *il,
-				 struct il_rx_buf *rxb);
-void il3945_hdl_c_stats(struct il_priv *il,
-			      struct il_rx_buf *rxb);
+extern void il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb);
+void il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb);
 extern void il3945_disable_events(struct il_priv *il);
 extern int il4965_get_temperature(const struct il_priv *il);
 extern void il3945_post_associate(struct il_priv *il);
 extern void il3945_config_ap(struct il_priv *il);
 
-extern int il3945_commit_rxon(struct il_priv *il,
-			       struct il_rxon_context *ctx);
+extern int il3945_commit_rxon(struct il_priv *il, struct il_rxon_context *ctx);
 
 /**
  * il3945_hw_find_station - Find station id for a given BSSID
@@ -266,7 +260,7 @@ extern int il3945_commit_rxon(struct il_priv *il,
  * not yet been merged into a single common layer for managing the
  * station tables.
  */
-extern u8 il3945_hw_find_station(struct il_priv *il, const u8 *bssid);
+extern u8 il3945_hw_find_station(struct il_priv *il, const u8 * bssid);
 
 extern struct ieee80211_ops il3945_hw_ops;
 
@@ -275,8 +269,10 @@ extern int il3945_init_hw_rate_table(struct il_priv *il);
 extern void il3945_reg_txpower_periodic(struct il_priv *il);
 extern int il3945_txpower_set_from_eeprom(struct il_priv *il);
 
-extern const struct il_channel_info *il3945_get_channel_info(
-	const struct il_priv *il, enum ieee80211_band band, u16 channel);
+extern const struct il_channel_info *il3945_get_channel_info(const struct
+							     il_priv *il,
+							     enum ieee80211_band
+							     band, u16 channel);
 
 extern int il3945_rs_next_rate(struct il_priv *il, int rate);
 
@@ -287,8 +283,6 @@ void il3945_post_scan(struct il_priv *il);
 /* rates */
 extern const struct il3945_rate_info il3945_rates[RATE_COUNT_3945];
 
-
-
 /* RSSI to dBm */
 #define IL39_RSSI_OFFSET	95
 
@@ -323,7 +317,7 @@ struct il3945_eeprom_txpower_sample {
  * DO NOT ALTER THIS STRUCTURE!!!
  */
 struct il3945_eeprom_txpower_group {
-	struct il3945_eeprom_txpower_sample samples[5];  /* 5 power levels */
+	struct il3945_eeprom_txpower_sample samples[5];	/* 5 power levels */
 	s32 a, b, c, d, e;	/* coefficients for voltage->power
 				 * formula (signed) */
 	s32 Fa, Fb, Fc, Fd, Fe;	/* these modify coeffs based on
@@ -354,7 +348,7 @@ struct il3945_eeprom_temperature_corr {
  */
 struct il3945_eeprom {
 	u8 reserved0[16];
-	u16 device_id;	/* abs.ofs: 16 */
+	u16 device_id;		/* abs.ofs: 16 */
 	u8 reserved1[2];
 	u16 pmc;		/* abs.ofs: 20 */
 	u8 reserved2[20];
@@ -389,7 +383,7 @@ struct il3945_eeprom {
  * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  */
 	u16 band_1_count;	/* abs.ofs: 196 */
-	struct il_eeprom_channel band_1_channels[14];  /* abs.ofs: 198 */
+	struct il_eeprom_channel band_1_channels[14];	/* abs.ofs: 198 */
 
 /*
  * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
@@ -397,28 +391,28 @@ struct il3945_eeprom {
  * (4915-5080MHz) (none of these is ever supported)
  */
 	u16 band_2_count;	/* abs.ofs: 226 */
-	struct il_eeprom_channel band_2_channels[13];  /* abs.ofs: 228 */
+	struct il_eeprom_channel band_2_channels[13];	/* abs.ofs: 228 */
 
 /*
  * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  * (5170-5320MHz)
  */
 	u16 band_3_count;	/* abs.ofs: 254 */
-	struct il_eeprom_channel band_3_channels[12];  /* abs.ofs: 256 */
+	struct il_eeprom_channel band_3_channels[12];	/* abs.ofs: 256 */
 
 /*
  * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  * (5500-5700MHz)
  */
 	u16 band_4_count;	/* abs.ofs: 280 */
-	struct il_eeprom_channel band_4_channels[11];  /* abs.ofs: 282 */
+	struct il_eeprom_channel band_4_channels[11];	/* abs.ofs: 282 */
 
 /*
  * 5.7 GHz channels 145, 149, 153, 157, 161, 165
  * (5725-5825MHz)
  */
 	u16 band_5_count;	/* abs.ofs: 304 */
-	struct il_eeprom_channel band_5_channels[6];  /* abs.ofs: 306 */
+	struct il_eeprom_channel band_5_channels[6];	/* abs.ofs: 306 */
 
 	u8 reserved9[194];
 
@@ -428,7 +422,7 @@ struct il3945_eeprom {
 #define IL_NUM_TX_CALIB_GROUPS 5
 	struct il3945_eeprom_txpower_group groups[IL_NUM_TX_CALIB_GROUPS];
 /* abs.ofs: 512 */
-	struct il3945_eeprom_temperature_corr corrections;  /* abs.ofs: 832 */
+	struct il3945_eeprom_temperature_corr corrections;	/* abs.ofs: 832 */
 	u8 reserved16[172];	/* fill out to full 1024 byte block */
 } __packed;
 
@@ -474,7 +468,8 @@ struct il3945_eeprom {
 /* Size of uCode instruction memory in bootstrap state machine */
 #define IL39_MAX_BSM_SIZE IL39_RTC_INST_SIZE
 
-static inline int il3945_hw_valid_rtc_data_addr(u32 addr)
+static inline int
+il3945_hw_valid_rtc_data_addr(u32 addr)
 {
 	return (addr >= IL39_RTC_DATA_LOWER_BOUND &&
 		addr < IL39_RTC_DATA_UPPER_BOUND);
@@ -486,19 +481,22 @@ struct il3945_shared {
 	__le32 tx_base_ptr[8];
 } __packed;
 
-static inline u8 il3945_hw_get_rate(__le16 rate_n_flags)
+static inline u8
+il3945_hw_get_rate(__le16 rate_n_flags)
 {
 	return le16_to_cpu(rate_n_flags) & 0xFF;
 }
 
-static inline u16 il3945_hw_get_rate_n_flags(__le16 rate_n_flags)
+static inline u16
+il3945_hw_get_rate_n_flags(__le16 rate_n_flags)
 {
 	return le16_to_cpu(rate_n_flags);
 }
 
-static inline __le16 il3945_hw_set_rate_n_flags(u8 rate, u16 flags)
+static inline __le16
+il3945_hw_set_rate_n_flags(u8 rate, u16 flags)
 {
-	return cpu_to_le16((u16)rate|flags);
+	return cpu_to_le16((u16) rate | flags);
 }
 
 /************************************/
@@ -553,7 +551,6 @@ static inline __le16 il3945_hw_set_rate_n_flags(u8 rate, u16 flags)
 #define FH39_TSSR_MSG_CONFIG      (FH39_TSSR_TBL + 0x008)
 #define FH39_TSSR_TX_STATUS       (FH39_TSSR_TBL + 0x010)
 
-
 /* DBM */
 
 #define FH39_SRVC_CHNL                            (6)
@@ -622,29 +619,31 @@ struct il3945_tfd {
 } __packed;
 
 #ifdef CONFIG_IWLEGACY_DEBUGFS
-ssize_t il3945_ucode_rx_stats_read(struct file *file, char __user *user_buf,
-				    size_t count, loff_t *ppos);
-ssize_t il3945_ucode_tx_stats_read(struct file *file, char __user *user_buf,
-				    size_t count, loff_t *ppos);
+ssize_t il3945_ucode_rx_stats_read(struct file *file, char __user * user_buf,
+				   size_t count, loff_t * ppos);
+ssize_t il3945_ucode_tx_stats_read(struct file *file, char __user * user_buf,
+				   size_t count, loff_t * ppos);
 ssize_t il3945_ucode_general_stats_read(struct file *file,
-					 char __user *user_buf, size_t count,
-					 loff_t *ppos);
+					char __user * user_buf, size_t count,
+					loff_t * ppos);
 #else
-static ssize_t il3945_ucode_rx_stats_read(struct file *file,
-					   char __user *user_buf, size_t count,
-					   loff_t *ppos)
+static ssize_t
+il3945_ucode_rx_stats_read(struct file *file, char __user * user_buf,
+			   size_t count, loff_t * ppos)
 {
 	return 0;
 }
-static ssize_t il3945_ucode_tx_stats_read(struct file *file,
-					   char __user *user_buf, size_t count,
-					   loff_t *ppos)
+
+static ssize_t
+il3945_ucode_tx_stats_read(struct file *file, char __user * user_buf,
+			   size_t count, loff_t * ppos)
 {
 	return 0;
 }
-static ssize_t il3945_ucode_general_stats_read(struct file *file,
-						char __user *user_buf,
-						size_t count, loff_t *ppos)
+
+static ssize_t
+il3945_ucode_general_stats_read(struct file *file, char __user * user_buf,
+				size_t count, loff_t * ppos)
 {
 	return 0;
 }

drivers/net/wireless/iwlegacy/csr.h

@@ -82,13 +82,13 @@
  */
 #define CSR_BASE    (0x000)
 
-#define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
-#define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
-#define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
-#define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
-#define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
-#define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
-#define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
+#define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000)	/* hardware interface config */
+#define CSR_INT_COALESCING      (CSR_BASE+0x004)	/* accum ints, 32-usec units */
+#define CSR_INT                 (CSR_BASE+0x008)	/* host interrupt status/ack */
+#define CSR_INT_MASK            (CSR_BASE+0x00c)	/* host interrupt enable */
+#define CSR_FH_INT_STATUS       (CSR_BASE+0x010)	/* busmaster int status/ack */
+#define CSR_GPIO_IN             (CSR_BASE+0x018)	/* read external chip pins */
+#define CSR_RESET               (CSR_BASE+0x020)	/* busmaster enable, NMI, etc */
 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
 
 /* 2nd byte of CSR_INT_COALESCING, not accessible via _il_wr()! */
@@ -166,26 +166,26 @@
 
 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A	(0x00080000)
 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM	(0x00200000)
-#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY	(0x00400000) /* PCI_OWN_SEM */
-#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
-#define CSR_HW_IF_CONFIG_REG_PREPARE		  (0x08000000) /* WAKE_ME */
+#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY	(0x00400000)	/* PCI_OWN_SEM */
+#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000)	/* ME_OWN */
+#define CSR_HW_IF_CONFIG_REG_PREPARE		  (0x08000000)	/* WAKE_ME */
 
-#define CSR_INT_PERIODIC_DIS			(0x00) /* disable periodic int*/
-#define CSR_INT_PERIODIC_ENA			(0xFF) /* 255*32 usec ~ 8 msec*/
+#define CSR_INT_PERIODIC_DIS			(0x00)	/* disable periodic int */
+#define CSR_INT_PERIODIC_ENA			(0xFF)	/* 255*32 usec ~ 8 msec */
 
 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
  * acknowledged (reset) by host writing "1" to flagged bits. */
-#define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
-#define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
-#define CSR_INT_BIT_RX_PERIODIC	 (1 << 28) /* Rx periodic */
-#define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
-#define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
-#define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
-#define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
-#define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
-#define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses, 3945 */
-#define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
-#define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */
+#define CSR_INT_BIT_FH_RX        (1 << 31)	/* Rx DMA, cmd responses, FH_INT[17:16] */
+#define CSR_INT_BIT_HW_ERR       (1 << 29)	/* DMA hardware error FH_INT[31] */
+#define CSR_INT_BIT_RX_PERIODIC	 (1 << 28)	/* Rx periodic */
+#define CSR_INT_BIT_FH_TX        (1 << 27)	/* Tx DMA FH_INT[1:0] */
+#define CSR_INT_BIT_SCD          (1 << 26)	/* TXQ pointer advanced */
+#define CSR_INT_BIT_SW_ERR       (1 << 25)	/* uCode error */
+#define CSR_INT_BIT_RF_KILL      (1 << 7)	/* HW RFKILL switch GP_CNTRL[27] toggled */
+#define CSR_INT_BIT_CT_KILL      (1 << 6)	/* Critical temp (chip too hot) rfkill */
+#define CSR_INT_BIT_SW_RX        (1 << 3)	/* Rx, command responses, 3945 */
+#define CSR_INT_BIT_WAKEUP       (1 << 1)	/* NIC controller waking up (pwr mgmt) */
+#define CSR_INT_BIT_ALIVE        (1 << 0)	/* uCode interrupts once it initializes */
 
 #define CSR_INI_SET_MASK	(CSR_INT_BIT_FH_RX   | \
 				 CSR_INT_BIT_HW_ERR  | \
@@ -197,21 +197,20 @@
 				 CSR_INT_BIT_ALIVE)
 
 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
-#define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
-#define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
-#define CSR39_FH_INT_BIT_RX_CHNL2  (1 << 18) /* Rx channel 2 (3945 only) */
-#define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
-#define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
-#define CSR39_FH_INT_BIT_TX_CHNL6  (1 << 6)  /* Tx channel 6 (3945 only) */
-#define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
-#define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */
+#define CSR_FH_INT_BIT_ERR       (1 << 31)	/* Error */
+#define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30)	/* High priority Rx, bypass coalescing */
+#define CSR39_FH_INT_BIT_RX_CHNL2  (1 << 18)	/* Rx channel 2 (3945 only) */
+#define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17)	/* Rx channel 1 */
+#define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16)	/* Rx channel 0 */
+#define CSR39_FH_INT_BIT_TX_CHNL6  (1 << 6)	/* Tx channel 6 (3945 only) */
+#define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)	/* Tx channel 1 */
+#define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)	/* Tx channel 0 */
 
 #define CSR39_FH_INT_RX_MASK	(CSR_FH_INT_BIT_HI_PRIOR | \
 				 CSR39_FH_INT_BIT_RX_CHNL2 | \
 				 CSR_FH_INT_BIT_RX_CHNL1 | \
 				 CSR_FH_INT_BIT_RX_CHNL0)
 
-
 #define CSR39_FH_INT_TX_MASK	(CSR39_FH_INT_BIT_TX_CHNL6 | \
 				 CSR_FH_INT_BIT_TX_CHNL1 | \
 				 CSR_FH_INT_BIT_TX_CHNL0)
@@ -285,7 +284,6 @@
 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
 
-
 /* EEPROM REG */
 #define CSR_EEPROM_REG_READ_VALID_MSK	(0x00000001)
 #define CSR_EEPROM_REG_BIT_CMD		(0x00000002)
@@ -293,19 +291,18 @@
 #define CSR_EEPROM_REG_MSK_DATA		(0xFFFF0000)
 
 /* EEPROM GP */
-#define CSR_EEPROM_GP_VALID_MSK		(0x00000007) /* signature */
+#define CSR_EEPROM_GP_VALID_MSK		(0x00000007)	/* signature */
 #define CSR_EEPROM_GP_IF_OWNER_MSK	(0x00000180)
 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K		(0x00000002)
 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K		(0x00000004)
 
 /* GP REG */
-#define CSR_GP_REG_POWER_SAVE_STATUS_MSK            (0x03000000) /* bit 24/25 */
+#define CSR_GP_REG_POWER_SAVE_STATUS_MSK            (0x03000000)	/* bit 24/25 */
 #define CSR_GP_REG_NO_POWER_SAVE            (0x00000000)
 #define CSR_GP_REG_MAC_POWER_SAVE           (0x01000000)
 #define CSR_GP_REG_PHY_POWER_SAVE           (0x02000000)
 #define CSR_GP_REG_POWER_SAVE_ERROR         (0x03000000)
 
-
 /* CSR GIO */
 #define CSR_GIO_REG_VAL_L0S_ENABLED	(0x00000002)
 

drivers/net/wireless/iwlegacy/prph.h

@@ -91,9 +91,9 @@
 #define APMG_PS_CTRL_VAL_RESET_REQ		(0x04000000)
 #define APMG_PS_CTRL_MSK_PWR_SRC		(0x03000000)
 #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN		(0x00000000)
-#define APMG_PS_CTRL_VAL_PWR_SRC_MAX		(0x01000000) /* 3945 only */
+#define APMG_PS_CTRL_VAL_PWR_SRC_MAX		(0x01000000)	/* 3945 only */
 #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX		(0x02000000)
-#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK	(0x000001E0) /* bit 8:5 */
+#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK	(0x000001E0)	/* bit 8:5 */
 #define APMG_SVR_DIGITAL_VOLTAGE_1_32		(0x00000060)
 
 #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS		(0x00000800)
@@ -202,19 +202,19 @@
  */
 
 /* BSM bit fields */
-#define BSM_WR_CTRL_REG_BIT_START     (0x80000000) /* start boot load now */
-#define BSM_WR_CTRL_REG_BIT_START_EN  (0x40000000) /* enable boot after pwrup*/
-#define BSM_DRAM_INST_LOAD            (0x80000000) /* start program load now */
+#define BSM_WR_CTRL_REG_BIT_START     (0x80000000)	/* start boot load now */
+#define BSM_WR_CTRL_REG_BIT_START_EN  (0x40000000)	/* enable boot after pwrup */
+#define BSM_DRAM_INST_LOAD            (0x80000000)	/* start program load now */
 
 /* BSM addresses */
 #define BSM_BASE                     (PRPH_BASE + 0x3400)
 #define BSM_END                      (PRPH_BASE + 0x3800)
 
-#define BSM_WR_CTRL_REG              (BSM_BASE + 0x000) /* ctl and status */
-#define BSM_WR_MEM_SRC_REG           (BSM_BASE + 0x004) /* source in BSM mem */
-#define BSM_WR_MEM_DST_REG           (BSM_BASE + 0x008) /* dest in SRAM mem */
-#define BSM_WR_DWCOUNT_REG           (BSM_BASE + 0x00C) /* bytes */
-#define BSM_WR_STATUS_REG            (BSM_BASE + 0x010) /* bit 0:  1 == done */
+#define BSM_WR_CTRL_REG              (BSM_BASE + 0x000)	/* ctl and status */
+#define BSM_WR_MEM_SRC_REG           (BSM_BASE + 0x004)	/* source in BSM mem */
+#define BSM_WR_MEM_DST_REG           (BSM_BASE + 0x008)	/* dest in SRAM mem */
+#define BSM_WR_DWCOUNT_REG           (BSM_BASE + 0x00C)	/* bytes */
+#define BSM_WR_STATUS_REG            (BSM_BASE + 0x010)	/* bit 0:  1 == done */
 
 /*
  * Pointers and size regs for bootstrap load and data SRAM save/restore.
@@ -231,8 +231,7 @@
  * Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1)
  */
 #define BSM_SRAM_LOWER_BOUND         (PRPH_BASE + 0x3800)
-#define BSM_SRAM_SIZE			(1024) /* bytes */
-
+#define BSM_SRAM_SIZE			(1024)	/* bytes */
 
 /* 3945 Tx scheduler registers */
 #define ALM_SCD_BASE                        (PRPH_BASE + 0x2E00)
@@ -520,4 +519,4 @@
 
 /*********************** END TX SCHEDULER *************************************/
 
-#endif				/* __il_prph_h__ */
+#endif /* __il_prph_h__ */