[ARM] Remove redundant instruction cache code from decompressor.

Now that we cleanly support handling of the cache for various ARM
processors in head.S, the per-processor class include file, and
associated inline function is no longer required.  This changeset
removes these files and the function call.

arch/arm/boot/compressed/misc.c

@@ -22,7 +22,6 @@ unsigned int __machine_arch_type;
 
 #include <asm/uaccess.h>
 #include <asm/arch/uncompress.h>
-#include <asm/proc/uncompress.h>
 
 #ifdef STANDALONE_DEBUG
 #define puts printf
@@ -291,7 +290,6 @@ decompress_kernel(ulg output_start, ulg free_mem_ptr_p, ulg free_mem_ptr_end_p,
 	free_mem_ptr_end	= free_mem_ptr_end_p;
 	__machine_arch_type	= arch_id;
 
-	proc_decomp_setup();
 	arch_decomp_setup();
 
 	makecrc();

include/asm-arm/proc-armo/uncompress.h

-/*
- *  linux/include/asm-arm/proc-armo/uncompress.h
- *
- *  Copyright (C) 1997 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#define proc_decomp_setup()

include/asm-arm/proc-armv/uncompress.h

-/*
- *  linux/include/asm-arm/proc-armv/uncompress.h
- *
- *  Copyright (C) 1997 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-static inline void proc_decomp_setup (void)
-{
-	__asm__ __volatile__("
-	mrc	p15, 0, r0, c0, c0
-	eor	r0, r0, #0x44 << 24
-	eor	r0, r0, #0x01 << 16
-	eor	r0, r0, #0xA1 << 8
-	movs	r0, r0, lsr #5
-	mcreq	p15, 0, r0, c7, c5, 0		@ flush I cache
-	mrceq	p15, 0, r0, c1, c0
-	orreq	r0, r0, #1 << 12
-	mcreq	p15, 0, r0, c1, c0		@ enable I cache
-	mov	r0, #0
-	mcreq	p15, 0, r0, c15, c1, 2		@ enable clock switching
-	" : : : "r0", "cc", "memory");
-}