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Commit e8690861 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc 

* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (408 commits)
  [POWERPC] Add memchr() to the bootwrapper
  [POWERPC] Implement logging of unhandled signals
  [POWERPC] Add legacy serial support for OPB with flattened device tree
  [POWERPC] Use 1TB segments
  [POWERPC] XilinxFB: Allow fixed framebuffer base address
  [POWERPC] XilinxFB: Add support for custom screen resolution
  [POWERPC] XilinxFB: Use pdata to pass around framebuffer parameters
  [POWERPC] PCI: Add 64-bit physical address support to setup_indirect_pci
  [POWERPC] 4xx: Kilauea defconfig file
  [POWERPC] 4xx: Kilauea DTS
  [POWERPC] 4xx: Add AMCC Kilauea eval board support to platforms/40x
  [POWERPC] 4xx: Add AMCC 405EX support to cputable.c
  [POWERPC] Adjust TASK_SIZE on ppc32 systems to 3GB that are capable
  [POWERPC] Use PAGE_OFFSET to tell if an address is user/kernel in SW TLB handlers
  [POWERPC] 85xx: Enable FP emulation in MPC8560 ADS defconfig
  [POWERPC] 85xx: Killed <asm/mpc85xx.h>
  [POWERPC] 85xx: Add cpm nodes for 8541/8555 CDS
  [POWERPC] 85xx: Convert mpc8560ads to the new CPM binding.
  [POWERPC] mpc8272ads: Remove muram from the CPM reg property.
  [POWERPC] Make clockevents work on PPC601 processors
  ...

Fixed up conflict in Documentation/powerpc/booting-without-of.txt manually.
parents 54730742 9b4b8feb
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MAINTAINERS
View file @ e8690861
......@@ -1535,7 +1535,7 @@ P: Pantelis Antoniou
M: pantelis.antoniou@gmail.com
P: Vitaly Bordug
M: vbordug@ru.mvista.com
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
L: netdev@vger.kernel.org
S: Maintained
......@@ -1543,14 +1543,14 @@ FREESCALE HIGHSPEED USB DEVICE DRIVER
P: Li Yang
M: leoli@freescale.com
L: linux-usb-devel@lists.sourceforge.net
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
S: Maintained
FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
P: Li Yang
M: leoli@freescale.com
L: netdev@vger.kernel.org
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
S: Maintained
FILE LOCKING (flock() and fcntl()/lockf())
......@@ -2297,38 +2297,49 @@ S: Maintained
LINUX FOR POWERPC EMBEDDED MPC52XX
P: Sylvain Munaut
M: tnt@246tNt.com
P: Grant Likely
M: grant.likely@secretlab.ca
W: http://www.246tNt.com/mpc52xx/
W: http://www.penguinppc.org/
L: linuxppc-dev@ozlabs.org
L: linuxppc-embedded@ozlabs.org
S: Maintained
LINUX FOR POWERPC EMBEDDED PPC4XX
P: Josh Boyer
M: jwboyer@linux.vnet.ibm.com
P: Matt Porter
M: mporter@kernel.crashing.org
W: http://www.penguinppc.org/
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
T: git kernel.org:/pub/scm/linux/kernel/git/jwboyer/powerpc.git
S: Maintained
LINUX FOR POWERPC EMBEDDED XILINX VIRTEX
P: Grant Likely
M: grant.likely@secretlab.ca
W: http://wiki.secretlab.ca/index.php/Linux_on_Xilinx_Virtex
L: linuxppc-dev@ozlabs.org
S: Maintained
LINUX FOR POWERPC BOOT CODE
P: Tom Rini
M: trini@kernel.crashing.org
W: http://www.penguinppc.org/
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
S: Maintained
LINUX FOR POWERPC EMBEDDED PPC8XX
P: Marcelo Tosatti
M: marcelo@kvack.org
W: http://www.penguinppc.org/
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
S: Maintained
LINUX FOR POWERPC EMBEDDED PPC83XX AND PPC85XX
P: Kumar Gala
M: galak@kernel.crashing.org
W: http://www.penguinppc.org/
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
S: Maintained
LINUX FOR POWERPC PA SEMI PWRFICIENT
......@@ -2990,7 +3001,7 @@ POWERPC 4xx EMAC DRIVER
P: Eugene Surovegin
M: ebs@ebshome.net
W: http://kernel.ebshome.net/emac/
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
L: netdev@vger.kernel.org
S: Maintained
......
arch/powerpc/Kconfig
View file @ e8690861
......@@ -14,6 +14,11 @@ config 64BIT
bool
default y if PPC64
config WORD_SIZE
int
default 64 if PPC64
default 32 if !PPC64
config PPC_MERGE
def_bool y
......@@ -21,6 +26,18 @@ config MMU
bool
default y
config GENERIC_CMOS_UPDATE
def_bool y
config GENERIC_TIME
def_bool y
config GENERIC_TIME_VSYSCALL
def_bool y
config GENERIC_CLOCKEVENTS
def_bool y
config GENERIC_HARDIRQS
bool
default y
......@@ -156,6 +173,7 @@ config HIGHMEM
bool "High memory support"
depends on PPC32
source kernel/time/Kconfig
source kernel/Kconfig.hz
source kernel/Kconfig.preempt
source "fs/Kconfig.binfmt"
......@@ -180,17 +198,29 @@ config MATH_EMULATION
unit, which will allow programs that use floating-point
instructions to run.
config 8XX_MINIMAL_FPEMU
bool "Minimal math emulation for 8xx"
depends on 8xx && !MATH_EMULATION
help
Older arch/ppc kernels still emulated a few floating point
instructions such as load and store, even when full math
emulation is disabled. Say "Y" here if you want to preserve
this behavior.
It is recommended that you build a soft-float userspace instead.
config IOMMU_VMERGE
bool "Enable IOMMU virtual merging (EXPERIMENTAL)"
depends on EXPERIMENTAL && PPC64
default n
bool "Enable IOMMU virtual merging"
depends on PPC64
default y
help
Cause IO segments sent to a device for DMA to be merged virtually
by the IOMMU when they happen to have been allocated contiguously.
This doesn't add pressure to the IOMMU allocator. However, some
drivers don't support getting large merged segments coming back
from *_map_sg(). Say Y if you know the drivers you are using are
properly handling this case.
from *_map_sg().
Most drivers don't have this problem; it is safe to say Y here.
config HOTPLUG_CPU
bool "Support for enabling/disabling CPUs"
......@@ -465,7 +495,7 @@ config PCI_8260
config 8260_PCI9
bool "Enable workaround for MPC826x erratum PCI 9"
depends on PCI_8260 && !ADS8272
depends on PCI_8260 && !8272
default y
choice
......@@ -569,7 +599,8 @@ config TASK_SIZE_BOOL
config TASK_SIZE
hex "Size of user task space" if TASK_SIZE_BOOL
default "0x80000000"
default "0x80000000" if PPC_PREP || PPC_8xx
default "0xc0000000"
config CONSISTENT_START_BOOL
bool "Set custom consistent memory pool address"
......@@ -581,6 +612,7 @@ config CONSISTENT_START_BOOL
config CONSISTENT_START
hex "Base virtual address of consistent memory pool" if CONSISTENT_START_BOOL
default "0xfd000000" if (NOT_COHERENT_CACHE && 8xx)
default "0xff100000" if NOT_COHERENT_CACHE
config CONSISTENT_SIZE_BOOL
......@@ -662,3 +694,7 @@ config KEYS_COMPAT
default y
source "crypto/Kconfig"
config PPC_CLOCK
bool
default n
arch/powerpc/Kconfig.debug
View file @ e8690861
......@@ -124,6 +124,16 @@ config IRQSTACKS
for handling hard and soft interrupts. This can help avoid
overflowing the process kernel stacks.
config VIRQ_DEBUG
bool "Expose hardware/virtual IRQ mapping via debugfs"
depends on DEBUG_FS && PPC_MERGE
help
This option will show the mapping relationship between hardware irq
numbers and virtual irq numbers. The mapping is exposed via debugfs
in the file powerpc/virq_mapping.
If you don't know what this means you don't need it.
config BDI_SWITCH
bool "Include BDI-2000 user context switcher"
depends on DEBUG_KERNEL && PPC32
......@@ -211,6 +221,15 @@ config PPC_EARLY_DEBUG_44x
Select this to enable early debugging for IBM 44x chips via the
inbuilt serial port.
config PPC_EARLY_DEBUG_CPM
bool "Early serial debugging for Freescale CPM-based serial ports"
depends on SERIAL_CPM
select PIN_TLB if PPC_8xx
help
Select this to enable early debugging for Freescale chips
using a CPM-based serial port. This assumes that the bootwrapper
has run, and set up the CPM in a particular way.
endchoice
config PPC_EARLY_DEBUG_44x_PHYSLOW
......@@ -223,4 +242,16 @@ config PPC_EARLY_DEBUG_44x_PHYSHIGH
depends PPC_EARLY_DEBUG_44x
default "0x1"
config PPC_EARLY_DEBUG_CPM_ADDR
hex "CPM UART early debug transmit descriptor address"
depends on PPC_EARLY_DEBUG_CPM
default "0xfa202008" if PPC_EP88XC
default "0xf0000008" if CPM2
default "0xff002008" if CPM1
help
This specifies the address of the transmit descriptor
used for early debug output. Because it is needed before
platform probing is done, all platforms selected must
share the same address.
endmenu
arch/powerpc/Makefile
View file @ e8690861
......@@ -35,11 +35,14 @@ endif
export CROSS32CC CROSS32AS CROSS32LD CROSS32AR CROSS32OBJCOPY
ifeq ($(CROSS_COMPILE),)
KBUILD_DEFCONFIG := $(shell uname -m)_defconfig
else
KBUILD_DEFCONFIG := ppc64_defconfig
endif
ifeq ($(CONFIG_PPC64),y)
OLDARCH := ppc64
SZ := 64
new_nm := $(shell if $(NM) --help 2>&1 | grep -- '--synthetic' > /dev/null; then echo y; else echo n; fi)
......@@ -49,22 +52,26 @@ endif
else
OLDARCH := ppc
SZ := 32
endif
# It seems there are times we use this Makefile without
# including the config file, but this replicates the old behaviour
ifeq ($(CONFIG_WORD_SIZE),)
CONFIG_WORD_SIZE := 32
endif
UTS_MACHINE := $(OLDARCH)
ifeq ($(HAS_BIARCH),y)
override AS += -a$(SZ)
override LD += -m elf$(SZ)ppc
override CC += -m$(SZ)
override AR := GNUTARGET=elf$(SZ)-powerpc $(AR)
override AS += -a$(CONFIG_WORD_SIZE)
override LD += -m elf$(CONFIG_WORD_SIZE)ppc
override CC += -m$(CONFIG_WORD_SIZE)
override AR := GNUTARGET=elf$(CONFIG_WORD_SIZE)-powerpc $(AR)
endif
LDFLAGS_vmlinux := -Bstatic
# The -Iarch/$(ARCH)/include is temporary while we are merging
CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) -Iarch/$(ARCH)/include
CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH)
AFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH)
CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=none -mcall-aixdesc
CFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) -ffixed-r2 -mmultiple
......@@ -72,11 +79,8 @@ CPPFLAGS += $(CPPFLAGS-y)
AFLAGS += $(AFLAGS-y)
CFLAGS += -msoft-float -pipe $(CFLAGS-y)
CPP = $(CC) -E $(CFLAGS)
# Temporary hack until we have migrated to asm-powerpc
LINUXINCLUDE-$(CONFIG_PPC32) := -Iarch/$(ARCH)/include
LINUXINCLUDE += $(LINUXINCLUDE-y)
CHECKFLAGS += -m$(SZ) -D__powerpc__ -D__powerpc$(SZ)__
CHECKFLAGS += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__
ifeq ($(CONFIG_PPC64),y)
GCC_BROKEN_VEC := $(shell if [ $(call cc-version) -lt 0400 ] ; then echo "y"; fi)
......@@ -96,6 +100,10 @@ else
endif
endif
ifeq ($(CONFIG_TUNE_CELL),y)
CFLAGS += $(call cc-option,-mtune=cell)
endif
# No AltiVec instruction when building kernel
CFLAGS += $(call cc-option,-mno-altivec)
......@@ -120,10 +128,9 @@ cpu-as-$(CONFIG_E200) += -Wa,-me200
AFLAGS += $(cpu-as-y)
CFLAGS += $(cpu-as-y)
head-y := arch/powerpc/kernel/head_32.o
head-$(CONFIG_PPC64) := arch/powerpc/kernel/head_64.o
head-y := arch/powerpc/kernel/head_$(CONFIG_WORD_SIZE).o
head-$(CONFIG_8xx) := arch/powerpc/kernel/head_8xx.o
head-$(CONFIG_4xx) := arch/powerpc/kernel/head_4xx.o
head-$(CONFIG_40x) := arch/powerpc/kernel/head_40x.o
head-$(CONFIG_44x) := arch/powerpc/kernel/head_44x.o
head-$(CONFIG_FSL_BOOKE) := arch/powerpc/kernel/head_fsl_booke.o
......@@ -166,25 +173,20 @@ define archhelp
@echo ' *_defconfig - Select default config from arch/$(ARCH)/configs'
endef
install:
install: vdso_install
$(Q)$(MAKE) $(build)=$(boot) BOOTIMAGE=$(KBUILD_IMAGE) install
vdso_install:
ifeq ($(CONFIG_PPC64),y)
$(Q)$(MAKE) $(build)=arch/$(ARCH)/kernel/vdso64 $@
endif
$(Q)$(MAKE) $(build)=arch/$(ARCH)/kernel/vdso32 $@
archclean:
$(Q)$(MAKE) $(clean)=$(boot)
archmrproper:
$(Q)rm -rf arch/$(ARCH)/include
archprepare: checkbin
ifeq ($(CONFIG_PPC32),y)
# Temporary hack until we have migrated to asm-powerpc
include/asm: arch/$(ARCH)/include/asm
arch/$(ARCH)/include/asm: FORCE
$(Q)if [ ! -d arch/$(ARCH)/include ]; then mkdir -p arch/$(ARCH)/include; fi
$(Q)ln -fsn $(srctree)/include/asm-$(OLDARCH) arch/$(ARCH)/include/asm
endif
# Use the file '.tmp_gas_check' for binutils tests, as gas won't output
# to stdout and these checks are run even on install targets.
TOUT := .tmp_gas_check
......
arch/powerpc/boot/.gitignore
View file @ e8690861
......@@ -18,14 +18,15 @@ kernel-vmlinux.strip.c
kernel-vmlinux.strip.gz
mktree
uImage
cuImage
cuImage.bin.gz
cuImage.elf
cuImage.*
treeImage.*
zImage
zImage.bin.*
zImage.chrp
zImage.coff
zImage.coff.lds
zImage.lds
zImage.ep*
zImage.*lds
zImage.miboot
zImage.pmac
zImage.pseries
......
arch/powerpc/boot/44x.c deleted 100644 → 0
View file @ 54730742
/*
* Copyright 2007 David Gibson, IBM Corporation.
*
* Based on earlier code:
* Matt Porter <mporter@kernel.crashing.org>
* Copyright 2002-2005 MontaVista Software Inc.
*
* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
* Copyright (c) 2003, 2004 Zultys Technologies
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <stddef.h>
#include "types.h"
#include "string.h"
#include "stdio.h"
#include "ops.h"
#include "reg.h"
#include "dcr.h"
/* Read the 44x memory controller to get size of system memory. */
void ibm44x_fixup_memsize(void)
{
int i;
unsigned long memsize, bank_config;
memsize = 0;
for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
}
dt_fixup_memory(0, memsize);
}
#define SPRN_DBCR0 0x134
#define DBCR0_RST_SYSTEM 0x30000000
void ibm44x_dbcr_reset(void)
{
unsigned long tmp;
asm volatile (
"mfspr %0,%1\n"
"oris %0,%0,%2@h\n"
"mtspr %1,%0"
: "=&r"(tmp) : "i"(SPRN_DBCR0), "i"(DBCR0_RST_SYSTEM)
);
}
/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
* banks into the OPB address space */
void ibm4xx_fixup_ebc_ranges(const char *ebc)
{
void *devp;
u32 bxcr;
u32 ranges[EBC_NUM_BANKS*4];
u32 *p = ranges;
int i;
for (i = 0; i < EBC_NUM_BANKS; i++) {
mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
bxcr = mfdcr(DCRN_EBC0_CFGDATA);
if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
*p++ = i;
*p++ = 0;
*p++ = bxcr & EBC_BXCR_BAS;
*p++ = EBC_BXCR_BANK_SIZE(bxcr);
}
}
devp = finddevice(ebc);
if (! devp)
fatal("Couldn't locate EBC node %s\n\r", ebc);
setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
}
arch/powerpc/boot/44x.h
View file @ e8690861
......@@ -10,10 +10,7 @@
#ifndef _PPC_BOOT_44X_H_
#define _PPC_BOOT_44X_H_
void ibm44x_fixup_memsize(void);
void ibm4xx_fixup_ebc_ranges(const char *ebc);
void ibm44x_dbcr_reset(void);
void ebony_init(void *mac0, void *mac1);
void bamboo_init(void *mac0, void *mac1);
#endif /* _PPC_BOOT_44X_H_ */
arch/powerpc/boot/4xx.c 0 → 100644
View file @ e8690861
/*
* Copyright 2007 David Gibson, IBM Corporation.
*
* Based on earlier code:
* Matt Porter <mporter@kernel.crashing.org>
* Copyright 2002-2005 MontaVista Software Inc.
*
* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
* Copyright (c) 2003, 2004 Zultys Technologies
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <stddef.h>
#include "types.h"
#include "string.h"
#include "stdio.h"
#include "ops.h"
#include "reg.h"
#include "dcr.h"
/* Read the 4xx SDRAM controller to get size of system memory. */
void ibm4xx_fixup_memsize(void)
{
int i;
unsigned long memsize, bank_config;
memsize = 0;
for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
}
dt_fixup_memory(0, memsize);
}
/* 4xx DDR1/2 Denali memory controller support */
/* DDR0 registers */
#define DDR0_02 2
#define DDR0_08 8
#define DDR0_10 10
#define DDR0_14 14
#define DDR0_42 42
#define DDR0_43 43
/* DDR0_02 */
#define DDR_START 0x1
#define DDR_START_SHIFT 0
#define DDR_MAX_CS_REG 0x3
#define DDR_MAX_CS_REG_SHIFT 24
#define DDR_MAX_COL_REG 0xf
#define DDR_MAX_COL_REG_SHIFT 16
#define DDR_MAX_ROW_REG 0xf
#define DDR_MAX_ROW_REG_SHIFT 8
/* DDR0_08 */
#define DDR_DDR2_MODE 0x1
#define DDR_DDR2_MODE_SHIFT 0
/* DDR0_10 */
#define DDR_CS_MAP 0x3
#define DDR_CS_MAP_SHIFT 8
/* DDR0_14 */
#define DDR_REDUC 0x1
#define DDR_REDUC_SHIFT 16
/* DDR0_42 */
#define DDR_APIN 0x7
#define DDR_APIN_SHIFT 24
/* DDR0_43 */
#define DDR_COL_SZ 0x7
#define DDR_COL_SZ_SHIFT 8
#define DDR_BANK8 0x1
#define DDR_BANK8_SHIFT 0
#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
static inline u32 mfdcr_sdram0(u32 reg)
{
mtdcr(DCRN_SDRAM0_CFGADDR, reg);
return mfdcr(DCRN_SDRAM0_CFGDATA);
}
void ibm4xx_denali_fixup_memsize(void)
{
u32 val, max_cs, max_col, max_row;
u32 cs, col, row, bank, dpath;
unsigned long memsize;
val = mfdcr_sdram0(DDR0_02);
if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
fatal("DDR controller is not initialized\n");
/* get maximum cs col and row values */
max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT);
max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
/* get CS value */
val = mfdcr_sdram0(DDR0_10);
val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
cs = 0;
while (val) {
if (val && 0x1)
cs++;
val = val >> 1;
}
if (!cs)
fatal("No memory installed\n");
if (cs > max_cs)
fatal("DDR wrong CS configuration\n");
/* get data path bytes */
val = mfdcr_sdram0(DDR0_14);
if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
dpath = 8; /* 64 bits */
else
dpath = 4; /* 32 bits */
/* get adress pins (rows) */
val = mfdcr_sdram0(DDR0_42);
row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
if (row > max_row)
fatal("DDR wrong APIN configuration\n");
row = max_row - row;
/* get collomn size and banks */
val = mfdcr_sdram0(DDR0_43);
col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
if (col > max_col)
fatal("DDR wrong COL configuration\n");
col = max_col - col;
if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT))
bank = 8; /* 8 banks */
else
bank = 4; /* 4 banks */
memsize = cs * (1 << (col+row)) * bank * dpath;
dt_fixup_memory(0, memsize);
}
#define SPRN_DBCR0_40X 0x3F2
#define SPRN_DBCR0_44X 0x134
#define DBCR0_RST_SYSTEM 0x30000000
void ibm44x_dbcr_reset(void)
{
unsigned long tmp;
asm volatile (
"mfspr %0,%1\n"
"oris %0,%0,%2@h\n"
"mtspr %1,%0"
: "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM)
);
}
void ibm40x_dbcr_reset(void)
{
unsigned long tmp;
asm volatile (
"mfspr %0,%1\n"
"oris %0,%0,%2@h\n"
"mtspr %1,%0"
: "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)
);
}
#define EMAC_RESET 0x20000000
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
{
/* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us */
if (emac0)
*emac0 = EMAC_RESET;
if (emac1)
*emac1 = EMAC_RESET;
mtdcr(DCRN_MAL0_CFG, MAL_RESET);
}
/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
* banks into the OPB address space */
void ibm4xx_fixup_ebc_ranges(const char *ebc)
{
void *devp;
u32 bxcr;
u32 ranges[EBC_NUM_BANKS*4];
u32 *p = ranges;
int i;
for (i = 0; i < EBC_NUM_BANKS; i++) {
mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
bxcr = mfdcr(DCRN_EBC0_CFGDATA);
if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
*p++ = i;
*p++ = 0;
*p++ = bxcr & EBC_BXCR_BAS;
*p++ = EBC_BXCR_BANK_SIZE(bxcr);
}
}
devp = finddevice(ebc);
if (! devp)
fatal("Couldn't locate EBC node %s\n\r", ebc);
setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
}
#define SPRN_CCR1 0x378
void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
{
u32 cpu, plb, opb, ebc, tb, uart0, m, vco;
u32 reg;
u32 fwdva, fwdvb, fbdv, lfbdv, opbdv0, perdv0, spcid0, prbdv0, tmp;
mtdcr(DCRN_CPR0_ADDR, CPR0_PLLD0);
reg = mfdcr(DCRN_CPR0_DATA);
tmp = (reg & 0x000F0000) >> 16;
fwdva = tmp ? tmp : 16;
tmp = (reg & 0x00000700) >> 8;
fwdvb = tmp ? tmp : 8;
tmp = (reg & 0x1F000000) >> 24;
fbdv = tmp ? tmp : 32;
lfbdv = (reg & 0x0000007F);
mtdcr(DCRN_CPR0_ADDR, CPR0_OPBD0);
reg = mfdcr(DCRN_CPR0_DATA);
tmp = (reg & 0x03000000) >> 24;
opbdv0 = tmp ? tmp : 4;
mtdcr(DCRN_CPR0_ADDR, CPR0_PERD0);
reg = mfdcr(DCRN_CPR0_DATA);
tmp = (reg & 0x07000000) >> 24;
perdv0 = tmp ? tmp : 8;
mtdcr(DCRN_CPR0_ADDR, CPR0_PRIMBD0);
reg = mfdcr(DCRN_CPR0_DATA);
tmp = (reg & 0x07000000) >> 24;
prbdv0 = tmp ? tmp : 8;
mtdcr(DCRN_CPR0_ADDR, CPR0_SCPID);
reg = mfdcr(DCRN_CPR0_DATA);
tmp = (reg & 0x03000000) >> 24;
spcid0 = tmp ? tmp : 4;
/* Calculate M */
mtdcr(DCRN_CPR0_ADDR, CPR0_PLLC0);
reg = mfdcr(DCRN_CPR0_DATA);
tmp = (reg & 0x03000000) >> 24;
if (tmp == 0) { /* PLL output */
tmp = (reg & 0x20000000) >> 29;
if (!tmp) /* PLLOUTA */
m = fbdv * lfbdv * fwdva;
else
m = fbdv * lfbdv * fwdvb;
}
else if (tmp == 1) /* CPU output */
m = fbdv * fwdva;
else
m = perdv0 * opbdv0 * fwdvb;
vco = (m * sysclk) + (m >> 1);
cpu = vco / fwdva;
plb = vco / fwdvb / prbdv0;
opb = plb / opbdv0;
ebc = plb / perdv0;
/* FIXME */
uart0 = ser_clk;
/* Figure out timebase. Either CPU or default TmrClk */
asm volatile (
"mfspr %0,%1\n"
:
"=&r"(reg) : "i"(SPRN_CCR1));
if (reg & 0x0080)
tb = 25000000; /* TmrClk is 25MHz */
else
tb = cpu;
dt_fixup_cpu_clocks(cpu, tb, 0);
dt_fixup_clock("/plb", plb);
dt_fixup_clock("/plb/opb", opb);
dt_fixup_clock("/plb/opb/ebc", ebc);
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
dt_fixup_clock("/plb/opb/serial@ef600400", uart0);
dt_fixup_clock("/plb/opb/serial@ef600500", uart0);
dt_fixup_clock("/plb/opb/serial@ef600600", uart0);
}
arch/powerpc/boot/4xx.h 0 → 100644
View file @ e8690861
/*
* PowerPC 4xx related functions
*
* Copyright 2007 IBM Corporation.
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef _POWERPC_BOOT_4XX_H_
#define _POWERPC_BOOT_4XX_H_
void ibm4xx_fixup_memsize(void);
void ibm4xx_denali_fixup_memsize(void);
void ibm44x_dbcr_reset(void);
void ibm40x_dbcr_reset(void);
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1);
void ibm4xx_fixup_ebc_ranges(const char *ebc);
void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk);
#endif /* _POWERPC_BOOT_4XX_H_ */
arch/powerpc/boot/Makefile
View file @ e8690861
......@@ -25,14 +25,19 @@ BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
-isystem $(shell $(CROSS32CC) -print-file-name=include)
BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
ifdef CONFIG_DEBUG_INFO
BOOTCFLAGS += -g
endif
ifeq ($(call cc-option-yn, -fstack-protector),y)
BOOTCFLAGS += -fno-stack-protector
endif
BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj)
$(obj)/44x.o: BOOTCFLAGS += -mcpu=440
$(obj)/4xx.o: BOOTCFLAGS += -mcpu=440
$(obj)/ebony.o: BOOTCFLAGS += -mcpu=440
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
zlib := inffast.c inflate.c inftrees.c
zlibheader := inffast.h inffixed.h inflate.h inftrees.h infutil.h
......@@ -44,10 +49,14 @@ $(addprefix $(obj)/,$(zlib) gunzip_util.o main.o): \
src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
ns16550.c serial.c simple_alloc.c div64.S util.S \
gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \
44x.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c
src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \
4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \
cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
fsl-soc.c mpc8xx.c pq2.c
src-plat := of.c cuboot-52xx.c cuboot-83xx.c cuboot-85xx.c holly.c \
cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
ps3-head.S ps3-hvcall.S ps3.c
ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c \
fixed-head.S ep88xc.c cuboot-hpc2.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
......@@ -139,9 +148,17 @@ image-$(CONFIG_PPC_ISERIES) += zImage.iseries
image-$(CONFIG_DEFAULT_UIMAGE) += uImage
ifneq ($(CONFIG_DEVICE_TREE),"")
image-$(CONFIG_PPC_8xx) += cuImage.8xx
image-$(CONFIG_PPC_EP88XC) += zImage.ep88xc
image-$(CONFIG_8260) += cuImage.pq2
image-$(CONFIG_PPC_MPC52xx) += cuImage.52xx
image-$(CONFIG_PPC_83xx) += cuImage.83xx
image-$(CONFIG_PPC_85xx) += cuImage.85xx
image-$(CONFIG_MPC7448HPC2) += cuImage.hpc2
image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo
image-$(CONFIG_SEQUOIA) += cuImage.sequoia
image-$(CONFIG_WALNUT) += treeImage.walnut
endif
# For 32-bit powermacs, build the COFF and miboot images
......
arch/powerpc/boot/bamboo.c 0 → 100644
View file @ e8690861
/*
* Copyright IBM Corporation, 2007
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
*
* Based on ebony wrapper:
* Copyright 2007 David Gibson, IBM Corporation.
*
* Clocking code based on code by:
* Stefan Roese <sr@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2 of the License
*/
#include <stdarg.h>
#include <stddef.h>
#include "types.h"
#include "elf.h"
#include "string.h"
#include "stdio.h"
#include "page.h"
#include "ops.h"
#include "dcr.h"
#include "4xx.h"
#include "44x.h"
static u8 *bamboo_mac0, *bamboo_mac1;
static void bamboo_fixups(void)
{
unsigned long sysclk = 33333333;
ibm440ep_fixup_clocks(sysclk, 11059200);
ibm4xx_fixup_memsize();
ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1);
}
void bamboo_init(void *mac0, void *mac1)
{
platform_ops.fixups = bamboo_fixups;
platform_ops.exit = ibm44x_dbcr_reset;
bamboo_mac0 = mac0;
bamboo_mac1 = mac1;
ft_init(_dtb_start, 0, 32);
serial_console_init();
}
arch/powerpc/boot/cpm-serial.c 0 → 100644
View file @ e8690861
/*
* CPM serial console support.
*
* Copyright 2007 Freescale Semiconductor, Inc.
* Author: Scott Wood <scottwood@freescale.com>
*
* It is assumed that the firmware (or the platform file) has already set
* up the port.
*/
#include "types.h"
#include "io.h"
#include "ops.h"
struct cpm_scc {
u32 gsmrl;
u32 gsmrh;
u16 psmr;
u8 res1[2];
u16 todr;
u16 dsr;
u16 scce;
u8 res2[2];
u16 sccm;
u8 res3;
u8 sccs;
u8 res4[8];
};
struct cpm_smc {
u8 res1[2];
u16 smcmr;
u8 res2[2];
u8 smce;
u8 res3[3];
u8 smcm;
u8 res4[5];
};
struct cpm_param {
u16 rbase;
u16 tbase;
u8 rfcr;
u8 tfcr;
};
struct cpm_bd {
u16 sc; /* Status and Control */
u16 len; /* Data length in buffer */
u8 *addr; /* Buffer address in host memory */
};
static void *cpcr;
static struct cpm_param *param;
static struct cpm_smc *smc;
static struct cpm_scc *scc;
struct cpm_bd *tbdf, *rbdf;
static u32 cpm_cmd;
static u8 *muram_start;
static u32 muram_offset;
static void (*do_cmd)(int op);
static void (*enable_port)(void);
static void (*disable_port)(void);
#define CPM_CMD_STOP_TX 4
#define CPM_CMD_RESTART_TX 6
#define CPM_CMD_INIT_RX_TX 0
static void cpm1_cmd(int op)
{
while (in_be16(cpcr) & 1)
;
out_be16(cpcr, (op << 8) | cpm_cmd | 1);
while (in_be16(cpcr) & 1)
;
}
static void cpm2_cmd(int op)
{
while (in_be32(cpcr) & 0x10000)
;
out_be32(cpcr, op | cpm_cmd | 0x10000);
while (in_be32(cpcr) & 0x10000)
;
}
static void smc_disable_port(void)
{
do_cmd(CPM_CMD_STOP_TX);
out_be16(&smc->smcmr, in_be16(&smc->smcmr) & ~3);
}
static void scc_disable_port(void)
{
do_cmd(CPM_CMD_STOP_TX);
out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) & ~0x30);
}
static void smc_enable_port(void)
{
out_be16(&smc->smcmr, in_be16(&smc->smcmr) | 3);
do_cmd(CPM_CMD_RESTART_TX);
}
static void scc_enable_port(void)
{
out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) | 0x30);
do_cmd(CPM_CMD_RESTART_TX);
}
static int cpm_serial_open(void)
{
disable_port();
out_8(&param->rfcr, 0x10);
out_8(&param->tfcr, 0x10);
rbdf = (struct cpm_bd *)muram_start;
rbdf->addr = (u8 *)(rbdf + 2);
rbdf->sc = 0xa000;
rbdf->len = 1;
tbdf = rbdf + 1;
tbdf->addr = (u8 *)(rbdf + 2) + 1;
tbdf->sc = 0x2000;
tbdf->len = 1;
sync();
out_be16(&param->rbase, muram_offset);
out_be16(&param->tbase, muram_offset + sizeof(struct cpm_bd));
do_cmd(CPM_CMD_INIT_RX_TX);
enable_port();
return 0;
}
static void cpm_serial_putc(unsigned char c)
{
while (tbdf->sc & 0x8000)
barrier();
sync();
tbdf->addr[0] = c;
eieio();
tbdf->sc |= 0x8000;
}
static unsigned char cpm_serial_tstc(void)
{
barrier();
return !(rbdf->sc & 0x8000);
}
static unsigned char cpm_serial_getc(void)
{
unsigned char c;
while (!cpm_serial_tstc())
;
sync();
c = rbdf->addr[0];
eieio();
rbdf->sc |= 0x8000;
return c;
}
int cpm_console_init(void *devp, struct serial_console_data *scdp)
{
void *reg_virt[2];
int is_smc = 0, is_cpm2 = 0, n;
unsigned long reg_phys;
void *parent, *muram;
if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) {
is_smc = 1;
} else if (dt_is_compatible(devp, "fsl,cpm2-scc-uart")) {
is_cpm2 = 1;
} else if (dt_is_compatible(devp, "fsl,cpm2-smc-uart")) {
is_cpm2 = 1;
is_smc = 1;
}
if (is_smc) {
enable_port = smc_enable_port;
disable_port = smc_disable_port;
} else {
enable_port = scc_enable_port;
disable_port = scc_disable_port;
}
if (is_cpm2)
do_cmd = cpm2_cmd;
else
do_cmd = cpm1_cmd;
n = getprop(devp, "fsl,cpm-command", &cpm_cmd, 4);
if (n < 4)
return -1;
n = getprop(devp, "virtual-reg", reg_virt, sizeof(reg_virt));
if (n < (int)sizeof(reg_virt)) {
for (n = 0; n < 2; n++) {
if (!dt_xlate_reg(devp, n, &reg_phys, NULL))
return -1;
reg_virt[n] = (void *)reg_phys;
}
}
if (is_smc)
smc = reg_virt[0];
else
scc = reg_virt[0];
param = reg_virt[1];
parent = get_parent(devp);
if (!parent)
return -1;
n = getprop(parent, "virtual-reg", reg_virt, sizeof(reg_virt));
if (n < (int)sizeof(reg_virt)) {
if (!dt_xlate_reg(parent, 0, &reg_phys, NULL))
return -1;
reg_virt[0] = (void *)reg_phys;
}
cpcr = reg_virt[0];
muram = finddevice("/soc/cpm/muram/data");
if (!muram)
return -1;
/* For bootwrapper-compatible device trees, we assume that the first
* entry has at least 18 bytes, and that #address-cells/#data-cells
* is one for both parent and child.
*/
n = getprop(muram, "virtual-reg", reg_virt, sizeof(reg_virt));
if (n < (int)sizeof(reg_virt)) {
if (!dt_xlate_reg(muram, 0, &reg_phys, NULL))
return -1;
reg_virt[0] = (void *)reg_phys;
}
muram_start = reg_virt[0];
n = getprop(muram, "reg", &muram_offset, 4);
if (n < 4)
return -1;
scdp->open = cpm_serial_open;
scdp->putc = cpm_serial_putc;
scdp->getc = cpm_serial_getc;
scdp->tstc = cpm_serial_tstc;
return 0;
}
arch/powerpc/boot/cuboot-52xx.c 0 → 100644
View file @ e8690861
/*
* Old U-boot compatibility for MPC5200
*
* Author: Grant Likely <grant.likely@secretlab.ca>
*
* Copyright (c) 2007 Secret Lab Technologies Ltd.
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "stdio.h"
#include "io.h"
#include "cuboot.h"
#define TARGET_PPC_MPC52xx
#include "ppcboot.h"
static bd_t bd;
static void platform_fixups(void)
{
void *soc, *reg;
int div;
u32 sysfreq;
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
dt_fixup_mac_addresses(bd.bi_enetaddr);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
/* Unfortunately, the specific model number is encoded in the
* soc node name in existing dts files -- once that is fixed,
* this can do a simple path lookup.
*/
soc = find_node_by_devtype(NULL, "soc");
if (soc) {
setprop(soc, "bus-frequency", &bd.bi_ipbfreq,
sizeof(bd.bi_ipbfreq));
if (!dt_xlate_reg(soc, 0, (void*)&reg, NULL))
return;
div = in_8(reg + 0x204) & 0x0020 ? 8 : 4;
sysfreq = bd.bi_busfreq * div;
setprop(soc, "system-frequency", &sysfreq, sizeof(sysfreq));
}
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
serial_console_init();
platform_ops.fixups = platform_fixups;
}
arch/powerpc/boot/cuboot-83xx.c
View file @ e8690861
......@@ -18,7 +18,6 @@
#include "ppcboot.h"
static bd_t bd;
extern char _dtb_start[], _dtb_end[];
static void platform_fixups(void)
{
......
arch/powerpc/boot/cuboot-85xx.c
View file @ e8690861
......@@ -18,7 +18,6 @@
#include "ppcboot.h"
static bd_t bd;
extern char _dtb_start[], _dtb_end[];
static void platform_fixups(void)
{
......
arch/powerpc/boot/cuboot-8xx.c 0 → 100644
View file @ e8690861
/*
* Old U-boot compatibility for 8xx
*
* Author: Scott Wood <scottwood@freescale.com>
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "stdio.h"
#include "cuboot.h"
#define TARGET_8xx
#define TARGET_HAS_ETH1
#include "ppcboot.h"
static bd_t bd;
static void platform_fixups(void)
{
void *node;
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 16, bd.bi_busfreq);
node = finddevice("/soc/cpm");
if (node)
setprop(node, "clock-frequency", &bd.bi_busfreq, 4);
node = finddevice("/soc/cpm/brg");
if (node)
setprop(node, "clock-frequency", &bd.bi_busfreq, 4);
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
serial_console_init();
platform_ops.fixups = platform_fixups;
}
arch/powerpc/boot/cuboot-bamboo.c 0 → 100644
View file @ e8690861
/*
* Old U-boot compatibility for Bamboo
*
* Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
*
* Copyright 2007 IBM Corporation
*
* Based on cuboot-ebony.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "stdio.h"
#include "44x.h"
#include "cuboot.h"
#define TARGET_44x
#include "ppcboot.h"
static bd_t bd;
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
bamboo_init(&bd.bi_enetaddr, &bd.bi_enet1addr);
}
arch/powerpc/boot/cuboot-hpc2.c 0 → 100644
View file @ e8690861
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
*
* Author: Roy Zang <tie-fei.zang@freescale.com>
*
* Description:
* Old U-boot compatibility for mpc7448hpc2 board
* Based on the code of Scott Wood <scottwood@freescale.com>
* for 83xx and 85xx.
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include "ops.h"
#include "stdio.h"
#include "cuboot.h"
#define TARGET_HAS_ETH1
#include "ppcboot.h"
static bd_t bd;
extern char _dtb_start[], _dtb_end[];
static void platform_fixups(void)
{
void *tsi;
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
tsi = find_node_by_devtype(NULL, "tsi-bridge");
if (tsi)
setprop(tsi, "bus-frequency", &bd.bi_busfreq,
sizeof(bd.bi_busfreq));
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
serial_console_init();
platform_ops.fixups = platform_fixups;
}
arch/powerpc/boot/cuboot-pq2.c 0 → 100644
View file @ e8690861
/*
* Old U-boot compatibility for PowerQUICC II
* (a.k.a. 82xx with CPM, not the 8240 family of chips)
*
* Author: Scott Wood <scottwood@freescale.com>
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "stdio.h"
#include "cuboot.h"
#include "io.h"
#include "fsl-soc.h"
#define TARGET_CPM2
#define TARGET_HAS_ETH1
#include "ppcboot.h"
static bd_t bd;
struct cs_range {
u32 csnum;
u32 base; /* must be zero */
u32 addr;
u32 size;
};
struct pci_range {
u32 flags;
u32 pci_addr[2];
u32 phys_addr;
u32 size[2];
};
struct cs_range cs_ranges_buf[MAX_PROP_LEN / sizeof(struct cs_range)];
struct pci_range pci_ranges_buf[MAX_PROP_LEN / sizeof(struct pci_range)];
/* Different versions of u-boot put the BCSR in different places, and
* some don't set up the PCI PIC at all, so we assume the device tree is
* sane and update the BRx registers appropriately.
*
* For any node defined as compatible with fsl,pq2-localbus,
* #address/#size must be 2/1 for the localbus, and 1/1 for the parent bus.
* Ranges must be for whole chip selects.
*/
static void update_cs_ranges(void)
{
void *bus_node, *parent_node;
u32 *ctrl_addr;
unsigned long ctrl_size;
u32 naddr, nsize;
int len;
int i;
bus_node = finddevice("/localbus");
if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus"))
return;
dt_get_reg_format(bus_node, &naddr, &nsize);
if (naddr != 2 || nsize != 1)
goto err;
parent_node = get_parent(bus_node);
if (!parent_node)
goto err;
dt_get_reg_format(parent_node, &naddr, &nsize);
if (naddr != 1 || nsize != 1)
goto err;
if (!dt_xlate_reg(bus_node, 0, (unsigned long *)&ctrl_addr,
&ctrl_size))
goto err;
len = getprop(bus_node, "ranges", cs_ranges_buf, sizeof(cs_ranges_buf));
for (i = 0; i < len / sizeof(struct cs_range); i++) {
u32 base, option;
int cs = cs_ranges_buf[i].csnum;
if (cs >= ctrl_size / 8)
goto err;
if (cs_ranges_buf[i].base != 0)
goto err;
base = in_be32(&ctrl_addr[cs * 2]);
/* If CS is already valid, use the existing flags.
* Otherwise, guess a sane default.
*/
if (base & 1) {
base &= 0x7fff;
option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff;
} else {
base = 0x1801;
option = 0x10;
}
out_be32(&ctrl_addr[cs * 2], 0);
out_be32(&ctrl_addr[cs * 2 + 1],
option | ~(cs_ranges_buf[i].size - 1));
out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr);
}
return;
err:
printf("Bad /localbus node\r\n");
}
/* Older u-boots don't set PCI up properly. Update the hardware to match
* the device tree. The prefetch mem region and non-prefetch mem region
* must be contiguous in the host bus. As required by the PCI binding,
* PCI #addr/#size must be 3/2. The parent bus must be 1/1. Only
* 32-bit PCI is supported. All three region types (prefetchable mem,
* non-prefetchable mem, and I/O) must be present.
*/
static void fixup_pci(void)
{
struct pci_range *mem = NULL, *mmio = NULL,
*io = NULL, *mem_base = NULL;
u32 *pci_regs[3];
u8 *soc_regs;
int i, len;
void *node, *parent_node;
u32 naddr, nsize, mem_log2;
node = finddevice("/pci");
if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
return;
for (i = 0; i < 3; i++)
if (!dt_xlate_reg(node, i,
(unsigned long *)&pci_regs[i], NULL))
goto err;
soc_regs = (u8 *)fsl_get_immr();
if (!soc_regs)
goto err;
dt_get_reg_format(node, &naddr, &nsize);
if (naddr != 3 || nsize != 2)
goto err;
parent_node = get_parent(node);
if (!parent_node)
goto err;
dt_get_reg_format(parent_node, &naddr, &nsize);
if (naddr != 1 || nsize != 1)
goto err;
len = getprop(node, "ranges", pci_ranges_buf,
sizeof(pci_ranges_buf));
for (i = 0; i < len / sizeof(struct pci_range); i++) {
u32 flags = pci_ranges_buf[i].flags & 0x43000000;
if (flags == 0x42000000)
mem = &pci_ranges_buf[i];
else if (flags == 0x02000000)
mmio = &pci_ranges_buf[i];
else if (flags == 0x01000000)
io = &pci_ranges_buf[i];
}
if (!mem || !mmio || !io)
goto err;
if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
mem_base = mem;
else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
mem_base = mmio;
else
goto err;
out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
out_be32(&pci_regs[1][1], io->phys_addr | 1);
out_be32(&pci_regs[2][1], ~(io->size[1] - 1));
out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12);
out_le32(&pci_regs[0][2], mem->phys_addr >> 12);
out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000);
out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12);
out_le32(&pci_regs[0][8], mmio->phys_addr >> 12);
out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000);
out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12);
out_le32(&pci_regs[0][14], io->phys_addr >> 12);
out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000);
/* Inbound translation */
out_le32(&pci_regs[0][58], 0);
out_le32(&pci_regs[0][60], 0);
mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1));
/* If PCI is disabled, drive RST high to enable. */
if (!(in_le32(&pci_regs[0][32]) & 1)) {
/* Tpvrh (Power valid to RST# high) 100 ms */
udelay(100000);
out_le32(&pci_regs[0][32], 1);
/* Trhfa (RST# high to first cfg access) 2^25 clocks */
udelay(1020000);
}
/* Enable bus master and memory access */
out_le32(&pci_regs[0][64], 0x80000004);
out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6);
/* Park the bus on PCI, and elevate PCI's arbitration priority,
* as required by section 9.6 of the user's manual.
*/
out_8(&soc_regs[0x10028], 3);
out_be32((u32 *)&soc_regs[0x1002c], 0x01236745);
return;
err:
printf("Bad PCI node\r\n");
}
static void pq2_platform_fixups(void)
{
void *node;
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
node = finddevice("/soc/cpm");
if (node)
setprop(node, "clock-frequency", &bd.bi_cpmfreq, 4);
node = finddevice("/soc/cpm/brg");
if (node)
setprop(node, "clock-frequency", &bd.bi_brgfreq, 4);
update_cs_ranges();
fixup_pci();
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
serial_console_init();
platform_ops.fixups = pq2_platform_fixups;
}
arch/powerpc/boot/cuboot-sequoia.c 0 → 100644
View file @ e8690861
/*
* Old U-boot compatibility for Sequoia
*
* Valentine Barshak <vbarshak@ru.mvista.com>
* Copyright 2007 MontaVista Software, Inc
*
* Based on Ebony code by David Gibson <david@gibson.dropbear.id.au>
* Copyright IBM Corporation, 2007
*
* Based on Bamboo code by Josh Boyer <jwboyer@linux.vnet.ibm.com>
* Copyright IBM Corporation, 2007
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2 of the License
*/
#include <stdarg.h>
#include <stddef.h>
#include "types.h"
#include "elf.h"
#include "string.h"
#include "stdio.h"
#include "page.h"
#include "ops.h"
#include "dcr.h"
#include "4xx.h"
#include "44x.h"
#include "cuboot.h"
#define TARGET_4xx
#define TARGET_44x
#include "ppcboot.h"
static bd_t bd;
static void sequoia_fixups(void)
{
unsigned long sysclk = 33333333;
ibm440ep_fixup_clocks(sysclk, 11059200);
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
ibm4xx_denali_fixup_memsize();
dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
platform_ops.fixups = sequoia_fixups;
platform_ops.exit = ibm44x_dbcr_reset;
ft_init(_dtb_start, 0, 32);
serial_console_init();
}
arch/powerpc/boot/cuboot.c
View file @ e8690861
......@@ -17,9 +17,6 @@
#include "ppcboot.h"
extern char _end[];
extern char _dtb_start[], _dtb_end[];
void cuboot_init(unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7,
unsigned long end_of_ram)
......
arch/powerpc/boot/dcr.h
View file @ e8690861
......@@ -121,4 +121,22 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2C
#define DCRN_CPC0_MIRQ1 0x0ed
#define DCRN_CPC0_JTAGID 0x0ef
#define DCRN_MAL0_CFG 0x180
#define MAL_RESET 0x80000000
/* 440EP Clock/Power-on Reset regs */
#define DCRN_CPR0_ADDR 0xc
#define DCRN_CPR0_DATA 0xd
#define CPR0_PLLD0 0x60
#define CPR0_OPBD0 0xc0
#define CPR0_PERD0 0xe0
#define CPR0_PRIMBD0 0xa0
#define CPR0_SCPID 0x120
#define CPR0_PLLC0 0x40
/* 405GP Clocking/Power Management/Chip Control regs */
#define DCRN_CPC0_PLLMR 0xb0
#define DCRN_405_CPC0_CR0 0xb1
#define DCRN_405_CPC0_CR1 0xb2
#endif /* _PPC_BOOT_DCR_H_ */
arch/powerpc/boot/devtree.c
View file @ e8690861
......@@ -74,6 +74,8 @@ void dt_fixup_cpu_clocks(u32 cpu, u32 tb, u32 bus)
if (bus > 0)
setprop_val(devp, "bus-frequency", bus);
}
timebase_period_ns = 1000000000 / tb;
}
void dt_fixup_clock(const char *path, u32 freq)
......@@ -86,34 +88,38 @@ void dt_fixup_clock(const char *path, u32 freq)
}
}
void dt_fixup_mac_address(u32 index, const u8 *addr)
{
void *devp = find_node_by_prop_value(NULL, "linux,network-index",
(void*)&index, sizeof(index));
if (devp) {
printf("ENET%d: local-mac-address <-"
" %02x:%02x:%02x:%02x:%02x:%02x\n\r", index,
addr[0], addr[1], addr[2],
addr[3], addr[4], addr[5]);
setprop(devp, "local-mac-address", addr, 6);
}
}
void __dt_fixup_mac_addresses(u32 startindex, ...)
{
va_list ap;
u32 index = startindex;
void *devp;
const u8 *addr;
va_start(ap, startindex);
while ((addr = va_arg(ap, const u8 *))) {
devp = find_node_by_prop_value(NULL, "linux,network-index",
(void*)&index, sizeof(index));
printf("ENET%d: local-mac-address <-"
" %02x:%02x:%02x:%02x:%02x:%02x\n\r", index,
addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
if (devp)
setprop(devp, "local-mac-address", addr, 6);
while ((addr = va_arg(ap, const u8 *)))
dt_fixup_mac_address(index++, addr);
index++;
}
va_end(ap);
}
#define MAX_ADDR_CELLS 4
#define MAX_RANGES 8
static void get_reg_format(void *node, u32 *naddr, u32 *nsize)
void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize)
{
if (getprop(node, "#address-cells", naddr, 4) != 4)
*naddr = 2;
......@@ -207,7 +213,7 @@ static int find_range(u32 *reg, u32 *ranges, int nregaddr,
* In particular, PCI is not supported. Also, only the beginning of the
* reg block is tracked; size is ignored except in ranges.
*/
static u32 dt_xlate_buf[MAX_ADDR_CELLS * MAX_RANGES * 3];
static u32 prop_buf[MAX_PROP_LEN / 4];
static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
unsigned long *size)
......@@ -216,14 +222,14 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
u32 this_addr[MAX_ADDR_CELLS];
void *parent;
u64 ret_addr, ret_size;
u32 naddr, nsize, prev_naddr;
u32 naddr, nsize, prev_naddr, prev_nsize;
int buflen, offset;
parent = get_parent(node);
if (!parent)
return 0;
get_reg_format(parent, &naddr, &nsize);
dt_get_reg_format(parent, &naddr, &nsize);
if (nsize > 2)
return 0;
......@@ -231,41 +237,47 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
offset = (naddr + nsize) * res;
if (reglen < offset + naddr + nsize ||
sizeof(dt_xlate_buf) < offset + naddr + nsize)
MAX_PROP_LEN < (offset + naddr + nsize) * 4)
return 0;
copy_val(last_addr, dt_xlate_buf + offset, naddr);
copy_val(last_addr, prop_buf + offset, naddr);
ret_size = dt_xlate_buf[offset + naddr];
ret_size = prop_buf[offset + naddr];
if (nsize == 2) {
ret_size <<= 32;
ret_size |= dt_xlate_buf[offset + naddr + 1];
ret_size |= prop_buf[offset + naddr + 1];
}
while ((node = get_parent(node))) {
for (;;) {
prev_naddr = naddr;
prev_nsize = nsize;
node = parent;
parent = get_parent(node);
if (!parent)
break;
get_reg_format(node, &naddr, &nsize);
dt_get_reg_format(parent, &naddr, &nsize);
buflen = getprop(node, "ranges", dt_xlate_buf,
sizeof(dt_xlate_buf));
if (buflen < 0)
buflen = getprop(node, "ranges", prop_buf,
sizeof(prop_buf));
if (buflen == 0)
continue;
if (buflen > sizeof(dt_xlate_buf))
if (buflen < 0 || buflen > sizeof(prop_buf))
return 0;
offset = find_range(last_addr, dt_xlate_buf, prev_naddr,
naddr, nsize, buflen / 4);
offset = find_range(last_addr, prop_buf, prev_naddr,
naddr, prev_nsize, buflen / 4);
if (offset < 0)
return 0;
copy_val(this_addr, dt_xlate_buf + offset, prev_naddr);
copy_val(this_addr, prop_buf + offset, prev_naddr);
if (!sub_reg(last_addr, this_addr))
return 0;
copy_val(this_addr, dt_xlate_buf + offset + prev_naddr, naddr);
copy_val(this_addr, prop_buf + offset + prev_naddr, naddr);
if (!add_reg(last_addr, this_addr, naddr))
return 0;
......@@ -292,16 +304,35 @@ int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size)
{
int reglen;
reglen = getprop(node, "reg", dt_xlate_buf, sizeof(dt_xlate_buf)) / 4;
reglen = getprop(node, "reg", prop_buf, sizeof(prop_buf)) / 4;
return dt_xlate(node, res, reglen, addr, size);
}
int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr)
{
if (buflen > sizeof(dt_xlate_buf))
if (buflen > sizeof(prop_buf))
return 0;
memcpy(dt_xlate_buf, buf, buflen);
memcpy(prop_buf, buf, buflen);
return dt_xlate(node, 0, buflen / 4, xlated_addr, NULL);
}
int dt_is_compatible(void *node, const char *compat)
{
char *buf = (char *)prop_buf;
int len, pos;
len = getprop(node, "compatible", buf, MAX_PROP_LEN);
if (len < 0)
return 0;
for (pos = 0; pos < len; pos++) {
if (!strcmp(buf + pos, compat))
return 1;
pos += strnlen(&buf[pos], len - pos);
}
return 0;
}
arch/powerpc/boot/dts/bamboo.dts 0 → 100644
View file @ e8690861
/*
* Device Tree Source for AMCC Bamboo
*
* Copyright (c) 2006, 2007 IBM Corp.
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
*
* FIXME: Draft only!
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
/ {
#address-cells = <2>;
#size-cells = <1>;
model = "amcc,bamboo";
compatible = "amcc,bamboo";
dcr-parent = <&/cpus/PowerPC,440EP@0>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,440EP@0 {
device_type = "cpu";
reg = <0>;
clock-frequency = <0>; /* Filled in by zImage */
timebase-frequency = <0>; /* Filled in by zImage */
i-cache-line-size = <20>;
d-cache-line-size = <20>;
i-cache-size = <8000>;
d-cache-size = <8000>;
dcr-controller;
dcr-access-method = "native";
};
};
memory {
device_type = "memory";
reg = <0 0 0>; /* Filled in by zImage */
};
UIC0: interrupt-controller0 {
compatible = "ibm,uic-440ep","ibm,uic";
interrupt-controller;
cell-index = <0>;
dcr-reg = <0c0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
};
UIC1: interrupt-controller1 {
compatible = "ibm,uic-440ep","ibm,uic";
interrupt-controller;
cell-index = <1>;
dcr-reg = <0d0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <1e 4 1f 4>; /* cascade */
interrupt-parent = <&UIC0>;
};
SDR0: sdr {
compatible = "ibm,sdr-440ep";
dcr-reg = <00e 002>;
};
CPR0: cpr {
compatible = "ibm,cpr-440ep";
dcr-reg = <00c 002>;
};
plb {
compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
#address-cells = <2>;
#size-cells = <1>;
ranges;
clock-frequency = <0>; /* Filled in by zImage */
SDRAM0: sdram {
compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
dcr-reg = <010 2>;
};
DMA0: dma {
compatible = "ibm,dma-440ep", "ibm,dma-440gp";
dcr-reg = <100 027>;
};
MAL0: mcmal {
compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
dcr-reg = <180 62>;
num-tx-chans = <4>;
num-rx-chans = <2>;
interrupt-parent = <&MAL0>;
interrupts = <0 1 2 3 4>;
#interrupt-cells = <1>;
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
/*RXEOB*/ 1 &UIC0 b 4
/*SERR*/ 2 &UIC1 0 4
/*TXDE*/ 3 &UIC1 1 4
/*RXDE*/ 4 &UIC1 3 4>;
};
POB0: opb {
compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
/* Bamboo is oddball in the 44x world and doesn't use the ERPN
* bits.
*/
ranges = <00000000 0 00000000 80000000
80000000 0 80000000 80000000>;
interrupt-parent = <&UIC1>;
interrupts = <7 4>;
clock-frequency = <0>; /* Filled in by zImage */
EBC0: ebc {
compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
dcr-reg = <012 2>;
#address-cells = <2>;
#size-cells = <1>;
clock-frequency = <0>; /* Filled in by zImage */
ranges;
interrupts = <5 1>;
interrupt-parent = <&UIC1>;
};
UART0: serial@ef600300 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600300 8>;
virtual-reg = <ef600300>;
clock-frequency = <0>; /* Filled in by zImage */
current-speed = <1c200>;
interrupt-parent = <&UIC0>;
interrupts = <0 4>;
};
UART1: serial@ef600400 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600400 8>;
virtual-reg = <ef600400>;
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <1 4>;
};
UART2: serial@ef600500 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600500 8>;
virtual-reg = <ef600500>;
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <3 4>;
};
UART3: serial@ef600600 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600600 8>;
virtual-reg = <ef600600>;
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <4 4>;
};
IIC0: i2c@ef600700 {
device_type = "i2c";
compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
reg = <ef600700 14>;
interrupt-parent = <&UIC0>;
interrupts = <2 4>;
};
IIC1: i2c@ef600800 {
device_type = "i2c";
compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
reg = <ef600800 14>;
interrupt-parent = <&UIC0>;
interrupts = <7 4>;
};
ZMII0: emac-zmii@ef600d00 {
device_type = "zmii-interface";
compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
reg = <ef600d00 c>;
};
EMAC0: ethernet@ef600e00 {
device_type = "network";
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
interrupt-parent = <&UIC1>;
interrupts = <1c 4 1d 4>;
reg = <ef600e00 70>;
local-mac-address = [000000000000];
mal-device = <&MAL0>;
mal-tx-channel = <0 1>;
mal-rx-channel = <0>;
cell-index = <0>;
max-frame-size = <5dc>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rmii";
phy-map = <00000001>;
zmii-device = <&ZMII0>;
zmii-channel = <0>;
};
EMAC1: ethernet@ef600f00 {
device_type = "network";
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
interrupt-parent = <&UIC1>;
interrupts = <1e 4 1f 4>;
reg = <ef600f00 70>;
local-mac-address = [000000000000];
mal-device = <&MAL0>;
mal-tx-channel = <2 3>;
mal-rx-channel = <1>;
cell-index = <1>;
max-frame-size = <5dc>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rmii";
phy-map = <00000001>;
zmii-device = <&ZMII0>;
zmii-channel = <1>;
};
};
};
chosen {
linux,stdout-path = "/plb/opb/serial@ef600300";
bootargs = "console=ttyS0,115200";
};
};
arch/powerpc/boot/dts/ebony.dts
View file @ e8690861
......@@ -9,10 +9,6 @@
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* To build:
* dtc -I dts -O asm -o ebony.S -b 0 ebony.dts
* dtc -I dts -O dtb -o ebony.dtb -b 0 ebony.dts
*/
/ {
......@@ -142,13 +138,16 @@ EBC0: ebc {
interrupt-parent = <&UIC1>;
small-flash@0,80000 {
device_type = "rom";
compatible = "direct-mapped";
probe-type = "JEDEC";
compatible = "jedec-flash";
bank-width = <1>;
partitions = <0 80000>;
partition-names = "OpenBIOS";
reg = <0 80000 80000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "OpenBIOS";
reg = <0 80000>;
read-only;
};
};
ds1743@1,0 {
......@@ -158,14 +157,19 @@ ds1743@1,0 {
};
large-flash@2,0 {
device_type = "rom";
compatible = "direct-mapped";
probe-type = "JEDEC";
compatible = "jedec-flash";
bank-width = <1>;
partitions = <0 380000
380000 80000>;
partition-names = "fs", "firmware";
reg = <2 0 400000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "fs";
reg = <0 380000>;
};
partition@380000 {
label = "firmware";
reg = <380000 80000>;
};
};
ir@3,0 {
......@@ -175,6 +179,7 @@ ir@3,0 {
fpga@7,0 {
compatible = "Ebony-FPGA";
reg = <7 0 10>;
virtual-reg = <e8300000>;
};
};
......
arch/powerpc/boot/dts/ep88xc.dts 0 → 100644
View file @ e8690861
/*
* EP88xC Device Tree Source
*
* Copyright 2006 MontaVista Software, Inc.
* Copyright 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/ {
model = "EP88xC";
compatible = "fsl,ep88xc";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,885@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <d#16>;
i-cache-line-size = <d#16>;
d-cache-size = <d#8192>;
i-cache-size = <d#8192>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
reg = <0 0>;
};
localbus@fa200100 {
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <fa200100 40>;
ranges = <
0 0 fc000000 04000000
3 0 fa000000 01000000
>;
flash@0,2000000 {
compatible = "cfi-flash";
reg = <0 2000000 2000000>;
bank-width = <4>;
device-width = <2>;
};
board-control@3,400000 {
reg = <3 400000 10>;
compatible = "fsl,ep88xc-bcsr";
};
};
soc@fa200000 {
compatible = "fsl,mpc885", "fsl,pq1-soc";
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 fa200000 00004000>;
bus-frequency = <0>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <fa200000 4000>;
mdio@e00 {
compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
reg = <e00 188>;
#address-cells = <1>;
#size-cells = <0>;
PHY0: ethernet-phy@0 {
reg = <0>;
device_type = "ethernet-phy";
};
PHY1: ethernet-phy@1 {
reg = <1>;
device_type = "ethernet-phy";
};
};
ethernet@e00 {
device_type = "network";
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
reg = <e00 188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <3 1>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
};
ethernet@1e00 {
device_type = "network";
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
reg = <1e00 188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <7 1>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
};
PIC: interrupt-controller@0 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 24>;
compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
};
pcmcia@80 {
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
compatible = "fsl,pq-pcmcia";
device_type = "pcmcia";
reg = <80 80>;
interrupt-parent = <&PIC>;
interrupts = <d 1>;
};
cpm@9c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc885-cpm", "fsl,cpm1";
command-proc = <9c0>;
interrupts = <0>; // cpm error interrupt
interrupt-parent = <&CPM_PIC>;
reg = <9c0 40>;
ranges;
muram@2000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 2000 2000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 1c00>;
};
};
brg@9f0 {
compatible = "fsl,mpc885-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
reg = <9f0 10>;
};
CPM_PIC: interrupt-controller@930 {
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <5 2 0 2>;
interrupt-parent = <&PIC>;
reg = <930 20>;
compatible = "fsl,mpc885-cpm-pic",
"fsl,cpm1-pic";
};
// MON-1
serial@a80 {
device_type = "serial";
compatible = "fsl,mpc885-smc-uart",
"fsl,cpm1-smc-uart";
reg = <a80 10 3e80 40>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0090>;
linux,planetcore-label = "SMC1";
};
// SER-1
serial@a20 {
device_type = "serial";
compatible = "fsl,mpc885-scc-uart",
"fsl,cpm1-scc-uart";
reg = <a20 20 3d00 80>;
interrupts = <1d>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <0040>;
linux,planetcore-label = "SCC2";
};
usb@a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc885-usb",
"fsl,cpm1-usb";
reg = <a00 18 1c00 80>;
interrupt-parent = <&CPM_PIC>;
interrupts = <1e>;
fsl,cpm-command = <0000>;
};
};
};
};
arch/powerpc/boot/dts/holly.dts
View file @ e8690861
......@@ -8,10 +8,6 @@
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* To build:
* dtc -I dts -O asm -o holly.S -b 0 holly.dts
* dtc -I dts -O dtb -o holly.dtb -b 0 holly.dts
*/
/ {
......@@ -35,7 +31,6 @@ PowerPC,750CL@0 {
timebase-frequency = <2faf080>;
clock-frequency = <23c34600>;
bus-frequency = <bebc200>;
32-bit;
};
};
......
arch/powerpc/boot/dts/kilauea.dts 0 → 100644
View file @ e8690861
/*
* Device Tree Source for AMCC Kilauea (405EX)
*
* Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "amcc,kilauea";
compatible = "amcc,kilauea";
dcr-parent = <&/cpus/PowerPC,405EX@0>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,405EX@0 {
device_type = "cpu";
reg = <0>;
clock-frequency = <0>; /* Filled in by U-Boot */
timebase-frequency = <0>; /* Filled in by U-Boot */
i-cache-line-size = <20>;
d-cache-line-size = <20>;
i-cache-size = <4000>; /* 16 kB */
d-cache-size = <4000>; /* 16 kB */
dcr-controller;
dcr-access-method = "native";
};
};
memory {
device_type = "memory";
reg = <0 0>; /* Filled in by U-Boot */
};
UIC0: interrupt-controller {
compatible = "ibm,uic-405ex", "ibm,uic";
interrupt-controller;
cell-index = <0>;
dcr-reg = <0c0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
};
UIC1: interrupt-controller1 {
compatible = "ibm,uic-405ex","ibm,uic";
interrupt-controller;
cell-index = <1>;
dcr-reg = <0d0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <1e 4 1f 4>; /* cascade */
interrupt-parent = <&UIC0>;
};
UIC2: interrupt-controller2 {
compatible = "ibm,uic-405ex","ibm,uic";
interrupt-controller;
cell-index = <2>;
dcr-reg = <0e0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <1c 4 1d 4>; /* cascade */
interrupt-parent = <&UIC0>;
};
plb {
compatible = "ibm,plb-405ex", "ibm,plb4";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-frequency = <0>; /* Filled in by U-Boot */
SDRAM0: memory-controller {
compatible = "ibm,sdram-405ex";
dcr-reg = <010 2>;
};
MAL0: mcmal {
compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
dcr-reg = <180 62>;
num-tx-chans = <2>;
num-rx-chans = <2>;
interrupt-parent = <&MAL0>;
interrupts = <0 1 2 3 4>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
/*RXEOB*/ 1 &UIC0 b 4
/*SERR*/ 2 &UIC1 0 4
/*TXDE*/ 3 &UIC1 1 4
/*RXDE*/ 4 &UIC1 2 4>;
interrupt-map-mask = <ffffffff>;
};
POB0: opb {
compatible = "ibm,opb-405ex", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
ranges = <80000000 80000000 10000000
ef600000 ef600000 a00000
f0000000 f0000000 10000000>;
dcr-reg = <0a0 5>;
clock-frequency = <0>; /* Filled in by U-Boot */
EBC0: ebc {
compatible = "ibm,ebc-405ex", "ibm,ebc";
dcr-reg = <012 2>;
#address-cells = <2>;
#size-cells = <1>;
clock-frequency = <0>; /* Filled in by U-Boot */
/* ranges property is supplied by U-Boot */
interrupts = <5 1>;
interrupt-parent = <&UIC1>;
nor_flash@0,0 {
compatible = "amd,s29gl512n", "cfi-flash";
bank-width = <2>;
reg = <0 000000 4000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0 200000>;
};
partition@200000 {
label = "root";
reg = <200000 200000>;
};
partition@400000 {
label = "user";
reg = <400000 3b60000>;
};
partition@3f60000 {
label = "env";
reg = <3f60000 40000>;
};
partition@3fa0000 {
label = "u-boot";
reg = <3fa0000 60000>;
};
};
};
UART0: serial@ef600200 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600200 8>;
virtual-reg = <ef600200>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <1a 4>;
};
UART1: serial@ef600300 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600300 8>;
virtual-reg = <ef600300>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <1 4>;
};
IIC0: i2c@ef600400 {
device_type = "i2c";
compatible = "ibm,iic-405ex", "ibm,iic";
reg = <ef600400 14>;
interrupt-parent = <&UIC0>;
interrupts = <2 4>;
};
IIC1: i2c@ef600500 {
device_type = "i2c";
compatible = "ibm,iic-405ex", "ibm,iic";
reg = <ef600500 14>;
interrupt-parent = <&UIC0>;
interrupts = <7 4>;
};
RGMII0: emac-rgmii@ef600b00 {
device_type = "rgmii-interface";
compatible = "ibm,rgmii-405ex", "ibm,rgmii";
reg = <ef600b00 104>;
};
EMAC0: ethernet@ef600900 {
linux,network-index = <0>;
device_type = "network";
compatible = "ibm,emac-405ex", "ibm,emac4";
interrupt-parent = <&EMAC0>;
interrupts = <0 1>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*Status*/ 0 &UIC0 18 4
/*Wake*/ 1 &UIC1 1d 4>;
reg = <ef600900 70>;
local-mac-address = [000000000000]; /* Filled in by U-Boot */
mal-device = <&MAL0>;
mal-tx-channel = <0>;
mal-rx-channel = <0>;
cell-index = <0>;
max-frame-size = <5dc>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
phy-map = <00000000>;
rgmii-device = <&RGMII0>;
rgmii-channel = <0>;
};
EMAC1: ethernet@ef600a00 {
linux,network-index = <1>;
device_type = "network";
compatible = "ibm,emac-405ex", "ibm,emac4";
interrupt-parent = <&EMAC1>;
interrupts = <0 1>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*Status*/ 0 &UIC0 19 4
/*Wake*/ 1 &UIC1 1f 4>;
reg = <ef600a00 70>;
local-mac-address = [000000000000]; /* Filled in by U-Boot */
mal-device = <&MAL0>;
mal-tx-channel = <1>;
mal-rx-channel = <1>;
cell-index = <1>;
max-frame-size = <5dc>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
phy-map = <00000000>;
rgmii-device = <&RGMII0>;
rgmii-channel = <1>;
};
};
};
};
arch/powerpc/boot/dts/kuroboxHD.dts
View file @ e8690861
......@@ -15,9 +15,6 @@
XXXX add flash parts, rtc, ??
build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
*/
/ {
......@@ -50,7 +47,6 @@ memory {
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
......@@ -72,7 +68,7 @@ i2c@80003000 {
rtc@32 {
device_type = "rtc";
compatible = "ricoh,rs5c372b";
compatible = "ricoh,rs5c372a";
reg = <32>;
};
};
......@@ -83,7 +79,7 @@ serial@80004500 {
reg = <80004500 8>;
clock-frequency = <5d08d88>;
current-speed = <2580>;
interrupts = <9 2>;
interrupts = <9 0>;
interrupt-parent = <&mpic>;
};
......@@ -104,7 +100,6 @@ mpic: interrupt-controller@80040000 {
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
built-in;
};
pci@fec00000 {
......
arch/powerpc/boot/dts/kuroboxHG.dts
View file @ e8690861
......@@ -15,9 +15,6 @@
XXXX add flash parts, rtc, ??
build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
*/
/ {
......@@ -50,7 +47,6 @@ memory {
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
......@@ -72,7 +68,7 @@ i2c@80003000 {
rtc@32 {
device_type = "rtc";
compatible = "ricoh,rs5c372b";
compatible = "ricoh,rs5c372a";
reg = <32>;
};
};
......@@ -83,7 +79,7 @@ serial@80004500 {
reg = <80004500 8>;
clock-frequency = <7c044a8>;
current-speed = <2580>;
interrupts = <9 2>;
interrupts = <9 0>;
interrupt-parent = <&mpic>;
};
......@@ -104,7 +100,6 @@ mpic: interrupt-controller@80040000 {
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
built-in;
};
pci@fec00000 {
......
arch/powerpc/boot/dts/lite5200.dts
View file @ e8690861
......@@ -19,7 +19,7 @@
/ {
model = "fsl,lite5200";
// revision = "1.0";
compatible = "fsl,lite5200\0generic-mpc5200";
compatible = "fsl,lite5200","generic-mpc5200";
#address-cells = <1>;
#size-cells = <1>;
......@@ -37,7 +37,6 @@ PowerPC,5200@0 {
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
......@@ -50,10 +49,9 @@ soc5200@f0000000 {
model = "fsl,mpc5200";
compatible = "mpc5200";
revision = ""; // from bootloader
#interrupt-cells = <3>;
device_type = "soc";
ranges = <0 f0000000 f0010000>;
reg = <f0000000 00010000>;
ranges = <0 f0000000 0000c000>;
reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
......@@ -69,7 +67,6 @@ mpc5200_pic: pic@500 {
device_type = "interrupt-controller";
compatible = "mpc5200-pic";
reg = <500 80>;
built-in;
};
gpt@600 { // General Purpose Timer
......@@ -185,27 +182,6 @@ gpio-wkup@c00 {
interrupt-parent = <&mpc5200_pic>;
};
pci@0d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "mpc5200-pci";
reg = <d00 100>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
c000 0 0 2 &mpc5200_pic 0 0 3
c000 0 0 3 &mpc5200_pic 0 0 3
c000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 a 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 b0000000 0 01000000>;
};
spi@f00 {
device_type = "spi";
compatible = "mpc5200-spi";
......@@ -216,7 +192,7 @@ spi@f00 {
usb@1000 {
device_type = "usb-ohci-be";
compatible = "mpc5200-ohci\0ohci-be";
compatible = "mpc5200-ohci","ohci-be";
reg = <1000 ff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
......@@ -317,7 +293,7 @@ ata@3a00 {
i2c@3d00 {
device_type = "i2c";
compatible = "mpc5200-i2c\0fsl-i2c";
compatible = "mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <3d00 40>;
interrupts = <2 f 0>;
......@@ -327,7 +303,7 @@ i2c@3d00 {
i2c@3d40 {
device_type = "i2c";
compatible = "mpc5200-i2c\0fsl-i2c";
compatible = "mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <3d40 40>;
interrupts = <2 10 0>;
......@@ -336,8 +312,29 @@ i2c@3d40 {
};
sram@8000 {
device_type = "sram";
compatible = "mpc5200-sram\0sram";
compatible = "mpc5200-sram","sram";
reg = <8000 4000>;
};
};
pci@f0000d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "mpc5200-pci";
reg = <f0000d00 100>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
c000 0 0 2 &mpc5200_pic 0 0 3
c000 0 0 3 &mpc5200_pic 0 0 3
c000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 a 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 b0000000 0 01000000>;
};
};
arch/powerpc/boot/dts/lite5200b.dts
View file @ e8690861
......@@ -19,7 +19,7 @@
/ {
model = "fsl,lite5200b";
// revision = "1.0";
compatible = "fsl,lite5200b\0generic-mpc5200";
compatible = "fsl,lite5200b","generic-mpc5200";
#address-cells = <1>;
#size-cells = <1>;
......@@ -37,7 +37,6 @@ PowerPC,5200@0 {
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
......@@ -50,15 +49,14 @@ soc5200@f0000000 {
model = "fsl,mpc5200b";
compatible = "mpc5200";
revision = ""; // from bootloader
#interrupt-cells = <3>;
device_type = "soc";
ranges = <0 f0000000 f0010000>;
reg = <f0000000 00010000>;
ranges = <0 f0000000 0000c000>;
reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "mpc5200b-cdm\0mpc5200-cdm";
compatible = "mpc5200b-cdm","mpc5200-cdm";
reg = <200 38>;
};
......@@ -67,13 +65,12 @@ mpc5200_pic: pic@500 {
interrupt-controller;
#interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "mpc5200b-pic\0mpc5200-pic";
compatible = "mpc5200b-pic","mpc5200-pic";
reg = <500 80>;
built-in;
};
gpt@600 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <0>;
reg = <600 10>;
......@@ -83,7 +80,7 @@ gpt@600 { // General Purpose Timer
};
gpt@610 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <1>;
reg = <610 10>;
......@@ -92,7 +89,7 @@ gpt@610 { // General Purpose Timer
};
gpt@620 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <2>;
reg = <620 10>;
......@@ -101,7 +98,7 @@ gpt@620 { // General Purpose Timer
};
gpt@630 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <3>;
reg = <630 10>;
......@@ -110,7 +107,7 @@ gpt@630 { // General Purpose Timer
};
gpt@640 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <4>;
reg = <640 10>;
......@@ -119,7 +116,7 @@ gpt@640 { // General Purpose Timer
};
gpt@650 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <5>;
reg = <650 10>;
......@@ -128,7 +125,7 @@ gpt@650 { // General Purpose Timer
};
gpt@660 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <6>;
reg = <660 10>;
......@@ -137,7 +134,7 @@ gpt@660 { // General Purpose Timer
};
gpt@670 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <7>;
reg = <670 10>;
......@@ -146,7 +143,7 @@ gpt@670 { // General Purpose Timer
};
rtc@800 { // Real time clock
compatible = "mpc5200b-rtc\0mpc5200-rtc";
compatible = "mpc5200b-rtc","mpc5200-rtc";
device_type = "rtc";
reg = <800 100>;
interrupts = <1 5 0 1 6 0>;
......@@ -155,7 +152,7 @@ rtc@800 { // Real time clock
mscan@900 {
device_type = "mscan";
compatible = "mpc5200b-mscan\0mpc5200-mscan";
compatible = "mpc5200b-mscan","mpc5200-mscan";
cell-index = <0>;
interrupts = <2 11 0>;
interrupt-parent = <&mpc5200_pic>;
......@@ -164,7 +161,7 @@ mscan@900 {
mscan@980 {
device_type = "mscan";
compatible = "mpc5200b-mscan\0mpc5200-mscan";
compatible = "mpc5200b-mscan","mpc5200-mscan";
cell-index = <1>;
interrupts = <2 12 0>;
interrupt-parent = <&mpc5200_pic>;
......@@ -172,48 +169,22 @@ mscan@980 {
};
gpio@b00 {
compatible = "mpc5200b-gpio\0mpc5200-gpio";
compatible = "mpc5200b-gpio","mpc5200-gpio";
reg = <b00 40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio-wkup@c00 {
compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup";
compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup";
reg = <c00 40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
pci@0d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "mpc5200b-pci\0mpc5200-pci";
reg = <d00 100>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
c000 0 0 2 &mpc5200_pic 1 1 3
c000 0 0 3 &mpc5200_pic 1 2 3
c000 0 0 4 &mpc5200_pic 1 3 3
c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
c800 0 0 2 &mpc5200_pic 1 2 3
c800 0 0 3 &mpc5200_pic 1 3 3
c800 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 a 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 b0000000 0 01000000>;
};
spi@f00 {
device_type = "spi";
compatible = "mpc5200b-spi\0mpc5200-spi";
compatible = "mpc5200b-spi","mpc5200-spi";
reg = <f00 20>;
interrupts = <2 d 0 2 e 0>;
interrupt-parent = <&mpc5200_pic>;
......@@ -221,7 +192,7 @@ spi@f00 {
usb@1000 {
device_type = "usb-ohci-be";
compatible = "mpc5200b-ohci\0mpc5200-ohci\0ohci-be";
compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be";
reg = <1000 ff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
......@@ -229,7 +200,7 @@ usb@1000 {
bestcomm@1200 {
device_type = "dma-controller";
compatible = "mpc5200b-bestcomm\0mpc5200-bestcomm";
compatible = "mpc5200b-bestcomm","mpc5200-bestcomm";
reg = <1200 80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
......@@ -239,13 +210,13 @@ bestcomm@1200 {
};
xlb@1f00 {
compatible = "mpc5200b-xlb\0mpc5200-xlb";
compatible = "mpc5200b-xlb","mpc5200-xlb";
reg = <1f00 100>;
};
serial@2000 { // PSC1
device_type = "serial";
compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
cell-index = <0>;
reg = <2000 100>;
......@@ -256,7 +227,7 @@ serial@2000 { // PSC1
// PSC2 in ac97 mode example
//ac97@2200 { // PSC2
// device_type = "sound";
// compatible = "mpc5200b-psc-ac97\0mpc5200-psc-ac97";
// compatible = "mpc5200b-psc-ac97","mpc5200-psc-ac97";
// cell-index = <1>;
// reg = <2200 100>;
// interrupts = <2 2 0>;
......@@ -276,7 +247,7 @@ serial@2000 { // PSC1
// PSC4 in uart mode example
//serial@2600 { // PSC4
// device_type = "serial";
// compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
// compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
// cell-index = <3>;
// reg = <2600 100>;
// interrupts = <2 b 0>;
......@@ -286,7 +257,7 @@ serial@2000 { // PSC1
// PSC5 in uart mode example
//serial@2800 { // PSC5
// device_type = "serial";
// compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
// compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
// cell-index = <4>;
// reg = <2800 100>;
// interrupts = <2 c 0>;
......@@ -296,7 +267,7 @@ serial@2000 { // PSC1
// PSC6 in spi mode example
//spi@2c00 { // PSC6
// device_type = "spi";
// compatible = "mpc5200b-psc-spi\0mpc5200-psc-spi";
// compatible = "mpc5200b-psc-spi","mpc5200-psc-spi";
// cell-index = <5>;
// reg = <2c00 100>;
// interrupts = <2 4 0>;
......@@ -305,7 +276,7 @@ serial@2000 { // PSC1
ethernet@3000 {
device_type = "network";
compatible = "mpc5200b-fec\0mpc5200-fec";
compatible = "mpc5200b-fec","mpc5200-fec";
reg = <3000 800>;
mac-address = [ 02 03 04 05 06 07 ]; // Bad!
interrupts = <2 5 0>;
......@@ -314,7 +285,7 @@ ethernet@3000 {
ata@3a00 {
device_type = "ata";
compatible = "mpc5200b-ata\0mpc5200-ata";
compatible = "mpc5200b-ata","mpc5200-ata";
reg = <3a00 100>;
interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
......@@ -322,7 +293,7 @@ ata@3a00 {
i2c@3d00 {
device_type = "i2c";
compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c";
compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <3d00 40>;
interrupts = <2 f 0>;
......@@ -332,7 +303,7 @@ i2c@3d00 {
i2c@3d40 {
device_type = "i2c";
compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c";
compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <3d40 40>;
interrupts = <2 10 0>;
......@@ -341,8 +312,34 @@ i2c@3d40 {
};
sram@8000 {
device_type = "sram";
compatible = "mpc5200b-sram\0mpc5200-sram\0sram";
compatible = "mpc5200b-sram","mpc5200-sram","sram";
reg = <8000 4000>;
};
};
pci@f0000d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "mpc5200b-pci","mpc5200-pci";
reg = <f0000d00 100>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
c000 0 0 2 &mpc5200_pic 1 1 3
c000 0 0 3 &mpc5200_pic 1 2 3
c000 0 0 4 &mpc5200_pic 1 3 3
c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
c800 0 0 2 &mpc5200_pic 1 2 3
c800 0 0 3 &mpc5200_pic 1 3 3
c800 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 a 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 b0000000 0 01000000>;
};
};
arch/powerpc/boot/dts/mpc7448hpc2.dts
View file @ e8690861
......@@ -31,7 +31,6 @@ PowerPC,7448@0 {
timebase-frequency = <0>; // 33 MHz, from uboot
clock-frequency = <0>; // From U-Boot
bus-frequency = <0>; // From U-Boot
32-bit;
};
};
......@@ -44,7 +43,6 @@ memory {
tsi108@c0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "tsi-bridge";
ranges = <00000000 c0000000 00010000>;
reg = <c0000000 00010000>;
......@@ -80,6 +78,7 @@ phy9: ethernet-phy@9 {
};
ethernet@6200 {
linux,network-index = <0>;
#size-cells = <0>;
device_type = "network";
compatible = "tsi108-ethernet";
......@@ -92,6 +91,7 @@ ethernet@6200 {
};
ethernet@6600 {
linux,network-index = <1>;
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
......@@ -128,7 +128,6 @@ mpic: pic@7400 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <7400 400>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
......@@ -180,12 +179,14 @@ RT0: router@1180 {
device_type = "pic-router";
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
big-endian;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
};
};
chosen {
linux,stdout-path = "/tsi108@c0000000/serial@7808";
};
};
arch/powerpc/boot/dts/mpc8272ads.dts
View file @ e8690861
This diff is collapsed.
arch/powerpc/boot/dts/mpc8313erdb.dts
View file @ e8690861
......@@ -29,7 +29,6 @@ PowerPC,8313@0 {
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
......@@ -41,7 +40,6 @@ memory {
soc8313@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
......@@ -73,11 +71,11 @@ i2c@3100 {
spi@7000 {
device_type = "spi";
compatible = "mpc83xx_spi";
compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
mode = <0>;
mode = "cpu";
};
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
......@@ -152,36 +150,6 @@ serial@4600 {
interrupt-parent = < &ipic >;
};
pci@8500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0E -mini PCI */
7000 0 0 1 &ipic 12 8
7000 0 0 2 &ipic 12 8
7000 0 0 3 &ipic 12 8
7000 0 0 4 &ipic 12 8
/* IDSEL 0x0F - PCI slot */
7800 0 0 1 &ipic 11 8
7800 0 0 2 &ipic 12 8
7800 0 0 3 &ipic 11 8
7800 0 0 4 &ipic 12 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
crypto@30000 {
device_type = "crypto";
model = "SEC2";
......@@ -207,8 +175,37 @@ ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0E -mini PCI */
7000 0 0 1 &ipic 12 8
7000 0 0 2 &ipic 12 8
7000 0 0 3 &ipic 12 8
7000 0 0 4 &ipic 12 8
/* IDSEL 0x0F - PCI slot */
7800 0 0 1 &ipic 11 8
7800 0 0 2 &ipic 12 8
7800 0 0 3 &ipic 11 8
7800 0 0 4 &ipic 12 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};
arch/powerpc/boot/dts/mpc832x_mds.dts
View file @ e8690861
......@@ -29,7 +29,6 @@ PowerPC,8323@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
......@@ -46,7 +45,6 @@ bcsr@f8000000 {
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
......@@ -99,71 +97,11 @@ crypto@30000 {
descriptor-types-mask = <0122003f>;
};
pci@8500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 AD17 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 AD18 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 AD19 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 AD21*/
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 AD22*/
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 AD23*/
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 AD24*/
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 d0000000 0 00100000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
......@@ -333,10 +271,68 @@ qeic: qeic@80 {
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 AD17 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 AD18 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 AD19 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 AD21*/
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 AD22*/
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 AD23*/
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 AD24*/
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 d0000000 0 00100000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};
arch/powerpc/boot/dts/mpc832x_rdb.dts
View file @ e8690861
......@@ -29,7 +29,6 @@ PowerPC,8323@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
......@@ -41,7 +40,6 @@ memory {
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
......@@ -94,45 +92,11 @@ crypto@30000 {
descriptor-types-mask = <0122003f>;
};
pci@8500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 AD16 (USB) */
8000 0 0 1 &pic 11 8
/* IDSEL 0x11 AD17 (Mini1)*/
8800 0 0 1 &pic 12 8
8800 0 0 2 &pic 13 8
8800 0 0 3 &pic 14 8
8800 0 0 4 &pic 30 8
/* IDSEL 0x12 AD18 (PCI/Mini2) */
9000 0 0 1 &pic 13 8
9000 0 0 2 &pic 14 8
9000 0 0 3 &pic 30 8
9000 0 0 4 &pic 11 8>;
interrupt-parent = <&pic>;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 10000000
02000000 0 90000000 90000000 0 10000000
01000000 0 d0000000 d0000000 0 04000000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pic:pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
......@@ -211,7 +175,7 @@ spi@4c0 {
reg = <4c0 40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
mode = "cpu";
mode = "cpu-qe";
};
spi@500 {
......@@ -292,10 +256,42 @@ qeic:qeic@80 {
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = <&pic>;
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 AD16 (USB) */
8000 0 0 1 &pic 11 8
/* IDSEL 0x11 AD17 (Mini1)*/
8800 0 0 1 &pic 12 8
8800 0 0 2 &pic 13 8
8800 0 0 3 &pic 14 8
8800 0 0 4 &pic 30 8
/* IDSEL 0x12 AD18 (PCI/Mini2) */
9000 0 0 1 &pic 13 8
9000 0 0 2 &pic 14 8
9000 0 0 3 &pic 30 8
9000 0 0 4 &pic 11 8>;
interrupt-parent = <&pic>;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 10000000
02000000 0 90000000 90000000 0 10000000
01000000 0 d0000000 d0000000 0 04000000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};
arch/powerpc/boot/dts/mpc8349emitx.dts
View file @ e8690861
......@@ -28,7 +28,6 @@ PowerPC,8349@0 {
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
......@@ -40,7 +39,6 @@ memory {
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
......@@ -72,11 +70,11 @@ i2c@3100 {
spi@7000 {
device_type = "spi";
compatible = "mpc83xx_spi";
compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
mode = <0>;
mode = "cpu";
};
usb@22000 {
......@@ -142,6 +140,7 @@ ethernet@24000 {
interrupts = <20 8 21 8 22 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1c >;
linux,network-index = <0>;
};
ethernet@25000 {
......@@ -161,6 +160,7 @@ ethernet@25000 {
interrupts = <23 8 24 8 25 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1f >;
linux,network-index = <1>;
};
serial@4500 {
......@@ -181,7 +181,29 @@ serial@4600 {
interrupt-parent = < &ipic >;
};
pci@8500 {
crypto@30000 {
device_type = "crypto";
model = "SEC2";
compatible = "talitos";
reg = <30000 10000>;
interrupts = <b 8>;
interrupt-parent = < &ipic >;
num-channels = <4>;
channel-fifo-len = <18>;
exec-units-mask = <0000007e>;
descriptor-types-mask = <01010ebf>;
};
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
device_type = "ipic";
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 - SATA */
......@@ -197,12 +219,12 @@ pci@8500 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci@8600 {
pci@e0008600 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0E - MiniPCI Slot */
......@@ -214,7 +236,7 @@ pci@8600 {
>;
interrupt-parent = < &ipic >;
interrupts = <43 8>;
bus-range = <1 1>;
bus-range = <0 0>;
ranges = <42000000 0 a0000000 a0000000 0 10000000
02000000 0 b0000000 b0000000 0 10000000
01000000 0 00000000 e3000000 0 01000000>;
......@@ -222,31 +244,11 @@ pci@8600 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8600 100>;
reg = <e0008600 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
crypto@30000 {
device_type = "crypto";
model = "SEC2";
compatible = "talitos";
reg = <30000 10000>;
interrupts = <b 8>;
interrupt-parent = < &ipic >;
num-channels = <4>;
channel-fifo-len = <18>;
exec-units-mask = <0000007e>;
descriptor-types-mask = <01010ebf>;
};
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};
};
arch/powerpc/boot/dts/mpc8349emitxgp.dts
View file @ e8690861
......@@ -28,7 +28,6 @@ PowerPC,8349@0 {
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
......@@ -40,7 +39,6 @@ memory {
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
......@@ -72,11 +70,11 @@ i2c@3100 {
spi@7000 {
device_type = "spi";
compatible = "mpc83xx_spi";
compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
mode = <0>;
mode = "cpu";
};
usb@23000 {
......@@ -116,6 +114,7 @@ ethernet@24000 {
interrupts = <20 8 21 8 22 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1c >;
linux,network-index = <0>;
};
serial@4500 {
......@@ -136,28 +135,6 @@ serial@4600 {
interrupt-parent = < &ipic >;
};
pci@8600 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0F - PCI Slot */
7800 0 0 1 &ipic 14 8 /* PCI_INTA */
7800 0 0 2 &ipic 15 8 /* PCI_INTB */
>;
interrupt-parent = < &ipic >;
interrupts = <43 8>;
bus-range = <1 1>;
ranges = <42000000 0 a0000000 a0000000 0 10000000
02000000 0 b0000000 b0000000 0 10000000
01000000 0 00000000 e3000000 0 01000000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8600 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
crypto@30000 {
device_type = "crypto";
model = "SEC2";
......@@ -176,8 +153,29 @@ ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};
pci@e0008600 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0F - PCI Slot */
7800 0 0 1 &ipic 14 8 /* PCI_INTA */
7800 0 0 2 &ipic 15 8 /* PCI_INTB */
>;
interrupt-parent = < &ipic >;
interrupts = <43 8>;
bus-range = <1 1>;
ranges = <42000000 0 a0000000 a0000000 0 10000000
02000000 0 b0000000 b0000000 0 10000000
01000000 0 00000000 e3000000 0 01000000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008600 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};
arch/powerpc/boot/dts/mpc834x_mds.dts
View file @ e8690861
......@@ -29,7 +29,6 @@ PowerPC,8349@0 {
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
......@@ -46,7 +45,6 @@ bcsr@e2400000 {
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
......@@ -78,11 +76,11 @@ i2c@3100 {
spi@7000 {
device_type = "spi";
compatible = "mpc83xx_spi";
compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
mode = <0>;
mode = "cpu";
};
/* phy type (ULPI or SERIAL) are only types supportted for MPH */
......@@ -146,6 +144,7 @@ ethernet@24000 {
interrupts = <20 8 21 8 22 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy0 >;
linux,network-index = <0>;
};
ethernet@25000 {
......@@ -165,6 +164,7 @@ ethernet@25000 {
interrupts = <23 8 24 8 25 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1 >;
linux,network-index = <1>;
};
serial@4500 {
......@@ -185,7 +185,38 @@ serial@4600 {
interrupt-parent = < &ipic >;
};
pci@8500 {
/* May need to remove if on a part without crypto engine */
crypto@30000 {
device_type = "crypto";
model = "SEC2";
compatible = "talitos";
reg = <30000 10000>;
interrupts = <b 8>;
interrupt-parent = < &ipic >;
num-channels = <4>;
channel-fifo-len = <18>;
exec-units-mask = <0000007e>;
/* desc mask is for rev2.0,
* we need runtime fixup for >2.0 */
descriptor-types-mask = <01010ebf>;
};
/* IPIC
* interrupts cell = <intr #, sense>
* sense values match linux IORESOURCE_IRQ_* defines:
* sense == 8: Level, low assertion
* sense == 2: Edge, high-to-low change
*/
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
device_type = "ipic";
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
......@@ -240,12 +271,12 @@ c000 0 0 3 &ipic 17 8
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci@8600 {
pci@e0008600 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
......@@ -300,40 +331,8 @@ c000 0 0 3 &ipic 17 8
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8600 100>;
reg = <e0008600 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
/* May need to remove if on a part without crypto engine */
crypto@30000 {
device_type = "crypto";
model = "SEC2";
compatible = "talitos";
reg = <30000 10000>;
interrupts = <b 8>;
interrupt-parent = < &ipic >;
num-channels = <4>;
channel-fifo-len = <18>;
exec-units-mask = <0000007e>;
/* desc mask is for rev2.0,
* we need runtime fixup for >2.0 */
descriptor-types-mask = <01010ebf>;
};
/* IPIC
* interrupts cell = <intr #, sense>
* sense values match linux IORESOURCE_IRQ_* defines:
* sense == 8: Level, low assertion
* sense == 2: Edge, high-to-low change
*/
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};
};
arch/powerpc/boot/dts/mpc836x_mds.dts
View file @ e8690861
......@@ -34,7 +34,6 @@ PowerPC,8360@0 {
timebase-frequency = <3EF1480>;
bus-frequency = <FBC5200>;
clock-frequency = <1F78A400>;
32-bit;
};
};
......@@ -51,7 +50,6 @@ bcsr@f8000000 {
soc8360@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
......@@ -113,72 +111,11 @@ crypto@30000 {
descriptor-types-mask = <01010ebf>;
};
pci@8500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 AD17 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 AD18 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 AD19 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 AD21*/
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 AD22*/
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 AD23*/
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 AD24*/
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
......@@ -364,11 +301,69 @@ qeic: qeic@80 {
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 AD17 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 AD18 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 AD19 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 AD21*/
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 AD22*/
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 AD23*/
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 AD24*/
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};
arch/powerpc/boot/dts/mpc8540ads.dts
View file @ e8690861
......@@ -30,7 +30,6 @@ PowerPC,8540@0 {
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
};
};
......@@ -42,7 +41,6 @@ memory {
soc8540@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
......@@ -173,7 +171,19 @@ serial@4600 {
interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
pci@8000 {
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
};
pci@e0008000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
......@@ -257,21 +267,8 @@ a800 0 0 3 &mpic 4 1
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
reg = <e0008000 1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
};
};
arch/powerpc/boot/dts/mpc8541cds.dts
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arch/powerpc/boot/dts/mpc8544ds.dts
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arch/powerpc/boot/dts/mpc8548cds.dts
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arch/powerpc/boot/dts/mpc8555cds.dts
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arch/powerpc/boot/dts/mpc8560ads.dts
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arch/powerpc/boot/dts/mpc8568mds.dts
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arch/powerpc/boot/dts/mpc8641_hpcn.dts
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arch/powerpc/boot/dts/mpc866ads.dts
View file @ e8690861
......@@ -30,7 +30,6 @@ PowerPC,866@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
};
......@@ -44,7 +43,6 @@ memory {
soc866@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
......@@ -78,7 +76,6 @@ mpc8xx_pic: pic@ff000000 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
built-in;
device_type = "mpc8xx-pic";
compatible = "CPM";
};
......@@ -86,7 +83,6 @@ mpc8xx_pic: pic@ff000000 {
cpm@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
......@@ -103,7 +99,6 @@ cpm_pic: pic@930 {
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
reg = <930 20>;
built-in;
device_type = "cpm-pic";
compatible = "CPM";
};
......
arch/powerpc/boot/dts/mpc885ads.dts
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arch/powerpc/boot/dts/prpmc2800.dts
View file @ e8690861
......@@ -9,10 +9,6 @@
*
* Property values that are labeled as "Default" will be updated by bootwrapper
* if it can determine the exact PrPMC type.
*
* To build:
* dtc -I dts -O asm -o prpmc2800.S -b 0 prpmc2800.dts
* dtc -I dts -O dtb -o prpmc2800.dtb -b 0 prpmc2800.dts
*/
/ {
......@@ -47,7 +43,6 @@ memory {
mv64x60@f1000000 { /* Marvell Discovery */
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <1>;
model = "mv64360"; /* Default */
compatible = "marvell,mv64x60";
clock-frequency = <7f28155>; /* 133.333333 MHz */
......
arch/powerpc/boot/dts/sequoia.dts 0 → 100644
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arch/powerpc/boot/ebony.c
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arch/powerpc/boot/fixed-head.S 0 → 100644
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.text
.global _zimage_start
_zimage_start:
b _zimage_start_lib
arch/powerpc/boot/flatdevtree.c
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arch/powerpc/boot/flatdevtree.h
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......@@ -76,7 +76,7 @@ struct ft_cxt {
unsigned int nodes_used;
};
int ft_begin_node(struct ft_cxt *cxt, const char *name);
char *ft_begin_node(struct ft_cxt *cxt, const char *name);
void ft_end_node(struct ft_cxt *cxt);
void ft_begin_tree(struct ft_cxt *cxt);
......@@ -96,8 +96,7 @@ int ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
void ft_dump_blob(const void *bphp);
void ft_merge_blob(struct ft_cxt *cxt, void *blob);
void *ft_find_device(struct ft_cxt *cxt, const char *srch_path);
void *ft_find_device_rel(struct ft_cxt *cxt, const void *top,
void *ft_find_device(struct ft_cxt *cxt, const void *top,
const char *srch_path);
void *ft_find_descendent(struct ft_cxt *cxt, void *top, const char *srch_path);
int ft_get_prop(struct ft_cxt *cxt, const void *phandle, const char *propname,
......@@ -109,5 +108,6 @@ void *ft_find_node_by_prop_value(struct ft_cxt *cxt, const void *prev,
const char *propname, const char *propval,
int proplen);
void *ft_create_node(struct ft_cxt *cxt, const void *parent, const char *name);
char *ft_get_path(struct ft_cxt *cxt, const void *phandle, char *buf, int len);
#endif /* FLATDEVTREE_H */
arch/powerpc/boot/flatdevtree_env.h
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arch/powerpc/boot/flatdevtree_misc.c
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#ifndef _PPC_BOOT_FSL_SOC_H_
#define _PPC_BOOT_FSL_SOC_H_
#include "types.h"
u32 *fsl_get_immr(void);
#endif
arch/powerpc/boot/gunzip_util.c
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arch/powerpc/boot/holly.c
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......@@ -21,11 +21,6 @@
#include "ops.h"
#include "io.h"
extern char _start[];
extern char _end[];
extern char _dtb_start[];
extern char _dtb_end[];
BSS_STACK(4096);
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
......
arch/powerpc/boot/io.h
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arch/powerpc/boot/mv64x60_i2c.c
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