Commit eac137b4 authored by Jérémy Fanguède's avatar Jérémy Fanguède Committed by Christoffer Dall

KVM: arm64: Enable the EL1 physical timer for AArch32 guests

Some 32bits guest OS can use the CNTP timer, however KVM does not
handle the accesses, injecting a fault instead.

Use the proper handlers to emulate the EL1 Physical Timer (CNTP)
register accesses of AArch32 guests.
Signed-off-by: default avatarJérémy Fanguède <j.fanguede@virtualopensystems.com>
Signed-off-by: default avatarAlvise Rigo <a.rigo@virtualopensystems.com>
Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
parent 005781be
...@@ -1565,6 +1565,11 @@ static const struct sys_reg_desc cp15_regs[] = { ...@@ -1565,6 +1565,11 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
/* CNTP_TVAL */
{ Op1( 0), CRn(14), CRm( 2), Op2( 0), access_cntp_tval },
/* CNTP_CTL */
{ Op1( 0), CRn(14), CRm( 2), Op2( 1), access_cntp_ctl },
/* PMEVCNTRn */ /* PMEVCNTRn */
PMU_PMEVCNTR(0), PMU_PMEVCNTR(0),
PMU_PMEVCNTR(1), PMU_PMEVCNTR(1),
...@@ -1638,6 +1643,7 @@ static const struct sys_reg_desc cp15_64_regs[] = { ...@@ -1638,6 +1643,7 @@ static const struct sys_reg_desc cp15_64_regs[] = {
{ Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
{ Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
{ Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 }, { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
{ Op1( 2), CRn( 0), CRm(14), Op2( 0), access_cntp_cval },
}; };
/* Target specific emulation tables */ /* Target specific emulation tables */
......
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