Skip to content

L
linux
Commit edc05e6d authored by Ingo Molnar's avatar Ingo Molnar
Browse files
Options

x86: more coding style fixes in centaur.c 

no code changed:

 arch/x86/kernel/cpu/centaur.o:
    text    data     bss     dec     hex filename
    1031     324       0    1355     54b centaur.o.before
    1031     324       0    1355     54b centaur.o.after

 md5:
  4f306a7f980b58eb69c4bdcfcde565f1  centaur.o.before.asm
  4f306a7f980b58eb69c4bdcfcde565f1  centaur.o.after.asm
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 29a9994b
Hide whitespace changes
Inline Side-by-side
Showing with 199 additions and 195 deletions
arch/x86/kernel/cpu/centaur.c
View file @ edc05e6d
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/msr.h> #include <asm/msr.h>
#include <asm/e820.h> #include <asm/e820.h>
#include <asm/mtrr.h> #include <asm/mtrr.h>
#include "cpu.h" #include "cpu.h"
#ifdef CONFIG_X86_OOSTORE #ifdef CONFIG_X86_OOSTORE
...@@ -12,16 +14,17 @@ ...@@ -12,16 +14,17 @@
static u32 __cpuinit power2(u32 x) static u32 __cpuinit power2(u32 x)
{ {
u32 s = 1; u32 s = 1;
while(s <= x)
while (s <= x)
s <<= 1; s <<= 1;
return s >>= 1; return s >>= 1;
} }
/* /*
* Set up an actual MCR * Set up an actual MCR
*/ */
static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key) static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key)
{ {
u32 lo, hi; u32 lo, hi;
...@@ -35,16 +38,15 @@ static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key) ...@@ -35,16 +38,15 @@ static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key)
} }
/* /*
* Figure what we can cover with MCR's * Figure what we can cover with MCR's
* *
* Shortcut: We know you can't put 4Gig of RAM on a winchip * Shortcut: We know you can't put 4Gig of RAM on a winchip
*/ */
static u32 __cpuinit ramtop(void)
static u32 __cpuinit ramtop(void) /* 16388 */
{ {
int i;
u32 top = 0;
u32 clip = 0xFFFFFFFFUL; u32 clip = 0xFFFFFFFFUL;
u32 top = 0;
int i;
for (i = 0; i < e820.nr_map; i++) { for (i = 0; i < e820.nr_map; i++) {
unsigned long start, end; unsigned long start, end;
...@@ -52,13 +54,12 @@ static u32 __cpuinit ramtop(void) /* 16388 */ ...@@ -52,13 +54,12 @@ static u32 __cpuinit ramtop(void) /* 16388 */
if (e820.map[i].addr > 0xFFFFFFFFUL) if (e820.map[i].addr > 0xFFFFFFFFUL)
continue; continue;
/* /*
* Don't MCR over reserved space. Ignore the ISA hole * Don't MCR over reserved space. Ignore the ISA hole
* we frob around that catastrophe already * we frob around that catastrophe already
*/ */
if (e820.map[i].type == E820_RESERVED) {
if (e820.map[i].type == E820_RESERVED) if (e820.map[i].addr >= 0x100000UL &&
{ e820.map[i].addr < clip)
if (e820.map[i].addr >= 0x100000UL && e820.map[i].addr < clip)
clip = e820.map[i].addr; clip = e820.map[i].addr;
continue; continue;
} }
...@@ -69,28 +70,27 @@ static u32 __cpuinit ramtop(void) /* 16388 */ ...@@ -69,28 +70,27 @@ static u32 __cpuinit ramtop(void) /* 16388 */
if (end > top) if (end > top)
top = end; top = end;
} }
/* Everything below 'top' should be RAM except for the ISA hole. /*
Because of the limited MCR's we want to map NV/ACPI into our * Everything below 'top' should be RAM except for the ISA hole.
MCR range for gunk in RAM * Because of the limited MCR's we want to map NV/ACPI into our
* MCR range for gunk in RAM
Clip might cause us to MCR insufficient RAM but that is an *
acceptable failure mode and should only bite obscure boxes with * Clip might cause us to MCR insufficient RAM but that is an
a VESA hole at 15Mb * acceptable failure mode and should only bite obscure boxes with
* a VESA hole at 15Mb
The second case Clip sometimes kicks in is when the EBDA is marked *
as reserved. Again we fail safe with reasonable results * The second case Clip sometimes kicks in is when the EBDA is marked
*/ * as reserved. Again we fail safe with reasonable results
*/
if(top > clip) if (top > clip)
top = clip; top = clip;
return top; return top;
} }
/* /*
* Compute a set of MCR's to give maximum coverage * Compute a set of MCR's to give maximum coverage
*/ */
static int __cpuinit centaur_mcr_compute(int nr, int key) static int __cpuinit centaur_mcr_compute(int nr, int key)
{ {
u32 mem = ramtop(); u32 mem = ramtop();
...@@ -100,33 +100,31 @@ static int __cpuinit centaur_mcr_compute(int nr, int key) ...@@ -100,33 +100,31 @@ static int __cpuinit centaur_mcr_compute(int nr, int key)
u32 floor = 0; u32 floor = 0;
int ct = 0; int ct = 0;
while (ct < nr) while (ct < nr) {
{
u32 fspace = 0; u32 fspace = 0;
u32 high;
u32 low;
/* /*
* Find the largest block we will fill going upwards * Find the largest block we will fill going upwards
*/ */
high = power2(mem-top);
u32 high = power2(mem-top);
/* /*
* Find the largest block we will fill going downwards * Find the largest block we will fill going downwards
*/ */
low = base/2;
u32 low = base/2;
/* /*
* Don't fill below 1Mb going downwards as there * Don't fill below 1Mb going downwards as there
* is an ISA hole in the way. * is an ISA hole in the way.
*/ */
if (base <= 1024*1024) if (base <= 1024*1024)
low = 0; low = 0;
/* /*
* See how much space we could cover by filling below * See how much space we could cover by filling below
* the ISA hole * the ISA hole
*/ */
if (floor == 0) if (floor == 0)
...@@ -137,52 +135,48 @@ static int __cpuinit centaur_mcr_compute(int nr, int key) ...@@ -137,52 +135,48 @@ static int __cpuinit centaur_mcr_compute(int nr, int key)
/* And forget ROM space */ /* And forget ROM space */
/* /*
* Now install the largest coverage we get * Now install the largest coverage we get
*/ */
if (fspace > high && fspace > low) {
if (fspace > high && fspace > low)
{
centaur_mcr_insert(ct, floor, fspace, key); centaur_mcr_insert(ct, floor, fspace, key);
floor += fspace; floor += fspace;
} } else if (high > low) {
else if (high > low) {
centaur_mcr_insert(ct, top, high, key); centaur_mcr_insert(ct, top, high, key);
top += high; top += high;
} } else if (low > 0) {
else if (low > 0) {
base -= low; base -= low;
centaur_mcr_insert(ct, base, low, key); centaur_mcr_insert(ct, base, low, key);
} } else
else break; break;
ct++; ct++;
} }
/* /*
* We loaded ct values. We now need to set the mask. The caller * We loaded ct values. We now need to set the mask. The caller
* must do this bit. * must do this bit.
*/ */
return ct; return ct;
} }
static void __cpuinit centaur_create_optimal_mcr(void) static void __cpuinit centaur_create_optimal_mcr(void)
{ {
int used;
int i; int i;
/* /*
* Allocate up to 6 mcrs to mark as much of ram as possible * Allocate up to 6 mcrs to mark as much of ram as possible
* as write combining and weak write ordered. * as write combining and weak write ordered.
* *
* To experiment with: Linux never uses stack operations for * To experiment with: Linux never uses stack operations for
* mmio spaces so we could globally enable stack operation wc * mmio spaces so we could globally enable stack operation wc
* *
* Load the registers with type 31 - full write combining, all * Load the registers with type 31 - full write combining, all
* writes weakly ordered. * writes weakly ordered.
*/ */
int used = centaur_mcr_compute(6, 31); used = centaur_mcr_compute(6, 31);
/* /*
* Wipe unused MCRs * Wipe unused MCRs
*/ */
for (i = used; i < 8; i++) for (i = used; i < 8; i++)
wrmsr(MSR_IDT_MCR0+i, 0, 0); wrmsr(MSR_IDT_MCR0+i, 0, 0);
} }
...@@ -190,31 +184,30 @@ static void __cpuinit centaur_create_optimal_mcr(void) ...@@ -190,31 +184,30 @@ static void __cpuinit centaur_create_optimal_mcr(void)
static void __cpuinit winchip2_create_optimal_mcr(void) static void __cpuinit winchip2_create_optimal_mcr(void)
{ {
u32 lo, hi; u32 lo, hi;
int used;
int i; int i;
/* /*
* Allocate up to 6 mcrs to mark as much of ram as possible * Allocate up to 6 mcrs to mark as much of ram as possible
* as write combining, weak store ordered. * as write combining, weak store ordered.
* *
* Load the registers with type 25 * Load the registers with type 25
* 8 - weak write ordering * 8 - weak write ordering
* 16 - weak read ordering * 16 - weak read ordering
* 1 - write combining * 1 - write combining
*/ */
used = centaur_mcr_compute(6, 25);
int used = centaur_mcr_compute(6, 25);
/* /*
* Mark the registers we are using. * Mark the registers we are using.
*/ */
rdmsr(MSR_IDT_MCR_CTRL, lo, hi); rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
for (i = 0; i < used; i++) for (i = 0; i < used; i++)
lo |= 1<<(9+i); lo |= 1<<(9+i);
wrmsr(MSR_IDT_MCR_CTRL, lo, hi); wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
/* /*
* Wipe unused MCRs * Wipe unused MCRs
*/ */
for (i = used; i < 8; i++) for (i = used; i < 8; i++)
...@@ -222,9 +215,8 @@ static void __cpuinit winchip2_create_optimal_mcr(void) ...@@ -222,9 +215,8 @@ static void __cpuinit winchip2_create_optimal_mcr(void)
} }
/* /*
* Handle the MCR key on the Winchip 2. * Handle the MCR key on the Winchip 2.
*/ */
static void __cpuinit winchip2_unprotect_mcr(void) static void __cpuinit winchip2_unprotect_mcr(void)
{ {
u32 lo, hi; u32 lo, hi;
...@@ -301,28 +293,29 @@ static void __cpuinit init_c3(struct cpuinfo_x86 *c) ...@@ -301,28 +293,29 @@ static void __cpuinit init_c3(struct cpuinfo_x86 *c)
display_cacheinfo(c); display_cacheinfo(c);
} }
enum {
ECX8 = 1<<1,
EIERRINT = 1<<2,
DPM = 1<<3,
DMCE = 1<<4,
DSTPCLK = 1<<5,
ELINEAR = 1<<6,
DSMC = 1<<7,
DTLOCK = 1<<8,
EDCTLB = 1<<8,
EMMX = 1<<9,
DPDC = 1<<11,
EBRPRED = 1<<12,
DIC = 1<<13,
DDC = 1<<14,
DNA = 1<<15,
ERETSTK = 1<<16,
E2MMX = 1<<19,
EAMD3D = 1<<20,
};
static void __cpuinit init_centaur(struct cpuinfo_x86 *c) static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
{ {
enum {
ECX8 = 1<<1,
EIERRINT = 1<<2,
DPM = 1<<3,
DMCE = 1<<4,
DSTPCLK = 1<<5,
ELINEAR = 1<<6,
DSMC = 1<<7,
DTLOCK = 1<<8,
EDCTLB = 1<<8,
EMMX = 1<<9,
DPDC = 1<<11,
EBRPRED = 1<<12,
DIC = 1<<13,
DDC = 1<<14,
DNA = 1<<15,
ERETSTK = 1<<16,
E2MMX = 1<<19,
EAMD3D = 1<<20,
};
char *name; char *name;
u32 fcr_set = 0; u32 fcr_set = 0;
...@@ -330,126 +323,137 @@ static void __cpuinit init_centaur(struct cpuinfo_x86 *c) ...@@ -330,126 +323,137 @@ static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
u32 lo, hi, newlo; u32 lo, hi, newlo;
u32 aa, bb, cc, dd; u32 aa, bb, cc, dd;
/* Bit 31 in normal CPUID used for nonstandard 3DNow ID; /*
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
*/
clear_bit(0*32+31, c->x86_capability); clear_bit(0*32+31, c->x86_capability);
switch (c->x86) { switch (c->x86) {
case 5: case 5:
switch (c->x86_model) { switch (c->x86_model) {
case 4: case 4:
name = "C6"; name = "C6";
fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK; fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
fcr_clr = DPDC; fcr_clr = DPDC;
printk(KERN_NOTICE "Disabling bugged TSC.\n"); printk(KERN_NOTICE "Disabling bugged TSC.\n");
clear_bit(X86_FEATURE_TSC, c->x86_capability); clear_bit(X86_FEATURE_TSC, c->x86_capability);
#ifdef CONFIG_X86_OOSTORE #ifdef CONFIG_X86_OOSTORE
centaur_create_optimal_mcr(); centaur_create_optimal_mcr();
/* Enable /*
write combining on non-stack, non-string * Enable:
write combining on string, all types * write combining on non-stack, non-string
weak write ordering * write combining on string, all types
* weak write ordering
The C6 original lacks weak read order *
* The C6 original lacks weak read order
Note 0x120 is write only on Winchip 1 */ *
* Note 0x120 is write only on Winchip 1
wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0); */
wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
#endif #endif
break;
case 8:
switch (c->x86_mask) {
default:
name = "2";
break; break;
case 8: case 7 ... 9:
switch (c->x86_mask) { name = "2A";
default: break;
name = "2"; case 10 ... 15:
break; name = "2B";
case 7 ... 9: break;
name = "2A"; }
break; fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
case 10 ... 15: E2MMX|EAMD3D;
name = "2B"; fcr_clr = DPDC;
break;
}
fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
fcr_clr = DPDC;
#ifdef CONFIG_X86_OOSTORE #ifdef CONFIG_X86_OOSTORE
winchip2_unprotect_mcr(); winchip2_unprotect_mcr();
winchip2_create_optimal_mcr(); winchip2_create_optimal_mcr();
rdmsr(MSR_IDT_MCR_CTRL, lo, hi); rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
/* Enable /*
write combining on non-stack, non-string * Enable:
write combining on string, all types * write combining on non-stack, non-string
weak write ordering * write combining on string, all types
*/ * weak write ordering
lo |= 31; */
wrmsr(MSR_IDT_MCR_CTRL, lo, hi); lo |= 31;
winchip2_protect_mcr(); wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
winchip2_protect_mcr();
#endif #endif
break; break;
case 9: case 9:
name = "3"; name = "3";
fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D; fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
fcr_clr = DPDC; E2MMX|EAMD3D;
fcr_clr = DPDC;
#ifdef CONFIG_X86_OOSTORE #ifdef CONFIG_X86_OOSTORE
winchip2_unprotect_mcr(); winchip2_unprotect_mcr();
winchip2_create_optimal_mcr(); winchip2_create_optimal_mcr();
rdmsr(MSR_IDT_MCR_CTRL, lo, hi); rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
/* Enable /*
write combining on non-stack, non-string * Enable:
write combining on string, all types * write combining on non-stack, non-string
weak write ordering * write combining on string, all types
*/ * weak write ordering
lo |= 31; */
wrmsr(MSR_IDT_MCR_CTRL, lo, hi); lo |= 31;
winchip2_protect_mcr(); wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
winchip2_protect_mcr();
#endif #endif
break; break;
default: default:
name = "??"; name = "??";
} }
rdmsr(MSR_IDT_FCR1, lo, hi); rdmsr(MSR_IDT_FCR1, lo, hi);
newlo = (lo|fcr_set) & (~fcr_clr); newlo = (lo|fcr_set) & (~fcr_clr);
if (newlo != lo) { if (newlo != lo) {
printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n", lo, newlo); printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n",
wrmsr(MSR_IDT_FCR1, newlo, hi); lo, newlo);
} else { wrmsr(MSR_IDT_FCR1, newlo, hi);
printk(KERN_INFO "Centaur FCR is 0x%X\n", lo); } else {
} printk(KERN_INFO "Centaur FCR is 0x%X\n", lo);
/* Emulate MTRRs using Centaur's MCR. */ }
set_bit(X86_FEATURE_CENTAUR_MCR, c->x86_capability); /* Emulate MTRRs using Centaur's MCR. */
/* Report CX8 */ set_bit(X86_FEATURE_CENTAUR_MCR, c->x86_capability);
set_bit(X86_FEATURE_CX8, c->x86_capability); /* Report CX8 */
/* Set 3DNow! on Winchip 2 and above. */ set_bit(X86_FEATURE_CX8, c->x86_capability);
if (c->x86_model >= 8) /* Set 3DNow! on Winchip 2 and above. */
set_bit(X86_FEATURE_3DNOW, c->x86_capability); if (c->x86_model >= 8)
/* See if we can find out some more. */ set_bit(X86_FEATURE_3DNOW, c->x86_capability);
if (cpuid_eax(0x80000000) >= 0x80000005) { /* See if we can find out some more. */
/* Yes, we can. */ if (cpuid_eax(0x80000000) >= 0x80000005) {
cpuid(0x80000005, &aa, &bb, &cc, &dd); /* Yes, we can. */
/* Add L1 data and code cache sizes. */ cpuid(0x80000005, &aa, &bb, &cc, &dd);
c->x86_cache_size = (cc>>24)+(dd>>24); /* Add L1 data and code cache sizes. */
} c->x86_cache_size = (cc>>24)+(dd>>24);
sprintf(c->x86_model_id, "WinChip %s", name); }
break; sprintf(c->x86_model_id, "WinChip %s", name);
break;
case 6: case 6:
init_c3(c); init_c3(c);
break; break;
} }
} }
static unsigned int __cpuinit centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size) static unsigned int __cpuinit
centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{ {
/* VIA C3 CPUs (670-68F) need further shifting. */ /* VIA C3 CPUs (670-68F) need further shifting. */
if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
size >>= 8; size >>= 8;
/* VIA also screwed up Nehemiah stepping 1, and made /*
it return '65KB' instead of '64KB' * There's also an erratum in Nehemiah stepping 1, which
- Note, it seems this may only be in engineering samples. */ * returns '65KB' instead of '64KB'
if ((c->x86 == 6) && (c->x86_model == 9) && (c->x86_mask == 1) && (size == 65)) * - Note, it seems this may only be in engineering samples.
*/
if ((c->x86 == 6) && (c->x86_model == 9) &&
(c->x86_mask == 1) && (size == 65))
size -= 1; size -= 1;
return size; return size;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7