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Commit f215347c authored by Edward Cree's avatar Edward Cree Committed by David S. Miller
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sfc: update MCDI protocol headers 

Signed-off-by: default avatarEdward Cree <ecree@solarflare.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e676d81c
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Showing with 1776 additions and 1046 deletions
drivers/net/ethernet/sfc/mcdi_pcol.h
View file @ f215347c
......@@ -273,7 +273,8 @@
#define MC_CMD_ERR_NO_PRIVILEGE 0x1013
/* Workaround 26807 could not be turned on/off because some functions
* have already installed filters. See the comment at
* MC_CMD_WORKAROUND_BUG26807. */
* MC_CMD_WORKAROUND_BUG26807.
* May also returned for other operations such as sub-variant switching. */
#define MC_CMD_ERR_FILTERS_PRESENT 0x1014
/* The clock whose frequency you've attempted to set set
* doesn't exist on this NIC */
......@@ -292,6 +293,10 @@
* away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the
* datapath absence may be temporary*/
#define MC_CMD_ERR_NO_DATAPATH 0x1019
/* The operation could not complete because some VIs are allocated */
#define MC_CMD_ERR_VIS_PRESENT 0x101a
/* The operation could not complete because some PIO buffers are allocated */
#define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
#define MC_CMD_ERR_CODE_OFST 0
......@@ -312,10 +317,17 @@
#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
#define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
/* Points to the recovery mode entry point. */
/* Points to the recovery mode entry point. Misnamed but kept for compatibility. */
#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
#define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
/* Points to the recovery mode entry point. Same as above, but the right name. */
#define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
#define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
#define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
/* Points to noflash mode entry point. */
#define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
/* The command set exported by the boot ROM (MCDI v0) */
#define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \
......@@ -1002,7 +1014,9 @@
/***********************************/
/* MC_CMD_READ32
* Read multiple 32byte words from MC memory.
* Read multiple 32byte words from MC memory. Note - this command really
* belongs to INSECURE category but is required by shmboot. The command handler
* has additional checks to reject insecure calls.
*/
#define MC_CMD_READ32 0x1
......@@ -1050,7 +1064,9 @@
/***********************************/
/* MC_CMD_COPYCODE
* Copy MC code between two locations and jump.
* Copy MC code between two locations and jump. Note - this command really
* belongs to INSECURE category but is required by shmboot. The command handler
* has additional checks to reject insecure calls.
*/
#define MC_CMD_COPYCODE 0x3
......@@ -1555,11 +1571,10 @@
#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
/* MC_CMD_PTP_IN_RESET_STATS msgrequest */
/* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */
#define MC_CMD_PTP_IN_RESET_STATS_LEN 8
/* MC_CMD_PTP_IN_CMD_OFST 0 */
/* MC_CMD_PTP_IN_CMD_LEN 4 */
/* Reset PTP statistics */
/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
......@@ -1710,11 +1725,10 @@
/* enum: External. */
#define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
/* MC_CMD_PTP_IN_RST_CLK msgrequest */
/* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */
#define MC_CMD_PTP_IN_RST_CLK_LEN 8
/* MC_CMD_PTP_IN_CMD_OFST 0 */
/* MC_CMD_PTP_IN_CMD_LEN 4 */
/* Reset value of Timer Reg. */
/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
......@@ -2687,8 +2701,16 @@
#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
#define MC_CMD_DRV_ATTACH_LBN 0
#define MC_CMD_DRV_ATTACH_WIDTH 1
#define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
#define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1
#define MC_CMD_DRV_PREBOOT_LBN 1
#define MC_CMD_DRV_PREBOOT_WIDTH 1
#define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1
#define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1
#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2
#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1
#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3
#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1
/* 1 to set new state, or 0 to just report the existing state */
#define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
#define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
......@@ -2711,6 +2733,12 @@
* support
*/
#define MC_CMD_FW_RULES_ENGINE 0x5
/* enum: Prefer to use firmware with additional DPDK support */
#define MC_CMD_FW_DPDK 0x6
/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
* bug69716)
*/
#define MC_CMD_FW_L3XUDP 0x7
/* enum: Only this option is allowed for non-admin functions */
#define MC_CMD_FW_DONT_CARE 0xffffffff
......@@ -2740,6 +2768,11 @@
* refers to the Sorrento external FPGA port.
*/
#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
/* enum: If set, indicates that VI spreading is currently enabled. Will always
* indicate the current state, regardless of the value in the WANT_VI_SPREADING
* input.
*/
#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
/***********************************/
......@@ -3537,6 +3570,37 @@
/* Enum values, see field(s): */
/* 100M */
/* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */
#define AN_TYPE_LEN 4
#define AN_TYPE_TYPE_OFST 0
#define AN_TYPE_TYPE_LEN 4
/* enum: None, AN disabled or not supported */
#define MC_CMD_AN_NONE 0x0
/* enum: Clause 28 - BASE-T */
#define MC_CMD_AN_CLAUSE28 0x1
/* enum: Clause 37 - BASE-X */
#define MC_CMD_AN_CLAUSE37 0x2
/* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
* assemblies. Includes Clause 72/Clause 92 link-training.
*/
#define MC_CMD_AN_CLAUSE73 0x3
#define AN_TYPE_TYPE_LBN 0
#define AN_TYPE_TYPE_WIDTH 32
/* FEC_TYPE structuredef: Forward error correction types defined in IEEE802.3
*/
#define FEC_TYPE_LEN 4
#define FEC_TYPE_TYPE_OFST 0
#define FEC_TYPE_TYPE_LEN 4
/* enum: No FEC */
#define MC_CMD_FEC_NONE 0x0
/* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
#define MC_CMD_FEC_BASER 0x1
/* enum: Clause 91/Clause 108 Reed-Solomon FEC */
#define MC_CMD_FEC_RS 0x2
#define FEC_TYPE_TYPE_LBN 0
#define FEC_TYPE_TYPE_WIDTH 32
/***********************************/
/* MC_CMD_GET_LINK
......@@ -3552,10 +3616,14 @@
/* MC_CMD_GET_LINK_OUT msgresponse */
#define MC_CMD_GET_LINK_OUT_LEN 28
/* near-side advertised capabilities */
/* Near-side advertised capabilities. Refer to
* MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
*/
#define MC_CMD_GET_LINK_OUT_CAP_OFST 0
#define MC_CMD_GET_LINK_OUT_CAP_LEN 4
/* link-partner advertised capabilities */
/* Link-partner advertised capabilities. Refer to
* MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
*/
#define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
#define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
/* Autonegotiated speed in mbit/s. The link may still be down even if this
......@@ -3598,6 +3666,97 @@
#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
/* MC_CMD_GET_LINK_OUT_V2 msgresponse: Extended link state information */
#define MC_CMD_GET_LINK_OUT_V2_LEN 44
/* Near-side advertised capabilities. Refer to
* MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
*/
#define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0
#define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4
/* Link-partner advertised capabilities. Refer to
* MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
*/
#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4
#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4
/* Autonegotiated speed in mbit/s. The link may still be down even if this
* reads non-zero.
*/
#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_OFST 8
#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4
/* Current loopback setting. */
#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_OFST 12
#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4
/* Enum values, see field(s): */
/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
#define MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 16
#define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1
#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 2
#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 3
#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 6
#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 7
#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1
/* This returns the negotiated flow control value. */
#define MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20
#define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
/* Enum values, see field(s): */
/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24
#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
/* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
/* MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */
/* MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */
/* MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */
/* MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */
/* MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */
/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */
/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */
/* True local device capabilities (taking into account currently used PMD/MDI,
* e.g. plugged-in module). In general, subset of
* MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP, but may include extra _FEC_REQUEST
* bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal
* to SUPPORTED_CAP for non-pluggable PMDs. Refer to
* MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
*/
#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_OFST 28
#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4
/* Auto-negotiation type used on the link */
#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_OFST 32
#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4
/* Enum values, see field(s): */
/* AN_TYPE/TYPE */
/* Forward error correction used on the link */
#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_OFST 36
#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4
/* Enum values, see field(s): */
/* FEC_TYPE/TYPE */
#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 40
#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1
#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 2
#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 3
#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 5
#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 6
#define MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 7
#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1
#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8
#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1
/***********************************/
/* MC_CMD_SET_LINK
......@@ -3610,7 +3769,9 @@
/* MC_CMD_SET_LINK_IN msgrequest */
#define MC_CMD_SET_LINK_IN_LEN 16
/* ??? */
/* Near-side advertised capabilities. Refer to
* MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
*/
#define MC_CMD_SET_LINK_IN_CAP_OFST 0
#define MC_CMD_SET_LINK_IN_CAP_LEN 4
/* Flags */
......@@ -4515,6 +4676,8 @@
#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
#define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
#define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5
#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1
#define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6
......@@ -4542,6 +4705,8 @@
#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5
#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1
#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7
......@@ -4560,7 +4725,11 @@
/* MC_CMD_NVRAM_UPDATE_START
* Start a group of update operations on a virtual NVRAM partition. Locks
* required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
* PHY_LOCK required and not held).
* PHY_LOCK required and not held). In an adapter bound to a TSA controller,
* MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types
* i.e. static config, dynamic config and expansion ROM config. Attempting to
* perform this operation on a restricted partition will return the error
* EPERM.
*/
#define MC_CMD_NVRAM_UPDATE_START 0x38
......@@ -4720,8 +4889,12 @@
/***********************************/
/* MC_CMD_NVRAM_UPDATE_FINISH
* Finish a group of update operations on a virtual NVRAM partition. Locks
* required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad
* type/offset/length), EACCES (if PHY_LOCK required and not held)
* required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/
* length), EACCES (if PHY_LOCK required and not held). In an adapter bound to
* a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of
* partition types i.e. static config, dynamic config and expansion ROM config.
* Attempting to perform this operation on a restricted partition will return
* the error EPERM.
*/
#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
......@@ -5053,7 +5226,7 @@
#define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
/* enum: Port 1 PHY power switch over-current: bool */
#define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
/* enum: Mop-up microcontroller reference voltage (millivolts) */
/* enum: Mop-up microcontroller reference voltage: mV */
#define MC_CMD_SENSOR_MUM_VCC 0x30
/* enum: 0.9v power phase A voltage: mV */
#define MC_CMD_SENSOR_IN_0V9_A 0x31
......@@ -7157,11 +7330,15 @@
/* Size, in entries */
#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4
/* The EVQ to send events to. This is an index originally specified to INIT_EVQ
/* The EVQ to send events to. This is an index originally specified to
* INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
*/
#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
/* The value to put in the event data. Check hardware spec. for valid range. */
/* The value to put in the event data. Check hardware spec. for valid range.
* This field is ignored if DMA_MODE == EQUAL_STRIDE_PACKED_STREAM or DMA_MODE
* == PACKED_STREAM.
*/
#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
......@@ -7192,6 +7369,13 @@
#define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
/* enum: Pack multiple packets into large descriptors using the format designed
* to maximise packet rate. This mode uses 1 "bucket" per descriptor with
* multiple fixed-size packet buffers within each bucket. For a full
* description see SF-119419-TC. This mode is only supported by "dpdk" datapath
* firmware.
*/
#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14
#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
......@@ -7221,12 +7405,122 @@
#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540
#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
/* MC_CMD_INIT_RXQ_V3_IN msgrequest */
#define MC_CMD_INIT_RXQ_V3_IN_LEN 560
/* Size, in entries */
#define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0
#define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4
/* The EVQ to send events to. This is an index originally specified to
* INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
*/
#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4
#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4
/* The value to put in the event data. Check hardware spec. for valid range.
* This field is ignored if DMA_MODE == EQUAL_STRIDE_PACKED_STREAM or DMA_MODE
* == PACKED_STREAM.
*/
#define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
* local queue index.
*/
#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
/* There will be more flags here. */
#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16
#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1
#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3
#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1
#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10
#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
/* enum: One packet per descriptor (for normal networking) */
#define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
/* enum: Pack multiple packets into large descriptors using the format designed
* to maximise packet rate. This mode uses 1 "bucket" per descriptor with
* multiple fixed-size packet buffers within each bucket. For a full
* description see SF-119419-TC. This mode is only supported by "dpdk" datapath
* firmware.
*/
#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19
#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
/* Owner ID to use if in buffer mode (zero if physical) */
#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20
#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
/* The port ID associated with the v-adaptor which should contain this DMAQ. */
#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 24
#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4
/* 64-bit address of 4k of 4k-aligned host memory buffer */
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540
#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4
/* The number of packet buffers that will be contained within each
* EQUAL_STRIDE_PACKED_STREAM format bucket supplied by the driver. This field
* is ignored unless DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
*/
#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
/* The length in bytes of the area in each packet buffer that can be written to
* by the adapter. This is used to store the packet prefix and the packet
* payload. This length does not include any end padding added by the driver.
* This field is ignored unless DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
*/
#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 548
#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4
/* The length in bytes of a single packet buffer within a
* EQUAL_STRIDE_PACKED_STREAM format bucket. This field is ignored unless
* DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
*/
#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 552
#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4
/* The maximum time in nanoseconds that the datapath will be backpressured if
* there are no RX descriptors available. If the timeout is reached and there
* are still no descriptors then the packet will be dropped. A timeout of 0
* means the datapath will never be blocked. This field is ignored unless
* DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
*/
#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
/* MC_CMD_INIT_RXQ_OUT msgresponse */
#define MC_CMD_INIT_RXQ_OUT_LEN 0
/* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */
#define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
/* MC_CMD_INIT_RXQ_V3_OUT msgresponse */
#define MC_CMD_INIT_RXQ_V3_OUT_LEN 0
/***********************************/
/* MC_CMD_INIT_TXQ
......@@ -8131,6 +8425,273 @@
#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156
#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16
/* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional
* filter actions for Intel's DPDK (Data Plane Development Kit, dpdk.org) via
* its rte_flow API. This extension is only useful with the sfc_efx driver
* included as part of DPDK, used in conjunction with the dpdk datapath
* firmware variant.
*/
#define MC_CMD_FILTER_OP_V3_IN_LEN 180
/* identifies the type of operation requested */
#define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0
#define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4
/* Enum values, see field(s): */
/* MC_CMD_FILTER_OP_IN/OP */
/* filter handle (for remove / unsubscribe operations) */
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8
/* The port ID associated with the v-adaptor which should contain this filter.
*/
#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12
#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4
/* fields to include in match criteria */
#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16
#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4
#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0
#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2
#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3
#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4
#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5
#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7
#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8
#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10
#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11
#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
/* receive destination */
#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 20
#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4
/* enum: drop packets */
#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
/* enum: receive to host */
#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
/* enum: receive to MC */
#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
/* enum: loop back to TXDP 0 */
#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
/* enum: loop back to TXDP 1 */
#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
/* receive queue handle (for multiple queue modes, this is the base queue) */
#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 24
#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4
/* receive mode */
#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 28
#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4
/* enum: receive to just the specified queue */
#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
/* enum: receive to multiple queues using RSS context */
#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
/* enum: receive to multiple queues using .1p mapping */
#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
/* enum: install a filter entry that will never match; for test purposes only
*/
#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
* RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
* MC_CMD_DOT1P_MAPPING_ALLOC.
*/
#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 32
#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4
/* transmit domain (reserved; set to 0) */
#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 36
#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4
/* transmit destination (either set the MAC and/or PM bits for explicit
* control, or set this field to TX_DEST_DEFAULT for sensible default
* behaviour)
*/
#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 40
#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
/* enum: request default behaviour (based on filter type) */
#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1
#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1
#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1
/* source MAC address to match (as bytes in network order) */
#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 44
#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 6
/* source port to match (as bytes in network order) */
#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 50
#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 2
/* destination MAC address to match (as bytes in network order) */
#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 52
#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 6
/* destination port to match (as bytes in network order) */
#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 58
#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 2
/* Ethernet type to match (as bytes in network order) */
#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 60
#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 2
/* Inner VLAN tag to match (as bytes in network order) */
#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 62
#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 2
/* Outer VLAN tag to match (as bytes in network order) */
#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 64
#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 2
/* IP protocol to match (in low byte; set high byte to 0) */
#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 66
#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 2
/* Firmware defined register 0 to match (reserved; set to 0) */
#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 68
#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4
/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
* protocol is GRE) to match (as bytes in network order; set last byte to 0 for
* VXLAN/NVGRE, or 1 for Geneve)
*/
#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72
#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4
#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0
#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24
#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24
#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8
/* enum: Match VXLAN traffic with this VNI */
#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
/* enum: Match Geneve traffic with this VNI */
#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
/* enum: Reserved for experimental development use */
#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24
#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24
#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8
/* enum: Match NVGRE traffic with this VSID */
#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
/* source IP address to match (as bytes in network order; set last 12 bytes to
* 0 for IPv4 address)
*/
#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 76
#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 16
/* destination IP address to match (as bytes in network order; set last 12
* bytes to 0 for IPv4 address)
*/
#define MC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 92
#define MC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 16
/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
* order)
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 108
#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 6
/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 114
#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 2
/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
* network order)
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 116
#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 6
/* VXLAN/NVGRE inner frame destination port to match (as bytes in network
* order)
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 122
#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 2
/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 124
#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 2
/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 126
#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 2
/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 128
#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 2
/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
* 0)
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 130
#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 2
/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
* to 0)
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 132
#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4
/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
* to 0)
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 136
#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4
/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
* order; set last 12 bytes to 0 for IPv4 address)
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 140
#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 16
/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
* order; set last 12 bytes to 0 for IPv4 address)
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156
#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16
/* Set an action for all packets matching this filter. The DPDK driver and dpdk
* f/w variant use their own specific delivery structures, which are documented
* in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything
* other than MATCH_ACTION_NONE when the NIC is running another f/w variant
* will cause the filter insertion to fail with ENOTSUP.
*/
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4
/* enum: do nothing extra */
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
/* enum: Set the match flag in the packet prefix for packets matching the
* filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
* support the DPDK rte_flow "FLAG" action.
*/
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
/* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching
* the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
* support the DPDK rte_flow "MARK" action.
*/
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
/* the mark value for MATCH_ACTION_MARK */
#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176
#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
/* MC_CMD_FILTER_OP_OUT msgresponse */
#define MC_CMD_FILTER_OP_OUT_LEN 12
/* identifies the type of operation requested */
......@@ -8238,7 +8799,9 @@
* Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging.
* Please note that this interface is only of use to debug tools which have
* knowledge of firmware and hardware data structures; nothing here is intended
* for use by normal driver code.
* for use by normal driver code. Note that although this command is in the
* Admin privilege group, in tamperproof adapters, only read operations are
* permitted.
*/
#define MC_CMD_PARSER_DISP_RW 0xe5
......@@ -8272,9 +8835,13 @@
#define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4
/* enum: Read a word of DICPU DMEM or a LUE entry */
#define MC_CMD_PARSER_DISP_RW_IN_READ 0x0
/* enum: Write a word of DICPU DMEM or a LUE entry. */
/* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on
* tamperproof adapters.
*/
#define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
/* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). */
/* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not
* permitted on tamperproof adapters.
*/
#define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
/* data memory address (DICPU targets) or LUE index (LUE targets) */
#define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8
......@@ -9094,6 +9661,8 @@
#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
/* enum: Rules engine RXDP firmware */
#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
/* enum: DPDK RXDP firmware */
#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
/* enum: BIST RXDP firmware */
#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
/* enum: RXDP Test firmware image 1 */
......@@ -9127,6 +9696,8 @@
#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
/* enum: Rules engine TXDP firmware */
#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
/* enum: DPDK TXDP firmware */
#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
/* enum: BIST TXDP firmware */
#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
/* enum: TXDP Test firmware image 1 */
......@@ -9171,8 +9742,10 @@
#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
/* enum: Rules engine RX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
/* enum: reserved value - do not use (bug69716) */
#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED_9 0x9
/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9
/* enum: DPDK RX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
/* enum: RX PD firmware parsing but not filtering network overlay tunnel
......@@ -9212,8 +9785,10 @@
#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
/* enum: Rules engine TX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
/* enum: reserved value - do not use (bug69716) */
#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED_9 0x9
/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9
/* enum: DPDK TX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
/* Hardware capabilities of NIC */
......@@ -9300,6 +9875,8 @@
#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
/* enum: Rules engine RXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
/* enum: DPDK RXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
/* enum: BIST RXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
/* enum: RXDP Test firmware image 1 */
......@@ -9333,6 +9910,8 @@
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
/* enum: Rules engine TXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
/* enum: DPDK TXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
/* enum: BIST TXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
/* enum: TXDP Test firmware image 1 */
......@@ -9377,8 +9956,10 @@
#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
/* enum: Rules engine RX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
/* enum: reserved value - do not use (bug69716) */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED_9 0x9
/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9
/* enum: DPDK RX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
/* enum: RX PD firmware parsing but not filtering network overlay tunnel
......@@ -9418,8 +9999,10 @@
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
/* enum: Rules engine TX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
/* enum: reserved value - do not use (bug69716) */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED_9 0x9
/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9
/* enum: DPDK TX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
/* Hardware capabilities of NIC */
......@@ -9469,6 +10052,18 @@
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 19
#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 20
#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 22
#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 24
#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1
/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
* on older firmware (check the length).
*/
......@@ -9599,6 +10194,8 @@
#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
/* enum: Rules engine RXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
/* enum: DPDK RXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
/* enum: BIST RXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
/* enum: RXDP Test firmware image 1 */
......@@ -9632,6 +10229,8 @@
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
/* enum: Rules engine TXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
/* enum: DPDK TXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
/* enum: BIST TXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
/* enum: TXDP Test firmware image 1 */
......@@ -9676,8 +10275,10 @@
#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
/* enum: Rules engine RX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
/* enum: reserved value - do not use (bug69716) */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED_9 0x9
/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9
/* enum: DPDK RX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
/* enum: RX PD firmware parsing but not filtering network overlay tunnel
......@@ -9717,8 +10318,10 @@
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
/* enum: Rules engine TX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
/* enum: reserved value - do not use (bug69716) */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED_9 0x9
/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9
/* enum: DPDK TX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
/* Hardware capabilities of NIC */
......@@ -9768,6 +10371,18 @@
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 19
#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 20
#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 22
#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 24
#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1
/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
* on older firmware (check the length).
*/
......@@ -9923,6 +10538,8 @@
#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
/* enum: Rules engine RXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
/* enum: DPDK RXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
/* enum: BIST RXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
/* enum: RXDP Test firmware image 1 */
......@@ -9956,6 +10573,8 @@
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
/* enum: Rules engine TXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
/* enum: DPDK TXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
/* enum: BIST TXDP firmware */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
/* enum: TXDP Test firmware image 1 */
......@@ -10000,8 +10619,10 @@
#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
/* enum: Rules engine RX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
/* enum: reserved value - do not use (bug69716) */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED_9 0x9
/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9
/* enum: DPDK RX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
/* enum: RX PD firmware parsing but not filtering network overlay tunnel
......@@ -10041,8 +10662,10 @@
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
/* enum: Rules engine TX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
/* enum: reserved value - do not use (bug69716) */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED_9 0x9
/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9
/* enum: DPDK TX PD production firmware */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
/* Hardware capabilities of NIC */
......@@ -10092,6 +10715,18 @@
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 19
#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 20
#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 22
#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 24
#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1
/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
* on older firmware (check the length).
*/
......@@ -10201,7 +10836,16 @@
#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
#define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
#define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6
#define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2
/* Type of command/response */
#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28
#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
/* enum: MCDI command directed to or response originating from the MC. */
#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
/* enum: MCDI command directed to a TSA controller. MCDI responses of this type
* are not defined.
*/
#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
/***********************************/
......@@ -12051,6 +12695,10 @@
#define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
/* enum: Read Figure Of Merit (eye quality, higher is better). */
#define MC_CMD_KR_TUNE_IN_READ_FOM 0x7
/* enum: Start/stop link training frames */
#define MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8
/* enum: Issue KR link training command (control training coefficients) */
#define MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9
/* Align the arguments to 32 bits */
#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1
#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3
......@@ -12345,9 +12993,12 @@
/* Align the arguments to 32 bits */
#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1
#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3
/* Port-relative lane to scan eye on */
#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4
#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4
#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0
#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_WIDTH 8
#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_LBN 31
#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1
/* Scan duration / cycle count */
#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8
#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4
......@@ -12383,12 +13034,91 @@
#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3
#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4
#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4
#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0
#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_WIDTH 8
#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_LBN 31
#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1
/* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */
#define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4
#define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0
#define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4
/* MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN msgrequest */
#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_LEN 8
/* Requested operation */
#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0
#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_LEN 1
/* Align the arguments to 32 bits */
#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_OFST 1
#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_LEN 3
#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4
#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4
#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */
#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */
/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN msgrequest */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LEN 28
/* Requested operation */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_LEN 1
/* Align the arguments to 32 bits */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_OFST 1
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_LEN 3
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4
/* Set INITIALIZE state */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_OFST 8
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4
/* Set PRESET state */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_OFST 12
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4
/* C(-1) request */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_OFST 16
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */
/* C(0) request */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_OFST 20
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4
/* Enum values, see field(s): */
/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
/* C(+1) request */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_OFST 24
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4
/* Enum values, see field(s): */
/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT msgresponse */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_LEN 24
/* C(-1) status */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */
/* C(0) status */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4
/* Enum values, see field(s): */
/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
/* C(+1) status */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_OFST 8
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4
/* Enum values, see field(s): */
/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
/* C(-1) value */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_OFST 12
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4
/* C(0) value */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_OFST 16
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4
/* C(+1) status */
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_OFST 20
#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4
/***********************************/
/* MC_CMD_PCIE_TUNE
......@@ -13146,7 +13876,7 @@
*/
#define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
#define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
#define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
/* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */
#define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0
......@@ -13300,7 +14030,7 @@
*/
#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
#define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
#define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */
#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0
......@@ -14269,7 +14999,7 @@
*/
#define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
#define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
#define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
/* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */
#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20
......@@ -14320,7 +15050,7 @@
*/
#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
#define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
#define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
/* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */
#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20
......@@ -14372,7 +15102,7 @@
*/
#define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
#define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
#define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
/* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */
#define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4
......@@ -14391,7 +15121,7 @@
*/
#define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
#define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_ADMIN
#define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL
/* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */
#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4
......@@ -14410,7 +15140,7 @@
*/
#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
#define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_ADMIN
#define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL
/* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */
#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0
......
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