Staging: bcm: DDRInit: fixed issues w/ indentation.

restructured the levels of indentation to follow the linux
kernel coding style thus fixing checkpatch errors and warnings
respectfully.
Signed-off-by: Gary Alan Rookard <garyrookard@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

drivers/staging/bcm/DDRInit.c

@@ -62,7 +62,7 @@ static struct bcm_ddr_setting asT3_DDRSetting133MHz[] = {//      # DPLL Clock Se
 	{0x0F00A000, 0x00000016},
 	//# Enable start bit within memory controller
 	{0x0F007018, 0x01010000}
-                                        };
+};
 //80Mhz
 #define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10  //index for 0x0F007000
 static struct bcm_ddr_setting asT3_DDRSetting80MHz[] = {//   # DPLL Clock Setting
@@ -114,7 +114,7 @@ static struct bcm_ddr_setting asT3_DDRSetting80MHz[] = {//   # DPLL Clock Settin
 	{0x0F007094, 0x00000104},
 	//# Enable start bit within memory controller
 	{0x0F007018, 0x01010000}
-                                };
+};
 //100Mhz
 #define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13  //index for 0x0F007000
 static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {//  # DPLL Clock Setting
@@ -173,7 +173,7 @@ static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {//  # DPLL Clock Settin
 	{0x0F007094, 0x00000104},
 	//# Enable start bit within memory controller
 	{0x0F007018, 0x01010000}
-                                };
+};
 
 //Net T3B DDR Settings
 //DDR INIT-133Mhz
@@ -186,7 +186,7 @@ static struct bcm_ddr_setting asDPLL_266MHZ[] = {
 	// Changed source for X-bar and MIPS clock to APLL
 	{0x0f000840, 0x0FFF1B00},
 	{0x0f000870, 0x00000002}
-									  };
+};
 
 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11  //index for 0x0F007000
 static struct bcm_ddr_setting asT3B_DDRSetting133MHz[] = {//      # DPLL Clock Setting
@@ -297,7 +297,7 @@ static struct bcm_ddr_setting asT3B_DDRSetting80MHz[] = {//       # DPLL Clock S
 	{0x0F007094, 0x00000104},
 	//# Enable start bit within memory controller
 	{0x0F007018, 0x01010000}
-								};
+};
 
 //100Mhz
 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9  //index for 0x0F007000
@@ -352,7 +352,7 @@ static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {//      # DPLL Clock S
 	{0x0F007094, 0x00000104},
 	//# Enable start bit within memory controller
 	{0x0F007018, 0x01010000}
-							};
+};
 
 
 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9  //index for 0x0F007000