Commit f3e8d1da authored by Ralf Baechle's avatar Ralf Baechle

[MIPS] Alchemy: Fix build by conversion to irq_cpu.c.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent fb8dd014
...@@ -137,6 +137,7 @@ config SOC_AU1200 ...@@ -137,6 +137,7 @@ config SOC_AU1200
config SOC_AU1X00 config SOC_AU1X00
bool bool
select 64BIT_PHYS_ADDR select 64BIT_PHYS_ADDR
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_APM_EMULATION select SYS_SUPPORTS_APM_EMULATION
......
This diff is collapsed.
...@@ -926,9 +926,11 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; ...@@ -926,9 +926,11 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
#endif /* CONFIG_SOC_AU1200 */ #endif /* CONFIG_SOC_AU1200 */
#define AU1000_LAST_INTC0_INT 31 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 0)
#define AU1000_LAST_INTC1_INT 63 #define AU1000_INTC0_INT_LAST (MIPS_CPU_IRQ_BASE + 31)
#define AU1000_MAX_INTR 63 #define AU1000_INTC1_INT_BASE (MIPS_CPU_IRQ_BASE + 32)
#define AU1000_INTC1_INT_LAST (MIPS_CPU_IRQ_BASE + 63)
#define AU1000_MAX_INTR (MIPS_CPU_IRQ_BASE + 63)
#define INTX 0xFF /* not valid */ #define INTX 0xFF /* not valid */
/* Programmable Counters 0 and 1 */ /* Programmable Counters 0 and 1 */
......
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