Commit f4a2596c authored by Alex Deucher's avatar Alex Deucher

drm/radeon: fix endian bugs in radeon_atom_get_clock_dividers() (v3)

v2: fix copy paste typo.
v3: clarify new union member
Reported-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1586505a
...@@ -458,6 +458,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 ...@@ -458,6 +458,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
union union
{ {
ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
ULONG ulClockParams; //ULONG access for BE
ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
}; };
UCHAR ucRefDiv; //Output Parameter UCHAR ucRefDiv; //Output Parameter
...@@ -490,6 +491,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 ...@@ -490,6 +491,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
union union
{ {
ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
ULONG ulClockParams; //ULONG access for BE
ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
}; };
UCHAR ucRefDiv; //Output Parameter UCHAR ucRefDiv; //Output Parameter
......
...@@ -2710,8 +2710,7 @@ int radeon_atom_get_clock_dividers(struct radeon_device *rdev, ...@@ -2710,8 +2710,7 @@ int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
} else { } else {
if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
args.v3.ulClock.ulComputeClockFlag = clock_type; args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
args.v3.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
...@@ -2726,8 +2725,7 @@ int radeon_atom_get_clock_dividers(struct radeon_device *rdev, ...@@ -2726,8 +2725,7 @@ int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
dividers->vco_mode = (args.v3.ucCntlFlag & dividers->vco_mode = (args.v3.ucCntlFlag &
ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
} else { } else {
args.v5.ulClock.ulComputeClockFlag = clock_type; args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
args.v5.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
if (strobe_mode) if (strobe_mode)
args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
......
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