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Commit f4ab36cb authored by Drew Richardson's avatar Drew Richardson Committed by Will Deacon
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arm: perf: Convert event enums to #defines 

The enums are not necessary and this allows the event values to be
used to construct static strings at compile time.
Signed-off-by: default avatarDrew Richardson <drew.richardson@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent b916b785
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Showing with 85 additions and 101 deletions
arch/arm/kernel/perf_event_v7.c
View file @ f4ab36cb
...@@ -35,133 +35,117 @@ ...@@ -35,133 +35,117 @@
* but the encodings are considered to be `reserved' in the case that * but the encodings are considered to be `reserved' in the case that
* they are not available. * they are not available.
*/ */
enum armv7_perf_types { #define ARMV7_PERFCTR_PMNC_SW_INCR 0x00
ARMV7_PERFCTR_PMNC_SW_INCR = 0x00, #define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01
ARMV7_PERFCTR_L1_ICACHE_REFILL = 0x01, #define ARMV7_PERFCTR_ITLB_REFILL 0x02
ARMV7_PERFCTR_ITLB_REFILL = 0x02, #define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03
ARMV7_PERFCTR_L1_DCACHE_REFILL = 0x03, #define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04
ARMV7_PERFCTR_L1_DCACHE_ACCESS = 0x04, #define ARMV7_PERFCTR_DTLB_REFILL 0x05
ARMV7_PERFCTR_DTLB_REFILL = 0x05, #define ARMV7_PERFCTR_MEM_READ 0x06
ARMV7_PERFCTR_MEM_READ = 0x06, #define ARMV7_PERFCTR_MEM_WRITE 0x07
ARMV7_PERFCTR_MEM_WRITE = 0x07, #define ARMV7_PERFCTR_INSTR_EXECUTED 0x08
ARMV7_PERFCTR_INSTR_EXECUTED = 0x08, #define ARMV7_PERFCTR_EXC_TAKEN 0x09
ARMV7_PERFCTR_EXC_TAKEN = 0x09, #define ARMV7_PERFCTR_EXC_EXECUTED 0x0A
ARMV7_PERFCTR_EXC_EXECUTED = 0x0A, #define ARMV7_PERFCTR_CID_WRITE 0x0B
ARMV7_PERFCTR_CID_WRITE = 0x0B,
/* /*
* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS. * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
* It counts: * It counts:
* - all (taken) branch instructions, * - all (taken) branch instructions,
* - instructions that explicitly write the PC, * - instructions that explicitly write the PC,
* - exception generating instructions. * - exception generating instructions.
*/ */
ARMV7_PERFCTR_PC_WRITE = 0x0C, #define ARMV7_PERFCTR_PC_WRITE 0x0C
ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D, #define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D
ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E, #define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E
ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS = 0x0F, #define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10, #define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10
ARMV7_PERFCTR_CLOCK_CYCLES = 0x11, #define ARMV7_PERFCTR_CLOCK_CYCLES 0x11
ARMV7_PERFCTR_PC_BRANCH_PRED = 0x12, #define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12
/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */ /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
ARMV7_PERFCTR_MEM_ACCESS = 0x13, #define ARMV7_PERFCTR_MEM_ACCESS 0x13
ARMV7_PERFCTR_L1_ICACHE_ACCESS = 0x14, #define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14
ARMV7_PERFCTR_L1_DCACHE_WB = 0x15, #define ARMV7_PERFCTR_L1_DCACHE_WB 0x15
ARMV7_PERFCTR_L2_CACHE_ACCESS = 0x16, #define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16
ARMV7_PERFCTR_L2_CACHE_REFILL = 0x17, #define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17
ARMV7_PERFCTR_L2_CACHE_WB = 0x18, #define ARMV7_PERFCTR_L2_CACHE_WB 0x18
ARMV7_PERFCTR_BUS_ACCESS = 0x19, #define ARMV7_PERFCTR_BUS_ACCESS 0x19
ARMV7_PERFCTR_MEM_ERROR = 0x1A, #define ARMV7_PERFCTR_MEM_ERROR 0x1A
ARMV7_PERFCTR_INSTR_SPEC = 0x1B, #define ARMV7_PERFCTR_INSTR_SPEC 0x1B
ARMV7_PERFCTR_TTBR_WRITE = 0x1C, #define ARMV7_PERFCTR_TTBR_WRITE 0x1C
ARMV7_PERFCTR_BUS_CYCLES = 0x1D, #define ARMV7_PERFCTR_BUS_CYCLES 0x1D
ARMV7_PERFCTR_CPU_CYCLES = 0xFF #define ARMV7_PERFCTR_CPU_CYCLES 0xFF
};
/* ARMv7 Cortex-A8 specific event types */ /* ARMv7 Cortex-A8 specific event types */
enum armv7_a8_perf_types { #define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43
ARMV7_A8_PERFCTR_L2_CACHE_ACCESS = 0x43, #define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44
ARMV7_A8_PERFCTR_L2_CACHE_REFILL = 0x44, #define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50
ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS = 0x50, #define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56
ARMV7_A8_PERFCTR_STALL_ISIDE = 0x56,
};
/* ARMv7 Cortex-A9 specific event types */ /* ARMv7 Cortex-A9 specific event types */
enum armv7_a9_perf_types { #define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68
ARMV7_A9_PERFCTR_INSTR_CORE_RENAME = 0x68, #define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60
ARMV7_A9_PERFCTR_STALL_ICACHE = 0x60, #define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66
ARMV7_A9_PERFCTR_STALL_DISPATCH = 0x66,
};
/* ARMv7 Cortex-A5 specific event types */ /* ARMv7 Cortex-A5 specific event types */
enum armv7_a5_perf_types { #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2
ARMV7_A5_PERFCTR_PREFETCH_LINEFILL = 0xc2, #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3
ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP = 0xc3,
};
/* ARMv7 Cortex-A15 specific event types */ /* ARMv7 Cortex-A15 specific event types */
enum armv7_a15_perf_types { #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ = 0x40, #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE = 0x41, #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42
ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ = 0x42, #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43
ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE = 0x43,
ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ = 0x4C, #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C
ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE = 0x4D, #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D
ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ = 0x50, #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50
ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE = 0x51, #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ = 0x52, #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52
ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE = 0x53, #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53
ARMV7_A15_PERFCTR_PC_WRITE_SPEC = 0x76, #define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76
};
/* ARMv7 Cortex-A12 specific event types */ /* ARMv7 Cortex-A12 specific event types */
enum armv7_a12_perf_types { #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ = 0x40, #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE = 0x41,
ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ = 0x50, #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50
ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE = 0x51, #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
ARMV7_A12_PERFCTR_PC_WRITE_SPEC = 0x76, #define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76
ARMV7_A12_PERFCTR_PF_TLB_REFILL = 0xe7, #define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7
};
/* ARMv7 Krait specific event types */ /* ARMv7 Krait specific event types */
enum krait_perf_types { #define KRAIT_PMRESR0_GROUP0 0xcc
KRAIT_PMRESR0_GROUP0 = 0xcc, #define KRAIT_PMRESR1_GROUP0 0xd0
KRAIT_PMRESR1_GROUP0 = 0xd0, #define KRAIT_PMRESR2_GROUP0 0xd4
KRAIT_PMRESR2_GROUP0 = 0xd4, #define KRAIT_VPMRESR0_GROUP0 0xd8
KRAIT_VPMRESR0_GROUP0 = 0xd8,
KRAIT_PERFCTR_L1_ICACHE_ACCESS = 0x10011, #define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011
KRAIT_PERFCTR_L1_ICACHE_MISS = 0x10010, #define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010
KRAIT_PERFCTR_L1_ITLB_ACCESS = 0x12222, #define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222
KRAIT_PERFCTR_L1_DTLB_ACCESS = 0x12210, #define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210
};
/* ARMv7 Scorpion specific event types */ /* ARMv7 Scorpion specific event types */
enum scorpion_perf_types { #define SCORPION_LPM0_GROUP0 0x4c
SCORPION_LPM0_GROUP0 = 0x4c, #define SCORPION_LPM1_GROUP0 0x50
SCORPION_LPM1_GROUP0 = 0x50, #define SCORPION_LPM2_GROUP0 0x54
SCORPION_LPM2_GROUP0 = 0x54, #define SCORPION_L2LPM_GROUP0 0x58
SCORPION_L2LPM_GROUP0 = 0x58, #define SCORPION_VLPM_GROUP0 0x5c
SCORPION_VLPM_GROUP0 = 0x5c,
SCORPION_ICACHE_ACCESS = 0x10053, #define SCORPION_ICACHE_ACCESS 0x10053
SCORPION_ICACHE_MISS = 0x10052, #define SCORPION_ICACHE_MISS 0x10052
SCORPION_DTLB_ACCESS = 0x12013, #define SCORPION_DTLB_ACCESS 0x12013
SCORPION_DTLB_MISS = 0x12012, #define SCORPION_DTLB_MISS 0x12012
SCORPION_ITLB_MISS = 0x12021, #define SCORPION_ITLB_MISS 0x12021
};
/* /*
* Cortex-A8 HW events mapping * Cortex-A8 HW events mapping
......
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