Commit f6e56435 authored by Alexandru Elisei's avatar Alexandru Elisei Committed by Will Deacon

arm64: Use defines instead of magic numbers

Following assembly code is not trivial; make it slightly easier to read by
replacing some of the magic numbers with the defines which are already
present in sysreg.h.
Reviewed-by: default avatarDave Martin <Dave.Martin@arm.com>
Signed-off-by: default avatarAlexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 697e96ed
...@@ -442,8 +442,8 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU ...@@ -442,8 +442,8 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU
* reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
*/ */
.macro reset_pmuserenr_el0, tmpreg .macro reset_pmuserenr_el0, tmpreg
mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer mrs \tmpreg, id_aa64dfr0_el1
sbfx \tmpreg, \tmpreg, #8, #4 sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4
cmp \tmpreg, #1 // Skip if no PMU present cmp \tmpreg, #1 // Skip if no PMU present
b.lt 9000f b.lt 9000f
msr pmuserenr_el0, xzr // Disable PMU access from EL0 msr pmuserenr_el0, xzr // Disable PMU access from EL0
......
...@@ -505,7 +505,7 @@ ENTRY(el2_setup) ...@@ -505,7 +505,7 @@ ENTRY(el2_setup)
* kernel is intended to run at EL2. * kernel is intended to run at EL2.
*/ */
mrs x2, id_aa64mmfr1_el1 mrs x2, id_aa64mmfr1_el1
ubfx x2, x2, #8, #4 ubfx x2, x2, #ID_AA64MMFR1_VHE_SHIFT, #4
#else #else
mov x2, xzr mov x2, xzr
#endif #endif
...@@ -538,7 +538,7 @@ set_hcr: ...@@ -538,7 +538,7 @@ set_hcr:
#ifdef CONFIG_ARM_GIC_V3 #ifdef CONFIG_ARM_GIC_V3
/* GICv3 system register access */ /* GICv3 system register access */
mrs x0, id_aa64pfr0_el1 mrs x0, id_aa64pfr0_el1
ubfx x0, x0, #24, #4 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #4
cbz x0, 3f cbz x0, 3f
mrs_s x0, SYS_ICC_SRE_EL2 mrs_s x0, SYS_ICC_SRE_EL2
...@@ -564,8 +564,8 @@ set_hcr: ...@@ -564,8 +564,8 @@ set_hcr:
#endif #endif
/* EL2 debug */ /* EL2 debug */
mrs x1, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer mrs x1, id_aa64dfr0_el1
sbfx x0, x1, #8, #4 sbfx x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
cmp x0, #1 cmp x0, #1
b.lt 4f // Skip if no PMU present b.lt 4f // Skip if no PMU present
mrs x0, pmcr_el0 // Disable debug access traps mrs x0, pmcr_el0 // Disable debug access traps
...@@ -574,7 +574,7 @@ set_hcr: ...@@ -574,7 +574,7 @@ set_hcr:
csel x3, xzr, x0, lt // all PMU counters from EL1 csel x3, xzr, x0, lt // all PMU counters from EL1
/* Statistical profiling */ /* Statistical profiling */
ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer ubfx x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
cbz x0, 7f // Skip if SPE not present cbz x0, 7f // Skip if SPE not present
cbnz x2, 6f // VHE? cbnz x2, 6f // VHE?
mrs_s x4, SYS_PMBIDR_EL1 // If SPE available at EL2, mrs_s x4, SYS_PMBIDR_EL1 // If SPE available at EL2,
......
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