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Commit f7ec9146 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'renesas-dt-for-v4.14' of... 

Merge tag 'renesas-dt-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Pull "Renesas ARM Based SoC DT Updates for v4.14" from Simon Horman:

Changes of note:

* Add pin controller support to the RZ/G1M (r8a7743) SoC and
  RZ/A1 (r7s72100) SoCs now that the driver is available in v4.13-rc1.

* Add GPIO support to the RZ/G1M (r8a7743) SoC now that the driver
  is availabe in v4.13-rc1.

* Enable MMCIF0 and Ethernet AVB support on the RZ/G1M (r8a7743) SoC and
  the iWave-RZG1M-20M Qseven SOM. This depends on newly added pin
  controller support noted above.

* Use R-Car Gen 2 fallback binding for vin nodes

  This makes binding use consistent across R-Car Gen 2 SoCs.
  It does not have any run-time effect

* Use SMP jump stub SRAM region from DT on R-Car Gen 2 SoCs

  Geert Uytterhoeven says, "The R-Car Gen2 platform code for CPU core
  bringup needs to copy a jump stub to on-SoC SRAM.  Currently it uses a
  hardcoded address pointing to ICRAM1."

* Add Inter Connect RAM to R-Car Gen 2 and RZ/G1 SoCs

  Geert Uytterhoeven says, "R-Car Gen2 and RZ/G1 SoCs contain two or three
  blocks of SRAM, which can be used for several purposes.  One such purpose
  is holding a jump stub for CPU core bringup."
* Use generic compatible string for I2C EEPROM for RZ/A1 (r7s72100) SoC
  and koelsch board.

  This is part of a tree-wide cleanup by Javier Martinez Canillas

* tag 'renesas-dt-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (38 commits)
  ARM: dts: iwg20m: Correct indentation of mmcif0 properties
  ARM: dts: rskrza1: Add LED0 pin support
  ARM: dts: rskrza1: Add SDHI1 pin group
  ARM: dts: rskrza1: Add Ethernet pin group
  ARM: dts: rskrza1: Add SCIF2 pin group
  ARM: dts: genmai: Add ethernet pin group
  ARM: dts: genmai: Add user led device nodes
  ARM: dts: genmai: Add RIIC2 pin group
  ARM: dts: genmai: Add SCIF2 pin group
  ARM: dts: r7s72100: Add pin controller node
  ARM: dts: iwg20m: Add MMCIF0 support
  ARM: dts: r8a7794: Use R-Car Gen 2 fallback binding for vin nodes
  ARM: dts: r8a7791: Use R-Car Gen 2 fallback binding for vin nodes
  ARM: dts: r8a7790: Use R-Car Gen 2 fallback binding for vin nodes
  ARM: dts: r8a7743: Add MMCIF0 support
  ARM: dts: r8a7794: Reserve SRAM for the SMP jump stub
  ARM: dts: r8a7793: Reserve SRAM for the SMP jump stub
  ARM: dts: r8a7792: Reserve SRAM for the SMP jump stub
  ARM: dts: r8a7791: Reserve SRAM for the SMP jump stub
  ARM: dts: r8a7790: Reserve SRAM for the SMP jump stub
  ...
parents c71fbbcd bf38b9ac
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Showing with 591 additions and 13 deletions
arch/arm/boot/dts/r7s72100-genmai.dts
View file @ f7ec9146
......@@ -11,6 +11,8 @@
/dts-v1/;
#include "r7s72100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
model = "Genmai";
......@@ -34,6 +36,54 @@ lbsc {
#address-cells = <1>;
#size-cells = <1>;
};
leds {
status = "okay";
compatible = "gpio-leds";
led1 {
gpios = <&port4 10 GPIO_ACTIVE_LOW>;
};
led2 {
gpios = <&port4 11 GPIO_ACTIVE_LOW>;
};
};
};
&pinctrl {
scif2_pins: serial2 {
/* P3_0 as TxD2; P3_2 as RxD2 */
pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
};
i2c2_pins: i2c2 {
/* RIIC2: P1_4 as SCL, P1_5 as SDA */
pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
};
ether_pins: ether {
/* Ethernet on Ports 1,2,3,5 */
pinmux = <RZA1_PINMUX(1, 14, 4)>,/* P1_14 = ET_COL */
<RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
<RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
<RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
<RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
<RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
<RZA1_PINMUX(2, 0, 2)>, /* P2_0 = ET_TXCLK */
<RZA1_PINMUX(2, 1, 2)>, /* P2_1 = ET_TXER */
<RZA1_PINMUX(2, 2, 2)>, /* P2_2 = ET_TXEN */
<RZA1_PINMUX(2, 3, 2)>, /* P2_3 = ET_CRS */
<RZA1_PINMUX(2, 4, 2)>, /* P2_4 = ET_TXD0 */
<RZA1_PINMUX(2, 5, 2)>, /* P2_5 = ET_TXD1 */
<RZA1_PINMUX(2, 6, 2)>, /* P2_6 = ET_TXD2 */
<RZA1_PINMUX(2, 7, 2)>, /* P2_7 = ET_TXD3 */
<RZA1_PINMUX(2, 8, 2)>, /* P2_8 = ET_RXD0 */
<RZA1_PINMUX(2, 9, 2)>, /* P2_9 = ET_RXD1 */
<RZA1_PINMUX(2, 10, 2)>,/* P2_10 = ET_RXD2 */
<RZA1_PINMUX(2, 11, 2)>;/* P2_11 = ET_RXD3 */
};
};
&extal_clk {
......@@ -52,12 +102,28 @@ &mtu2 {
status = "okay";
};
&ether {
pinctrl-names = "default";
pinctrl-0 = <&ether_pins>;
status = "okay";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
eeprom@50 {
compatible = "renesas,24c128";
compatible = "renesas,24c128", "atmel,24c128";
reg = <0x50>;
pagesize = <64>;
};
......@@ -68,6 +134,9 @@ &rtc {
};
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
status = "okay";
};
......
arch/arm/boot/dts/r7s72100-rskrza1.dts
View file @ f7ec9146
......@@ -10,6 +10,8 @@
/dts-v1/;
#include "r7s72100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
model = "RSKRZA1";
......@@ -33,6 +35,15 @@ lbsc {
#address-cells = <1>;
#size-cells = <1>;
};
leds {
status = "okay";
compatible = "gpio-leds";
led0 {
gpios = <&port7 1 GPIO_ACTIVE_LOW>;
};
};
};
&extal_clk {
......@@ -47,11 +58,57 @@ &rtc_x1_clk {
clock-frequency = <32768>;
};
&pinctrl {
/* Serial Console */
scif2_pins: serial2 {
pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
<RZA1_PINMUX(3, 2, 4)>; /* RxD2 */
};
/* Ethernet */
ether_pins: ether {
/* Ethernet on Ports 1,2,3,5 */
pinmux = <RZA1_PINMUX(1, 14, 4)>, /* ET_COL */
<RZA1_PINMUX(5, 9, 2)>, /* ET_MDC */
<RZA1_PINMUX(3, 3, 2)>, /* ET_MDIO */
<RZA1_PINMUX(3, 4, 2)>, /* ET_RXCLK */
<RZA1_PINMUX(3, 5, 2)>, /* ET_RXER */
<RZA1_PINMUX(3, 6, 2)>, /* ET_RXDV */
<RZA1_PINMUX(2, 0, 2)>, /* ET_TXCLK */
<RZA1_PINMUX(2, 1, 2)>, /* ET_TXER */
<RZA1_PINMUX(2, 2, 2)>, /* ET_TXEN */
<RZA1_PINMUX(2, 3, 2)>, /* ET_CRS */
<RZA1_PINMUX(2, 4, 2)>, /* ET_TXD0 */
<RZA1_PINMUX(2, 5, 2)>, /* ET_TXD1 */
<RZA1_PINMUX(2, 6, 2)>, /* ET_TXD2 */
<RZA1_PINMUX(2, 7, 2)>, /* ET_TXD3 */
<RZA1_PINMUX(2, 8, 2)>, /* ET_RXD0 */
<RZA1_PINMUX(2, 9, 2)>, /* ET_RXD1 */
<RZA1_PINMUX(2, 10, 2)>, /* ET_RXD2 */
<RZA1_PINMUX(2, 11, 2)>; /* ET_RXD3 */
};
/* SDHI ch1 on CN1 */
sdhi1_pins: sdhi1 {
pinmux = <RZA1_PINMUX(3, 8, 7)>, /* SD_CD_1 */
<RZA1_PINMUX(3, 9, 7)>, /* SD_WP_1 */
<RZA1_PINMUX(3, 10, 7)>, /* SD_D1_1 */
<RZA1_PINMUX(3, 11, 7)>, /* SD_D0_1 */
<RZA1_PINMUX(3, 12, 7)>, /* SD_CLK_1 */
<RZA1_PINMUX(3, 13, 7)>, /* SD_CMD_1 */
<RZA1_PINMUX(3, 14, 7)>, /* SD_D3_1 */
<RZA1_PINMUX(3, 15, 7)>; /* SD_D2_1 */
};
};
&mtu2 {
status = "okay";
};
&ether {
pinctrl-names = "default";
pinctrl-0 = <&ether_pins>;
status = "okay";
renesas,no-ether-link;
phy-handle = <&phy0>;
......@@ -61,6 +118,8 @@ phy0: ethernet-phy@0 {
};
&sdhi1 {
pinctrl-names = "default";
pinctrl-0 = <&sdhi1_pins>;
bus-width = <4>;
status = "okay";
};
......@@ -78,5 +137,7 @@ &rtc {
};
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
status = "okay";
};
arch/arm/boot/dts/r7s72100.dtsi
View file @ f7ec9146
......@@ -207,6 +207,84 @@ cpu@0 {
};
};
pinctrl: pin-controller@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;
port0: gpio-0 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 6>;
};
port1: gpio-1 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 16 16>;
};
port2: gpio-2 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 32 16>;
};
port3: gpio-3 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 48 16>;
};
port4: gpio-4 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 64 16>;
};
port5: gpio-5 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 80 11>;
};
port6: gpio-6 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 96 16>;
};
port7: gpio-7 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 112 16>;
};
port8: gpio-8 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 128 16>;
};
port9: gpio-9 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 144 8>;
};
port10: gpio-10 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 160 16>;
};
port11: gpio-11 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 176 16>;
};
};
scif0: serial@e8007000 {
compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8007000 64>;
......
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
View file @ f7ec9146
......@@ -17,9 +17,40 @@ / {
aliases {
serial0 = &scif0;
ethernet0 = &avb;
};
};
&pfc {
scif0_pins: scif0 {
groups = "scif0_data_d";
function = "scif0";
};
avb_pins: avb {
groups = "avb_mdio", "avb_gmii";
function = "avb";
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy3>;
phy-mode = "gmii";
renesas,no-ether-link;
status = "okay";
phy3: ethernet-phy@3 {
reg = <3>;
micrel,led-mode = <1>;
};
};
arch/arm/boot/dts/r8a7743-iwg20m.dtsi
View file @ f7ec9146
......@@ -22,8 +22,34 @@ memory@200000000 {
device_type = "memory";
reg = <2 0x00000000 0 0x20000000>;
};
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&pfc {
mmcif0_pins: mmc {
groups = "mmc_data8_b", "mmc_ctrl";
function = "mmc";
};
};
&mmcif0 {
pinctrl-0 = <&mmcif0_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_3p3v>;
bus-width = <8>;
non-removable;
status = "okay";
};
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
View file @ f7ec9146
/*
* Device Tree Source for the SK-RZG1M board
*
* Copyright (C) 2016 Cogent Embedded, Inc.
* Copyright (C) 2016-2017 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
......@@ -39,11 +39,34 @@ &extal_clk {
clock-frequency = <20000000>;
};
&pfc {
scif0_pins: scif0 {
groups = "scif0_data_d";
function = "scif0";
};
ether_pins: ether {
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
groups = "intc_irq0";
function = "intc";
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
renesas,ether-link-active-low;
status = "okay";
......
arch/arm/boot/dts/r8a7743.dtsi
View file @ f7ec9146
/*
* Device Tree Source for the r8a7743 SoC
*
* Copyright (C) 2016 Cogent Embedded Inc.
* Copyright (C) 2016-2017 Cogent Embedded Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
......@@ -65,6 +65,126 @@ gic: interrupt-controller@f1001000 {
resets = <&cpg 408>;
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 0 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 912>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 912>;
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 26>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 911>;
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 64 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 910>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 910>;
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 96 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 909>;
};
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 128 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 908>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 908>;
};
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 160 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 907>;
};
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 192 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 905>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 905>;
};
gpio7: gpio@e6055800 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
reg = <0 0xe6055800 0 0x50>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 224 26>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 904>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 904>;
};
irqc: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a7743", "renesas,irqc";
#interrupt-cells = <2>;
......@@ -123,6 +243,11 @@ sysc: system-controller@e6180000 {
#power-domain-cells = <1>;
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7743";
reg = <0 0xe6060000 0 0x250>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7743",
"renesas,rcar-dmac";
......@@ -468,6 +593,29 @@ hscif2: serial@e62d0000 {
status = "disabled";
};
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x40000>;
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
};
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7743";
reg = <0 0xee700000 0 0x400>;
......@@ -480,6 +628,35 @@ ether: ethernet@ee700000 {
#size-cells = <0>;
status = "disabled";
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7743",
"renesas,etheravb-rcar-gen2";
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mmcif0: mmc@ee200000 {
compatible = "renesas,mmcif-r8a7743",
"renesas,sh-mmcif";
reg = <0 0xee200000 0 0x80>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 315>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
<&dmac1 0xd1>, <&dmac1 0xd2>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 315>;
reg-io-width = <4>;
max-frequency = <97500000>;
status = "disabled";
};
};
/* External root clock */
......
arch/arm/boot/dts/r8a7745.dtsi
View file @ f7ec9146
......@@ -468,6 +468,29 @@ hscif2: serial@e62d0000 {
status = "disabled";
};
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x40000>;
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
};
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7745";
reg = <0 0xee700000 0 0x400>;
......
arch/arm/boot/dts/r8a7790.dtsi
View file @ f7ec9146
......@@ -830,6 +830,24 @@ hscif1: serial@e62c8000 {
status = "disabled";
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
};
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7790";
reg = <0 0xee700000 0 0x400>;
......@@ -909,7 +927,7 @@ usb2: usb-channel@2 {
};
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7790";
compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
......@@ -918,7 +936,7 @@ vin0: video@e6ef0000 {
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a7790";
compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
......@@ -927,7 +945,7 @@ vin1: video@e6ef1000 {
};
vin2: video@e6ef2000 {
compatible = "renesas,vin-r8a7790";
compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
......@@ -936,7 +954,7 @@ vin2: video@e6ef2000 {
};
vin3: video@e6ef3000 {
compatible = "renesas,vin-r8a7790";
compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef3000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
......
arch/arm/boot/dts/r8a7791-koelsch.dts
View file @ f7ec9146
......@@ -702,7 +702,7 @@ adv7612_out: endpoint {
};
eeprom@50 {
compatible = "renesas,24c02";
compatible = "renesas,24c02", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
......
arch/arm/boot/dts/r8a7791.dtsi
View file @ f7ec9146
......@@ -890,6 +890,24 @@ hscif2: serial@e62d0000 {
status = "disabled";
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
};
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7791";
reg = <0 0xee700000 0 0x400>;
......@@ -969,7 +987,7 @@ usb2: usb-channel@2 {
};
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7791";
compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
......@@ -978,7 +996,7 @@ vin0: video@e6ef0000 {
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a7791";
compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
......@@ -987,7 +1005,7 @@ vin1: video@e6ef1000 {
};
vin2: video@e6ef2000 {
compatible = "renesas,vin-r8a7791";
compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
......
arch/arm/boot/dts/r8a7792.dtsi
View file @ f7ec9146
......@@ -465,6 +465,24 @@ hscif1: serial@e62c8000 {
status = "disabled";
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
};
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7792";
reg = <0 0xee100000 0 0x328>;
......
arch/arm/boot/dts/r8a7793.dtsi
View file @ f7ec9146
......@@ -848,6 +848,24 @@ hscif2: serial@e62d0000 {
status = "disabled";
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
};
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7793";
reg = <0 0xee700000 0 0x400>;
......
arch/arm/boot/dts/r8a7794.dtsi
View file @ f7ec9146
......@@ -588,6 +588,24 @@ hscif2: serial@e62d0000 {
status = "disabled";
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
};
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7794";
reg = <0 0xee700000 0 0x400>;
......@@ -783,7 +801,7 @@ qspi: spi@e6b10000 {
};
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7794";
compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
......@@ -792,7 +810,7 @@ vin0: video@e6ef0000 {
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a7794";
compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
......
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