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Commit f7f26550 authored by Kai Germaschewski's avatar Kai Germaschewski
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ISDN/HiSax: Helper functions for B-Channel {read,write}_reg() 

As a preparation for moving the B-Channel access functions into
a ops struct, introduce inline helper functions for using them.
parent 9f1961aa
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Showing with 278 additions and 194 deletions
drivers/isdn/hisax/hfc_2bds0.c
View file @ f7f26550
......@@ -144,7 +144,7 @@ SelFiFo(struct IsdnCardState *cs, u_char FiFo)
}
cs->hw.hfcD.fifo = FiFo;
WaitNoBusy(cs);
cs->BC_Write_Reg(cs, HFCD_DATA, cip, 0);
WriteReg(cs, HFCD_DATA, cip, 0);
WaitForBusy(cs);
return(2);
}
......
drivers/isdn/hisax/hfc_2bs0.c
View file @ f7f26550
......@@ -17,14 +17,26 @@
#include "isdnl1.h"
#include <linux/interrupt.h>
static inline u8
hfc_read_reg(struct IsdnCardState *cs, int data, u8 reg)
{
return cs->BC_Read_Reg(cs, data, reg);
}
static inline void
hfc_write_reg(struct IsdnCardState *cs, int data, u8 reg, u8 val)
{
cs->BC_Write_Reg(cs, data, reg, val);
}
static inline int
WaitForBusy(struct IsdnCardState *cs)
{
int to = 130;
u_char val;
while (!(cs->BC_Read_Reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) {
val = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2 |
while (!(hfc_read_reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) {
val = hfc_read_reg(cs, HFC_DATA, HFC_CIP | HFC_F2 |
(cs->hw.hfc.cip & 3));
udelay(1);
to--;
......@@ -41,7 +53,7 @@ WaitNoBusy(struct IsdnCardState *cs)
{
int to = 125;
while ((cs->BC_Read_Reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) {
while ((hfc_read_reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) {
udelay(1);
to--;
}
......@@ -72,9 +84,9 @@ ReadZReg(struct BCState *bcs, u_char reg)
int val;
WaitNoBusy(bcs->cs);
val = 256 * bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_HIGH);
val = 256 * hfc_read_reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_HIGH);
WaitNoBusy(bcs->cs);
val += bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_LOW);
val += hfc_read_reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_LOW);
return (val);
}
......@@ -91,14 +103,14 @@ hfc_clear_fifo(struct BCState *bcs)
cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) {
cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip);
hfc_write_reg(cs, HFC_STATUS, cip, cip);
WaitForBusy(cs);
}
WaitNoBusy(cs);
f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
f1 = hfc_read_reg(cs, HFC_DATA, cip);
cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
WaitNoBusy(cs);
f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
f2 = hfc_read_reg(cs, HFC_DATA, cip);
z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
cnt = 32;
......@@ -117,21 +129,21 @@ hfc_clear_fifo(struct BCState *bcs)
cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
idx = 0;
while ((idx < rcnt) && WaitNoBusy(cs)) {
cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
hfc_read_reg(cs, HFC_DATA_NODEB, cip);
idx++;
}
if (f1 != f2) {
WaitNoBusy(cs);
cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
hfc_read_reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
HFC_CHANNEL(bcs->channel));
WaitForBusy(cs);
}
cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
WaitNoBusy(cs);
f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
f1 = hfc_read_reg(cs, HFC_DATA, cip);
cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
WaitNoBusy(cs);
f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
f2 = hfc_read_reg(cs, HFC_DATA, cip);
z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
}
......@@ -158,9 +170,9 @@ hfc_empty_fifo(struct BCState *bcs, int count)
debugl1(cs, "hfc_empty_fifo: incoming packet too large");
cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
while ((idx++ < count) && WaitNoBusy(cs))
cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
hfc_read_reg(cs, HFC_DATA_NODEB, cip);
WaitNoBusy(cs);
stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
stat = hfc_read_reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
HFC_CHANNEL(bcs->channel));
WaitForBusy(cs);
return (NULL);
......@@ -170,9 +182,9 @@ hfc_empty_fifo(struct BCState *bcs, int count)
debugl1(cs, "hfc_empty_fifo: incoming packet too small");
cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
while ((idx++ < count) && WaitNoBusy(cs))
cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
hfc_read_reg(cs, HFC_DATA_NODEB, cip);
WaitNoBusy(cs);
stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
stat = hfc_read_reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
HFC_CHANNEL(bcs->channel));
WaitForBusy(cs);
#ifdef ERROR_STATISTIC
......@@ -191,7 +203,7 @@ hfc_empty_fifo(struct BCState *bcs, int count)
idx = 0;
cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
while ((idx < count) && WaitNoBusy(cs)) {
*ptr++ = cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
*ptr++ = hfc_read_reg(cs, HFC_DATA_NODEB, cip);
idx++;
}
if (idx != count) {
......@@ -200,7 +212,7 @@ hfc_empty_fifo(struct BCState *bcs, int count)
dev_kfree_skb_any(skb);
if (bcs->mode != L1_MODE_TRANS) {
WaitNoBusy(cs);
stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
stat = hfc_read_reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
HFC_CHANNEL(bcs->channel));
WaitForBusy(cs);
}
......@@ -208,11 +220,11 @@ hfc_empty_fifo(struct BCState *bcs, int count)
}
if (bcs->mode != L1_MODE_TRANS) {
WaitNoBusy(cs);
chksum = (cs->BC_Read_Reg(cs, HFC_DATA, cip) << 8);
chksum = (hfc_read_reg(cs, HFC_DATA, cip) << 8);
WaitNoBusy(cs);
chksum += cs->BC_Read_Reg(cs, HFC_DATA, cip);
chksum += hfc_read_reg(cs, HFC_DATA, cip);
WaitNoBusy(cs);
stat = cs->BC_Read_Reg(cs, HFC_DATA, cip);
stat = hfc_read_reg(cs, HFC_DATA, cip);
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "hfc_empty_fifo %d chksum %x stat %x",
bcs->channel, chksum, stat);
......@@ -225,7 +237,7 @@ hfc_empty_fifo(struct BCState *bcs, int count)
#endif
}
WaitNoBusy(cs);
stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
stat = hfc_read_reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
HFC_CHANNEL(bcs->channel));
WaitForBusy(cs);
}
......@@ -249,15 +261,15 @@ hfc_fill_fifo(struct BCState *bcs)
cip = HFC_CIP | HFC_F1 | HFC_SEND | HFC_CHANNEL(bcs->channel);
if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) {
cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip);
hfc_write_reg(cs, HFC_STATUS, cip, cip);
WaitForBusy(cs);
}
WaitNoBusy(cs);
if (bcs->mode != L1_MODE_TRANS) {
bcs->hw.hfc.f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
bcs->hw.hfc.f1 = hfc_read_reg(cs, HFC_DATA, cip);
cip = HFC_CIP | HFC_F2 | HFC_SEND | HFC_CHANNEL(bcs->channel);
WaitNoBusy(cs);
bcs->hw.hfc.f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
bcs->hw.hfc.f2 = hfc_read_reg(cs, HFC_DATA, cip);
bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(bcs, HFC_Z1 | HFC_SEND | HFC_CHANNEL(bcs->channel));
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
......@@ -293,7 +305,7 @@ hfc_fill_fifo(struct BCState *bcs)
cip = HFC_CIP | HFC_FIFO_IN | HFC_SEND | HFC_CHANNEL(bcs->channel);
idx = 0;
while ((idx < bcs->tx_skb->len) && WaitNoBusy(cs))
cs->BC_Write_Reg(cs, HFC_DATA_NODEB, cip, bcs->tx_skb->data[idx++]);
hfc_write_reg(cs, HFC_DATA_NODEB, cip, bcs->tx_skb->data[idx++]);
if (idx != bcs->tx_skb->len) {
debugl1(cs, "FIFO Send BUSY error");
printk(KERN_WARNING "HFC S FIFO channel %d BUSY Error\n", bcs->channel);
......@@ -307,7 +319,7 @@ hfc_fill_fifo(struct BCState *bcs)
if (bcs->mode != L1_MODE_TRANS) {
WaitForBusy(cs);
WaitNoBusy(cs);
cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F1_INC | HFC_SEND | HFC_CHANNEL(bcs->channel));
hfc_read_reg(cs, HFC_DATA, HFC_CIP | HFC_F1_INC | HFC_SEND | HFC_CHANNEL(bcs->channel));
}
test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
}
......@@ -327,16 +339,16 @@ main_irq_hfc(struct BCState *bcs)
count--;
cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) {
cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip);
hfc_write_reg(cs, HFC_STATUS, cip, cip);
WaitForBusy(cs);
}
WaitNoBusy(cs);
receive = 0;
if (bcs->mode == L1_MODE_HDLC) {
f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
f1 = hfc_read_reg(cs, HFC_DATA, cip);
cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
WaitNoBusy(cs);
f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
f2 = hfc_read_reg(cs, HFC_DATA, cip);
if (f1 != f2) {
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "hfc rec %d f1(%d) f2(%d)",
......@@ -411,7 +423,7 @@ mode_hfc(struct BCState *bcs, int mode, int bc)
break;
case (L1_MODE_TRANS):
cs->hw.hfc.ctmt &= ~(1 << bc); /* set HDLC mode */
cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt);
hfc_write_reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt);
hfc_clear_fifo(bcs); /* complete fifo clear */
if (bc) {
cs->hw.hfc.ctmt |= 1;
......@@ -435,7 +447,7 @@ mode_hfc(struct BCState *bcs, int mode, int bc)
}
break;
}
cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt);
hfc_write_reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt);
cs->writeisac(cs, ISAC_SPCR, cs->hw.hfc.isac_spcr);
if (mode == L1_MODE_HDLC)
hfc_clear_fifo(bcs);
......
drivers/isdn/hisax/hfcscard.c
View file @ f7f26550
......@@ -20,6 +20,18 @@ extern const char *CardType[];
static const char *hfcs_revision = "$Revision: 1.8.6.2 $";
static inline u8
hfcs_read_reg(struct IsdnCardState *cs, int data, u8 reg)
{
return cs->BC_Read_Reg(cs, data, reg);
}
static inline void
hfcs_write_reg(struct IsdnCardState *cs, int data, u8 reg, u8 val)
{
cs->BC_Write_Reg(cs, data, reg, val);
}
static void
hfcs_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......@@ -31,8 +43,8 @@ hfcs_interrupt(int intno, void *dev_id, struct pt_regs *regs)
return;
}
if ((HFCD_ANYINT | HFCD_BUSY_NBUSY) &
(stat = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_STAT))) {
val = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_INT_S1);
(stat = hfcs_read_reg(cs, HFCD_DATA, HFCD_STAT))) {
val = hfcs_read_reg(cs, HFCD_DATA, HFCD_INT_S1);
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "HFCS: stat(%02x) s1(%02x)", stat, val);
hfc2bds0_interrupt(cs, val);
......@@ -68,37 +80,37 @@ reset_hfcs(struct IsdnCardState *cs)
cs->hw.hfcD.cirm = HFCD_RESET;
if (cs->typ == ISDN_CTYPE_TELES3C)
cs->hw.hfcD.cirm |= HFCD_MEM8K;
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset On */
hfcs_write_reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset On */
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout((30*HZ)/1000);
cs->hw.hfcD.cirm = 0;
if (cs->typ == ISDN_CTYPE_TELES3C)
cs->hw.hfcD.cirm |= HFCD_MEM8K;
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset Off */
hfcs_write_reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset Off */
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout((10*HZ)/1000);
if (cs->typ == ISDN_CTYPE_TELES3C)
cs->hw.hfcD.cirm |= HFCD_INTB;
else if (cs->typ == ISDN_CTYPE_ACERP10)
cs->hw.hfcD.cirm |= HFCD_INTA;
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm);
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CLKDEL, 0x0e);
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_TEST, HFCD_AUTO_AWAKE); /* S/T Auto awake */
hfcs_write_reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm);
hfcs_write_reg(cs, HFCD_DATA, HFCD_CLKDEL, 0x0e);
hfcs_write_reg(cs, HFCD_DATA, HFCD_TEST, HFCD_AUTO_AWAKE); /* S/T Auto awake */
cs->hw.hfcD.ctmt = HFCD_TIM25 | HFCD_AUTO_TIMER;
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt);
hfcs_write_reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt);
cs->hw.hfcD.int_m2 = HFCD_IRQ_ENABLE;
cs->hw.hfcD.int_m1 = HFCD_INTS_B1TRANS | HFCD_INTS_B2TRANS |
HFCD_INTS_DTRANS | HFCD_INTS_B1REC | HFCD_INTS_B2REC |
HFCD_INTS_DREC | HFCD_INTS_L1STATE;
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M1, cs->hw.hfcD.int_m1);
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M2, cs->hw.hfcD.int_m2);
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_STATES, HFCD_LOAD_STATE | 2); /* HFC ST 2 */
hfcs_write_reg(cs, HFCD_DATA, HFCD_INT_M1, cs->hw.hfcD.int_m1);
hfcs_write_reg(cs, HFCD_DATA, HFCD_INT_M2, cs->hw.hfcD.int_m2);
hfcs_write_reg(cs, HFCD_DATA, HFCD_STATES, HFCD_LOAD_STATE | 2); /* HFC ST 2 */
udelay(10);
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_STATES, 2); /* HFC ST 2 */
hfcs_write_reg(cs, HFCD_DATA, HFCD_STATES, 2); /* HFC ST 2 */
cs->hw.hfcD.mst_m = HFCD_MASTER;
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m); /* HFC Master */
hfcs_write_reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m); /* HFC Master */
cs->hw.hfcD.sctrl = 0;
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl);
hfcs_write_reg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl);
}
static int
......@@ -120,8 +132,8 @@ hfcs_card_msg(struct IsdnCardState *cs, int mt, void *arg)
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout((80*HZ)/1000);
cs->hw.hfcD.ctmt |= HFCD_TIM800;
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt);
cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
hfcs_write_reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt);
hfcs_write_reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
return(0);
case CARD_TEST:
return(0);
......
drivers/isdn/hisax/hscx.c
View file @ f7f26550
......@@ -21,6 +21,24 @@ static char *HSCXVer[] __initdata =
{"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7",
"?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"};
static inline u8
hscx_read_reg(struct BCState *bcs, u8 addr)
{
struct IsdnCardState *cs = bcs->cs;
u8 hscx = bcs->hw.hscx.hscx;
return cs->BC_Read_Reg(cs, hscx, addr);
}
static inline void
hscx_write_reg(struct BCState *bcs, u8 addr, u8 val)
{
struct IsdnCardState *cs = bcs->cs;
u8 hscx = bcs->hw.hscx.hscx;
cs->BC_Write_Reg(cs, hscx, addr, val);
}
int __init
HscxVersion(struct IsdnCardState *cs, char *s)
{
......@@ -47,48 +65,49 @@ modehscx(struct BCState *bcs, int mode, int bc)
'A' + hscx, mode, bc);
bcs->mode = mode;
bcs->channel = bc;
cs->BC_Write_Reg(cs, hscx, HSCX_XAD1, 0xFF);
cs->BC_Write_Reg(cs, hscx, HSCX_XAD2, 0xFF);
cs->BC_Write_Reg(cs, hscx, HSCX_RAH2, 0xFF);
cs->BC_Write_Reg(cs, hscx, HSCX_XBCH, 0x0);
cs->BC_Write_Reg(cs, hscx, HSCX_RLCR, 0x0);
cs->BC_Write_Reg(cs, hscx, HSCX_CCR1,
hscx_write_reg(bcs, HSCX_XAD1, 0xFF);
hscx_write_reg(bcs, HSCX_XAD2, 0xFF);
hscx_write_reg(bcs, HSCX_RAH2, 0xFF);
hscx_write_reg(bcs, HSCX_XBCH, 0x0);
hscx_write_reg(bcs, HSCX_RLCR, 0x0);
hscx_write_reg(bcs, HSCX_CCR1,
test_bit(HW_IPAC, &cs->HW_Flags) ? 0x82 : 0x85);
cs->BC_Write_Reg(cs, hscx, HSCX_CCR2, 0x30);
cs->BC_Write_Reg(cs, hscx, HSCX_XCCR, 7);
cs->BC_Write_Reg(cs, hscx, HSCX_RCCR, 7);
hscx_write_reg(bcs, HSCX_CCR2, 0x30);
hscx_write_reg(bcs, HSCX_XCCR, 7);
hscx_write_reg(bcs, HSCX_RCCR, 7);
/* Switch IOM 1 SSI */
if (test_bit(HW_IOM1, &cs->HW_Flags) && (hscx == 0))
bc = 1 - bc;
if (bc == 0) {
cs->BC_Write_Reg(cs, hscx, HSCX_TSAX,
hscx_write_reg(bcs, HSCX_TSAX,
test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0);
cs->BC_Write_Reg(cs, hscx, HSCX_TSAR,
hscx_write_reg(bcs, HSCX_TSAR,
test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0);
} else {
cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, bcs->hw.hscx.tsaxr1);
cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, bcs->hw.hscx.tsaxr1);
hscx_write_reg(bcs, HSCX_TSAX, bcs->hw.hscx.tsaxr1);
hscx_write_reg(bcs, HSCX_TSAR, bcs->hw.hscx.tsaxr1);
}
switch (mode) {
case (L1_MODE_NULL):
cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, 0x1f);
cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, 0x1f);
cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x84);
case L1_MODE_NULL:
hscx_write_reg(bcs, HSCX_TSAX, 0x1f);
hscx_write_reg(bcs, HSCX_TSAR, 0x1f);
hscx_write_reg(bcs, HSCX_MODE, 0x84);
break;
case (L1_MODE_TRANS):
cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0xe4);
case L1_MODE_TRANS:
hscx_write_reg(bcs, HSCX_MODE, 0xe4);
break;
case (L1_MODE_HDLC):
cs->BC_Write_Reg(cs, hscx, HSCX_CCR1,
case L1_MODE_HDLC:
hscx_write_reg(bcs, HSCX_CCR1,
test_bit(HW_IPAC, &cs->HW_Flags) ? 0x8a : 0x8d);
cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x8c);
hscx_write_reg(bcs, HSCX_MODE, 0x8c);
break;
}
if (mode)
cs->BC_Write_Reg(cs, hscx, HSCX_CMDR, 0x41);
cs->BC_Write_Reg(cs, hscx, HSCX_ISTA, 0x00);
hscx_write_reg(bcs, HSCX_CMDR, 0x41);
hscx_write_reg(bcs, HSCX_ISTA, 0x00);
}
void
......@@ -207,32 +226,32 @@ inithscx(struct IsdnCardState *cs)
cs->bcs[1].hw.hscx.tsaxr0 = 0x2f;
cs->bcs[1].hw.hscx.tsaxr1 = 3;
val = cs->BC_Read_Reg(cs, 1, HSCX_ISTA);
val = hscx_read_reg(&cs->bcs[1], HSCX_ISTA);
debugl1(cs, "HSCX B ISTA %x", val);
if (val & 0x01) {
eval = cs->BC_Read_Reg(cs, 1, HSCX_EXIR);
eval = hscx_read_reg(&cs->bcs[1], HSCX_EXIR);
debugl1(cs, "HSCX B EXIR %x", eval);
}
if (val & 0x02) {
eval = cs->BC_Read_Reg(cs, 0, HSCX_EXIR);
eval = hscx_read_reg(&cs->bcs[0], HSCX_EXIR);
debugl1(cs, "HSCX A EXIR %x", eval);
}
val = cs->BC_Read_Reg(cs, 0, HSCX_ISTA);
val = hscx_read_reg(&cs->bcs[0], HSCX_ISTA);
debugl1(cs, "HSCX A ISTA %x", val);
val = cs->BC_Read_Reg(cs, 1, HSCX_STAR);
val = hscx_read_reg(&cs->bcs[1], HSCX_STAR);
debugl1(cs, "HSCX B STAR %x", val);
val = cs->BC_Read_Reg(cs, 0, HSCX_STAR);
val = hscx_read_reg(&cs->bcs[0], HSCX_STAR);
debugl1(cs, "HSCX A STAR %x", val);
/* disable all IRQ */
cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0xFF);
cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0xFF);
hscx_write_reg(&cs->bcs[0], HSCX_MASK, 0xFF);
hscx_write_reg(&cs->bcs[1], HSCX_MASK, 0xFF);
modehscx(cs->bcs, 0, 0);
modehscx(cs->bcs + 1, 0, 0);
modehscx(&cs->bcs[0], 0, 0);
modehscx(&cs->bcs[1], 0, 0);
/* Reenable all IRQ */
cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0);
cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0);
hscx_write_reg(&cs->bcs[0], HSCX_MASK, 0x0);
hscx_write_reg(&cs->bcs[1], HSCX_MASK, 0x0);
}
void __init
......
drivers/isdn/hisax/ipacx.c
View file @ f7f26550
......@@ -53,6 +53,24 @@ static int bch_setstack(struct PStack *st, struct BCState *bcs);
static void __devinit bch_init(struct IsdnCardState *cs, int hscx);
static void __init clear_pending_ints(struct IsdnCardState *cs);
static inline u8
ipacx_bc_read_reg(struct BCState *bcs, u8 addr)
{
struct IsdnCardState *cs = bcs->cs;
u8 hscx = bcs->hw.hscx.hscx;
return cs->BC_Read_Reg(cs, hscx, addr);
}
static inline void
ipacx_bc_write_reg(struct BCState *bcs, u8 addr, u8 val)
{
struct IsdnCardState *cs = bcs->cs;
u8 hscx = bcs->hw.hscx.hscx;
cs->BC_Write_Reg(cs, hscx, addr, val);
}
//----------------------------------------------------------
// Issue Layer 1 command to chip
//----------------------------------------------------------
......@@ -475,7 +493,7 @@ bch_empty_fifo(struct BCState *bcs, int count)
if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
if (cs->debug &L1_DEB_WARN)
debugl1(cs, "bch_empty_fifo() incoming packet too large");
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
ipacx_bc_write_reg(bcs, IPACX_CMDRB, 0x80); // RMC
bcs->hw.hscx.rcvidx = 0;
return;
}
......@@ -483,8 +501,8 @@ bch_empty_fifo(struct BCState *bcs, int count)
// Read data uninterruptible
ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
cnt = count;
while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB);
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
while (cnt--) *ptr++ = ipacx_bc_read_reg(bcs, IPACX_RFIFOB);
ipacx_bc_write_reg(bcs, IPACX_CMDRB, 0x80); // RMC
ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
bcs->hw.hscx.rcvidx += count;
......@@ -504,9 +522,7 @@ bch_empty_fifo(struct BCState *bcs, int count)
void
ipacx_fill_fifo(struct BCState *bcs)
{
struct IsdnCardState *cs = bcs->cs;
int more, count;
unsigned char hscx = bcs->hw.hscx.hscx;
unsigned char *p;
p = xmit_fill_fifo_b(bcs, B_FIFO_SIZE, &count, &more);
......@@ -514,9 +530,9 @@ ipacx_fill_fifo(struct BCState *bcs)
return;
while (count--)
cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++);
ipacx_bc_write_reg(bcs, IPACX_XFIFOB, *p++);
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a));
ipacx_bc_write_reg(bcs, IPACX_CMDRB, (more ? 0x08 : 0x0a));
}
//----------------------------------------------------------
......@@ -526,7 +542,7 @@ ipacx_fill_fifo(struct BCState *bcs)
static void
reset_xmit(struct BCState *bcs)
{
bcs->cs->BC_Write_Reg(bcs->cs, bcs->hw.hscx.hscx, IPACX_CMDRB, 0x01); // XRES
ipacx_bc_write_reg(bcs, IPACX_CMDRB, 0x01); // XRES
}
static void
......@@ -539,11 +555,11 @@ bch_int(struct IsdnCardState *cs, u_char hscx)
u_char rstab;
bcs = cs->bcs + hscx;
istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB);
istab = ipacx_bc_read_reg(bcs, IPACX_ISTAB);
if (!test_bit(BC_FLG_INIT, &bcs->Flag)) return;
if (istab &0x80) { // RME
rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB);
rstab = ipacx_bc_read_reg(bcs, IPACX_RSTAB);
if ((rstab &0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
if (!(rstab &0x80))
if (cs->debug &L1_DEB_WARN)
......@@ -554,10 +570,10 @@ bch_int(struct IsdnCardState *cs, u_char hscx)
if (!(rstab &0x20))
if (cs->debug &L1_DEB_WARN)
debugl1(cs, "bch_int() B-%d: CRC error", hscx);
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
ipacx_bc_write_reg(bcs, IPACX_CMDRB, 0x80); // RMC
}
else { // received frame ok
count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) &(B_FIFO_SIZE-1);
count = ipacx_bc_read_reg(bcs, IPACX_RBCLB) &(B_FIFO_SIZE-1);
if (count == 0) count = B_FIFO_SIZE;
bch_empty_fifo(bcs, count);
if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
......@@ -594,7 +610,7 @@ bch_int(struct IsdnCardState *cs, u_char hscx)
if (istab &0x20) { // RFO
if (cs->debug &L1_DEB_WARN)
debugl1(cs, "bch_int() B-%d: RFO error", hscx);
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES
ipacx_bc_write_reg(bcs, IPACX_CMDRB, 0x40); // RRES
}
if (istab &0x10) { // XPR
......@@ -634,22 +650,22 @@ bch_mode(struct BCState *bcs, int mode, int bc)
switch (mode) {
case (L1_MODE_NULL):
cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off
cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj.
cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
ipacx_bc_write_reg(bcs, IPACX_MODEB, 0xC0); // rec off
ipacx_bc_write_reg(bcs, IPACX_EXMB, 0x30); // std adj.
ipacx_bc_write_reg(bcs, IPACX_MASKB, 0xFF); // ints off
ipacx_bc_write_reg(bcs, IPACX_CMDRB, 0x41); // validate adjustments
break;
case (L1_MODE_TRANS):
cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode
cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
ipacx_bc_write_reg(bcs, IPACX_MODEB, 0x88); // ext transp mode
ipacx_bc_write_reg(bcs, IPACX_EXMB, 0x00); // xxx00000
ipacx_bc_write_reg(bcs, IPACX_CMDRB, 0x41); // validate adjustments
ipacx_bc_write_reg(bcs, IPACX_MASKB, _MASKB_IMASK);
break;
case (L1_MODE_HDLC):
cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0
cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
ipacx_bc_write_reg(bcs, IPACX_MODEB, 0xC8); // transp mode 0
ipacx_bc_write_reg(bcs, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled
ipacx_bc_write_reg(bcs, IPACX_CMDRB, 0x41); // validate adjustments
ipacx_bc_write_reg(bcs, IPACX_MASKB, _MASKB_IMASK);
break;
}
}
......
drivers/isdn/hisax/isar.c
View file @ f7f26550
This diff is collapsed.
drivers/isdn/hisax/jade.c
View file @ f7f26550
......@@ -20,16 +20,28 @@
static spinlock_t jade_lock = SPIN_LOCK_UNLOCKED;
static inline u8
jade_read_reg(struct IsdnCardState *cs, int jade, u8 addr)
{
return cs->BC_Read_Reg(cs, jade, addr);
}
static inline void
jade_write_reg(struct IsdnCardState *cs, int jade, u8 addr, u8 val)
{
cs->BC_Write_Reg(cs, jade, addr, val);
}
int __init
JadeVersion(struct IsdnCardState *cs, char *s)
{
int ver,i;
int to = 50;
cs->BC_Write_Reg(cs, -1, 0x50, 0x19);
jade_write_reg(cs, -1, 0x50, 0x19);
i=0;
while (to) {
udelay(1);
ver = cs->BC_Read_Reg(cs, -1, 0x60);
ver = jade_read_reg(cs, -1, 0x60);
to--;
if (ver)
break;
......@@ -41,7 +53,7 @@ JadeVersion(struct IsdnCardState *cs, char *s)
/* Wait for the JADE */
udelay(10);
/* Read version */
ver = cs->BC_Read_Reg(cs, -1, 0x60);
ver = jade_read_reg(cs, -1, 0x60);
printk(KERN_INFO "%s JADE version: %d\n", s, ver);
return (1);
}
......@@ -55,14 +67,14 @@ jade_write_indirect(struct IsdnCardState *cs, u_char reg, u_char value)
u_char ret;
spin_lock_irqsave(&jade_lock, flags);
/* Write the data */
cs->BC_Write_Reg(cs, -1, COMM_JADE+1, value);
jade_write_reg(cs, -1, COMM_JADE+1, value);
/* Say JADE we wanna write indirect reg 'reg' */
cs->BC_Write_Reg(cs, -1, COMM_JADE, reg);
jade_write_reg(cs, -1, COMM_JADE, reg);
to = 50;
/* Wait for RDY goes high */
while (to) {
udelay(1);
ret = cs->BC_Read_Reg(cs, -1, COMM_JADE);
ret = jade_read_reg(cs, -1, COMM_JADE);
to--;
if (ret & 1)
/* Got acknowledge */
......@@ -93,45 +105,45 @@ modejade(struct BCState *bcs, int mode, int bc)
bcs->mode = mode;
bcs->channel = bc;
cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO:0x00));
cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU|jadeCCR0_ITF));
cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR1, 0x00);
jade_write_reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO:0x00));
jade_write_reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU|jadeCCR0_ITF));
jade_write_reg(cs, jade, jade_HDLC_CCR1, 0x00);
jade_write_indirect(cs, jade_HDLC1SERRXPATH, 0x08);
jade_write_indirect(cs, jade_HDLC2SERRXPATH, 0x08);
jade_write_indirect(cs, jade_HDLC1SERTXPATH, 0x00);
jade_write_indirect(cs, jade_HDLC2SERTXPATH, 0x00);
cs->BC_Write_Reg(cs, jade, jade_HDLC_XCCR, 0x07);
cs->BC_Write_Reg(cs, jade, jade_HDLC_RCCR, 0x07);
jade_write_reg(cs, jade, jade_HDLC_XCCR, 0x07);
jade_write_reg(cs, jade, jade_HDLC_RCCR, 0x07);
if (bc == 0) {
cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x00);
cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x00);
jade_write_reg(cs, jade, jade_HDLC_TSAX, 0x00);
jade_write_reg(cs, jade, jade_HDLC_TSAR, 0x00);
} else {
cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x04);
cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x04);
jade_write_reg(cs, jade, jade_HDLC_TSAX, 0x04);
jade_write_reg(cs, jade, jade_HDLC_TSAR, 0x04);
}
switch (mode) {
case (L1_MODE_NULL):
cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, jadeMODE_TMO);
jade_write_reg(cs, jade, jade_HDLC_MODE, jadeMODE_TMO);
break;
case (L1_MODE_TRANS):
cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_TMO|jadeMODE_RAC|jadeMODE_XAC));
jade_write_reg(cs, jade, jade_HDLC_MODE, (jadeMODE_TMO|jadeMODE_RAC|jadeMODE_XAC));
break;
case (L1_MODE_HDLC):
cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_RAC|jadeMODE_XAC));
jade_write_reg(cs, jade, jade_HDLC_MODE, (jadeMODE_RAC|jadeMODE_XAC));
break;
}
if (mode) {
cs->BC_Write_Reg(cs, jade, jade_HDLC_RCMD, (jadeRCMD_RRES|jadeRCMD_RMC));
cs->BC_Write_Reg(cs, jade, jade_HDLC_XCMD, jadeXCMD_XRES);
jade_write_reg(cs, jade, jade_HDLC_RCMD, (jadeRCMD_RRES|jadeRCMD_RMC));
jade_write_reg(cs, jade, jade_HDLC_XCMD, jadeXCMD_XRES);
/* Unmask ints */
cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0xF8);
jade_write_reg(cs, jade, jade_HDLC_IMR, 0xF8);
}
else
/* Mask ints */
cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0x00);
jade_write_reg(cs, jade, jade_HDLC_IMR, 0x00);
}
static void
......@@ -245,39 +257,39 @@ initjade(struct IsdnCardState *cs)
cs->bcs[0].hw.hscx.hscx = 0;
cs->bcs[1].hw.hscx.hscx = 1;
cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00);
cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00);
jade_write_reg(cs, 0, jade_HDLC_IMR, 0x00);
jade_write_reg(cs, 1, jade_HDLC_IMR, 0x00);
val = cs->BC_Read_Reg(cs, 1, jade_HDLC_ISR);
val = jade_read_reg(cs, 1, jade_HDLC_ISR);
debugl1(cs, "jade B ISTA %x", val);
val = cs->BC_Read_Reg(cs, 0, jade_HDLC_ISR);
val = jade_read_reg(cs, 0, jade_HDLC_ISR);
debugl1(cs, "jade A ISTA %x", val);
val = cs->BC_Read_Reg(cs, 1, jade_HDLC_STAR);
val = jade_read_reg(cs, 1, jade_HDLC_STAR);
debugl1(cs, "jade B STAR %x", val);
val = cs->BC_Read_Reg(cs, 0, jade_HDLC_STAR);
val = jade_read_reg(cs, 0, jade_HDLC_STAR);
debugl1(cs, "jade A STAR %x", val);
/* Unmask ints */
cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0xF8);
cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0xF8);
jade_write_reg(cs, 0, jade_HDLC_IMR, 0xF8);
jade_write_reg(cs, 1, jade_HDLC_IMR, 0xF8);
/* Stop DSP audio tx/rx */
jade_write_indirect(cs, 0x11, 0x0f);
jade_write_indirect(cs, 0x17, 0x2f);
/* Transparent Mode, RxTx inactive, No Test, No RFS/TFS */
cs->BC_Write_Reg(cs, 0, jade_HDLC_MODE, jadeMODE_TMO);
cs->BC_Write_Reg(cs, 1, jade_HDLC_MODE, jadeMODE_TMO);
jade_write_reg(cs, 0, jade_HDLC_MODE, jadeMODE_TMO);
jade_write_reg(cs, 1, jade_HDLC_MODE, jadeMODE_TMO);
/* Power down, 1-Idle, RxTx least significant bit first */
cs->BC_Write_Reg(cs, 0, jade_HDLC_CCR0, 0x00);
cs->BC_Write_Reg(cs, 1, jade_HDLC_CCR0, 0x00);
jade_write_reg(cs, 0, jade_HDLC_CCR0, 0x00);
jade_write_reg(cs, 1, jade_HDLC_CCR0, 0x00);
/* Mask all interrupts */
cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00);
cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00);
jade_write_reg(cs, 0, jade_HDLC_IMR, 0x00);
jade_write_reg(cs, 1, jade_HDLC_IMR, 0x00);
/* Setup host access to hdlc controller */
jade_write_indirect(cs, jade_HDLCCNTRACCESS, (jadeINDIRECT_HAH1|jadeINDIRECT_HAH2));
/* Unmask HDLC int (dont forget DSP int later on)*/
cs->BC_Write_Reg(cs, -1,jade_INT, (jadeINT_HDLC1|jadeINT_HDLC2));
jade_write_reg(cs, -1,jade_INT, (jadeINT_HDLC1|jadeINT_HDLC2));
/* once again TRANSPARENT */
modejade(cs->bcs, 0, 0);
......
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