[PCI, ia32] don't assume "c->x86 > 6" applies to non-Intel CPUs

when programming PCI cache line size.

Just to be on the safe side.  Suggested by Ingo Oeser.

arch/i386/pci/common.c

@@ -152,7 +152,7 @@ static int __init pcibios_init(void)
 	pci_cache_line_size = 32 >> 2;
 	if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
 		pci_cache_line_size = 64 >> 2;	/* K7 & K8 */
-	else if (c->x86 > 6)
+	else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
 		pci_cache_line_size = 128 >> 2;	/* P4 */
 
 	pcibios_resource_survey();