Commit fefdc6cc authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher

drm/amdgpu: use different irq ring ID for Vega20 page queues

Vega20 uses ring id 1 for page queues EOP irq while previous
ASICs take ring id 3.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c713a461
......@@ -1706,13 +1706,15 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
amdgpu_fence_process(&adev->sdma.instance[instance].ring);
break;
case 1:
/* XXX compute */
if (adev->asic_type == CHIP_VEGA20)
amdgpu_fence_process(&adev->sdma.instance[instance].page);
break;
case 2:
/* XXX compute */
break;
case 3:
amdgpu_fence_process(&adev->sdma.instance[instance].page);
if (adev->asic_type != CHIP_VEGA20)
amdgpu_fence_process(&adev->sdma.instance[instance].page);
break;
}
return 0;
......
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