drm/amdgpu: use different irq ring ID for Vega20 page queues

Vega20 uses ring id 1 for page queues EOP irq while previous
ASICs take ring id 3.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

@@ -1706,12 +1706,14 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
 		amdgpu_fence_process(&adev->sdma.instance[instance].ring);
 		break;
 	case 1:
-		/* XXX compute */
+		if (adev->asic_type == CHIP_VEGA20)
+			amdgpu_fence_process(&adev->sdma.instance[instance].page);
 		break;
 	case 2:
 		/* XXX compute */
 		break;
 	case 3:
+		if (adev->asic_type != CHIP_VEGA20)
 			amdgpu_fence_process(&adev->sdma.instance[instance].page);
 		break;
 	}