- 24 Jul, 2015 31 commits
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Peter Hurley authored
Replace tty_ldisc_debug() macro definition; substitute with equivalent tty_debug() invocation. Signed-off-by:
Peter Hurley <peter@hurleysoftware.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Peter Hurley authored
Add tty_debug_hangup() macro which uses tty_debug to print the debug message; remove inlined #ifdefs. Signed-off-by:
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Peter Hurley authored
Introduce tty_debug() macro to output uniform debug information for tty core debug messages (function name and tty name). Note: printk(KERN_DEBUG) is retained here over pr_debug() since messages can be enabled in non-DEBUG builds. Signed-off-by:
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Peter Hurley authored
Output the function name, tty name, and invariant failure (if applicable). Add the tty count to the tty_open() message. Fix the disassociate_ctty() message, which printed the NULL pointer and the wrong message. Signed-off-by:
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Paul Gortmaker authored
The Kconfig for this driver is currently: config SERIAL_SUNHV bool "Sun4v Hypervisor Console support" ...meaning that it currently is not being built as a module by anyone. Lets remove the modular and unused code here, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. We don't swap module.h for init.h since this file has init.h already. We leave some tags like MODULE_LICENSE for documentation purposes, and for the "git blame" value. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code, so we remove that too. Cc: "David S. Miller" <davem@davemloft.net> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.com> Cc: sparclinux@vger.kernel.org Cc: linux-serial@vger.kernel.org Signed-off-by:Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
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Paul Gortmaker authored
The Kconfig for this driver is currently: config SERIAL_SUNCORE bool ...meaning that it currently is not being built as a module by anyone. Lets remove the modular and unused code here, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. We don't swap module.h for init.h since this file has init.h already. We leave some tags like MODULE_LICENSE for documentation purposes, and for the "git blame" value. Cc: "David S. Miller" <davem@davemloft.net> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.com> Cc: sparclinux@vger.kernel.org Cc: linux-serial@vger.kernel.org Signed-off-by: -
Paul Gortmaker authored
The Kconfig for this option is currently: config SERIAL_LANTIQ bool "Lantiq serial driver" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modularity, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. We delete the MODULE_DESCRIPTION and LICENSE tags since they are not adding any new information above and beyond what is at the top of the file. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code, so we remove that as well. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.com> Cc: linux-serial@vger.kernel.org Signed-off-by: -
Paul Gortmaker authored
The Kconfig for this option is currently: config SERIAL_SGI_L1_CONSOLE bool "SGI Altix L1 serial console support" ...meaning that it currently is not being built as a module by anyone. Lets remove the orphaned module code, so that when reading the driver there is no doubt it is builtin-only. We could consider making it tristate, but the above bool has been there since before the start of git history, which isn't all that surprising, since consoles are typically critical to have at early boot. So adding tristate is really of no value here. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.com> Cc: linux-serial@vger.kernel.org Signed-off-by: -
Javier Martinez Canillas authored
Commit 84f57d9e ("tty: serial/samsung: fix modular build") fixed build issues when the driver was built as a module. One of those was that printascii is only accessible when the driver is built-in. But there is no need to check for defined(CONFIG_DEBUG_LL) since the SERIAL_SAMSUNG_DEBUG Kconfig symbol already depends on DEBUG_LL. Signed-off-by:
Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by:
Kukjin Kim <kgene@kernel.org> Signed-off-by:
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Peter Hurley authored
The advance of the 'read' buffer index belongs in the outer flip buffer consume loop, with the other buffer index arithmetic. No functional change. Signed-off-by:
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Peter Hurley authored
Clarify flip buffer producer/consumer operation; the use of smp_load_acquire() and smp_store_release() more clearly indicates which memory access requires a barrier. Signed-off-by:
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Alexander Stein authored
The maximum bitrate supported depends on the clock rate used in BRG. This is stored in port.uartclk during probe. Respecting the 16x oversampling higher bitrates can be supported. Signed-off-by:
Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by:
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Krzysztof Kozlowski authored
i2c_driver does not need to set an owner because i2c_register_driver() will set it. Signed-off-by:
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Krzysztof Kozlowski authored
platform_driver does not need to set an owner because platform_driver_register() will set it. Signed-off-by:
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Cyrille Pitchen authored
For now this improvement is only used with TX DMA transfers. The data width must be set properly when configuring the DMA controller. Also the FIFO configuration must be set to match the DMA transfer data width: TXRDYM (Transmitter Ready Mode) and RXRDYM (Receiver Ready Mode) must be set into the FIFO Mode Register. These values are used by the USART to trigger the DMA controller. In single data mode they are not used and should be reset to 0. So the TXRDYM bits are changed to FOUR_DATA; then USART triggers the DMA controller when at least 4 data can be written into the TX FIFO througth the THR. On the other hand the RXRDYM bits are left unchanged to ONE_DATA. Atmel eXtended DMA controller allows us to set a different data width for each part of a scatter-gather transfer. So when calling dmaengine_slave_config() to configure the TX path, we just need to set dst_addr_width to the maximum data width. Then DMA writes into THR are split into up to two parts. The first part carries the first data to be sent and has a length equal to the greatest multiple of 4 (bytes) lower than or equal to the total length of the TX DMA transfer. The second part carries the trailing data (up to 3 bytes). The first part is written by the DMA into THR using 32 bit accesses, whereas 8bit accesses are used for the second part. Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
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Cyrille Pitchen authored
Depending on the hardware, TX and RX FIFOs may be available. The RX FIFO can avoid receive overruns, especially when DMA transfers are not used to read data from the Receive Holding Register. For heavy system load, The CPU is likely not be able to fetch data fast enough from the RHR. In addition, the RX FIFO can supersede the DMA/PDC to control the RTS line when the Hardware Handshaking mode is enabled. Two thresholds are to be set for that purpose: - When the number of data in the RX FIFO crosses and becomes lower than or equal to the low threshold, the RTS line is set to low level: the remote peer is requested to send data. - When the number of data in the RX FIFO crosses and becomes greater than or equal to the high threshold, the RTS line is set to high level: the remote peer should stop sending new data. - low threshold <= high threshold Once these two thresholds are set properly, this new feature is enabled by setting the FIFO RTS Control bit of the FIFO Mode Register. FIFOs also introduce a new multiple data mode: the USART works either in multiple data mode or in single data (legacy) mode. If MODE9 bit is set into the Mode Register or if USMODE is set to either LIN_MASTER, LIN_SLAVE or LON_MODE, FIFOs operate in single data mode. Otherwise, they operate in multiple data mode. In this new multiple data mode, accesses to the Receive Holding Register or Transmit Holding Register slightly change. Since this driver implements neither the 9bit data feature (MODE9 bit set into the Mode Register) nor LIN modes, the USART works in multiple data mode whenever FIFOs are available and enabled. We also assume that data are 8bit wide. In single data mode, 32bit access CAN be used to read a single data from RHR or write a single data into THR. However in multiple data mode, a 32bit access to RHR now allows us to read four consecutive data from RX FIFO. Also a 32bit access to THR now allows to write four consecutive data into TX FIFO. So we MUST use 8bit access whenever only one data have to be read/written at a time. Signed-off-by:
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Cyrille Pitchen authored
This patch replaces the UART_PUT_*, resp. UART_GET_*, macros by atmel_uart_writel(), resp. atmel_uart_readl(), inline function calls. Signed-off-by:
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Cyrille Pitchen authored
This patch updates macro definitions in atmel_serial.h to fit the 80 column rule. Please note that some deprecated comments such as "[AT91SAM9261 only]" are removed as the corresponding bits also exist in some later chips. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
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Cyrille Pitchen authored
This patch adds a new DT property, "atmel,fifo-size", to enable and set the maximum number of data the RX and TX FIFOs can store on FIFO capable USARTs. Please be aware that the VERSION register can not be used to guess the size of FIFOs. Indeed, for a given hardware version, the USARTs can be integrated on Atmel SoCs with different FIFO sizes. Also the "atmel,fifo-size" property is optional as older USARTs don't embed FIFO at all. Besides, the FIFO size can not be read or guessed from other registers: When designing the FIFO feature, no dedicated registers were added to store this size. Unsed spaces in the I/O register range are limited and better reserved for future usages. Instead, the FIFO size of each peripheral is documented in the programmer datasheet. Finally, on a given SoC, there can be several instances of USART with different FIFO sizes. This explain why we'd rather use a dedicated DT property than use the "compatible" property. Signed-off-by:
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Patrick Donnelly authored
task_pgrp requires an rcu or tasklist lock to be obtained if the returned pid is to be dereferenced, which kill_pgrp does. Obtain an RCU lock for the duration of use. Signed-off-by:
Patrick Donnelly <batrick@batbytes.com> Reviewed-by:
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Joerg Roedel authored
The XR17V35X UART needs the ECB bit set in its XR_EFR register to enable access to IER [7:5], ISR [5:4], FCR[5:4], MCR[7:5], and MSR [7:0]. Also reset the IER register to mask interrupts after access to all bits of this register has been enabled. This makes my 8-port XR17V35X working with the in-kernel serial driver. Cc: Joe Schultz <jschultz@xes-inc.com> Signed-off-by:
Joerg Roedel <jroedel@suse.de> Reviewed-by:
Michael Welling <mwelling@ieee.org> Signed-off-by:
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Peter Hurley authored
An already-active sender can swamp the interrupt handler with "too much work" if the rx interrupts are enabled when the fifo is disabled and operating in single-byte mode. Defer rx and line status interrupt enable until after the fifos are enabled in set_termios(), but at least initialize the shadow IER value with the interrupts which will be enabled. Signed-off-by:
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Jiri Slaby authored
We use __u8 in linux/gsmmux.h, so include linux/types.h to have that defined. Signed-off-by:
Jiri Slaby <jslaby@suse.cz> Signed-off-by:
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Vineet Gupta authored
Commit ed71871b ("tty/8250_early: Turn serial_in/serial_out into weak symbols") made these routines weak to allow platform specific Big endian override However recent updates to core, specifically ebc5e200 ("serial: of_serial: Support big-endian register accesses") and 6e63be3f ("serial: earlycon: Add support for big-endian MMIO accesses") means that round about way to overide the early serial accessors is no longer needed. Cc: Jiri Slaby <jslaby@suse.cz> Cc: Peter Hurley <peter@hurleysoftware.com> Cc: Rob Herring <robh@kernel.org> Cc: Kevin Cernekee <cernekee@gmail.com> Acked-by:
Noam Camus <noamc@ezchip.com> Signed-off-by:
Vineet Gupta <vgupta@synopsys.com> Reviewed-by:
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Peter Hurley authored
Refactor base port operations into new file; 8250_port.c. Legacy irq handling, RSA port support, port storage for universal driver, driver definition, module parameters and linkage remain in 8250_core.c The source file split and resulting modules is diagrammed below: 8250_core.c ====> 8250_core.c __ \ \ \ +-- 8250.ko (alias 8250_core) \ 8250_pnp.c __/ (universal driver) \ => 8250_port.c __ \ +-- 8250_base.ko 8250_dma.c __/ (port operations) Signed-off-by: -
David Jander authored
If the UART has been in use before this driver was loaded, IRQs might be active and get fired as soon as we set the handler, which will crash in the spin_lock_irqsave(&sport->port.lock, flags) because port.lock is not initialized until the port is added at the end of probe. Signed-off-by:
David Jander <david@protonic.nl> Signed-off-by:
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Manfred Schlaegl authored
To prevent problems with interrupt latency, and due to the fact, that the error will be counted anyway (icount.overrun), the dev_err is simply removed. Background: If an rx-fifo overflow occurs a dev_err message was called in interrupt context. Since dev_err messages are written to console in a synchronous way (unbuffered), and console may be a serial terminal, this leads to a highly increased interrupt-latency (several milliseconds). As a result of the high latency more rx-fifo overflows will happen, and therefore a feedback loop of errors is created. Signed-off-by:
Manfred Schlaegl <manfred.schlaegl@gmx.at> Acked-By:
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Manfred Schlaegl authored
As can be seen in function uart_insert_char (serial_core) the element buf_overrun of struct uart_icount is used to count overruns of tty-buffer. Added support for counting of overruns in imx driver analogue to serial_core. Signed-off-by:
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Fabio Estevam authored
Disable interrupts before requesting them in order to fix a kernel oops after lauching a kernel via kexec. Tested on a imx6sl-evk board. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
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Ricardo Ribalda Delgado authored
Being a soft core, it can be located not only on PPC or Microblaze platforms. Since the driver already does endianness detection we only need to change the Kconfig to use it in other arches. This is also done in other softcores as xilinx-spi. Signed-off-by:
Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by:
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Maxime Coquelin authored
SysRq support activation depends on CONFIG_SERIAL_STM32_USART_CONSOLE, but this config flag does not exists. This patch fix this by depending on the valid config flag, which is SERIAL_STM32_CONSOLE. Reported-by:
Andreas Ruprecht <andreas.ruprecht@fau.de> Signed-off-by:
Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by:
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- 23 Jul, 2015 9 commits
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Qipan Li authored
While UART work in DMA mode, function start_rx will request descriptor from DMA engine, if there is no left descriptor UART, driver will give err logs "DMA slave single fail". currently start_rx is called in set_termios function, so everytime, port setting will call start_rx once. Now put start_rx in startup, it will be called once while open the port. Signed-off-by:
Qipan Li <Qipan.Li@csr.com> Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
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Qipan Li authored
when UART works in DMA mode and left bytes in rx fifo less than a dma transfer unit, DMA engine can't transfer the bytes out to rx DMA buffer. so it need a way to fetch them out and flush them into tty buffer in time. in the above case, we want UART switch from DMA mode to PIO mode and fetch && flush bytes into tty layer buffer until rxfifo become empty, after that done let UART switch from PIO mode back to DMA mode. (record as method1) method1 result in the next receive result wrong. for example in PIO part of method1, we fetched && pushed X1...X3 bytes, when UART rxfifo newly received Y1...Y4 bytes, UART trigger a DMA unit transfer, the DMA unit's content is X1...X3Y1 and rxfifo fifo status is empty, so X1X2X3 pushed twice by PIO way and DMA way also the bytes Y2Y3Y4 missed. add rxfifo reset operation before UART switch back to DMA mode would resolve the issue. ([method1 + do fifo reset] record as method2) before the commit, UART driver use method2. but methd2 have a risk of data loss, as if UART's shift register receive a complete byte and transfer it into rxfifo before rxfifo reset operation the byte will loss. UART and USP have the similar bits CLEAR_RX_ADDR_EN(uart)/FRADDR_CLR_EN(usp), When found UART controller changing I/O to DMA mode, UART controller clears the two low bits of read point (rx_fifo_addr[1:0]). when enable the bit + method1(record as method3), in above example the DMA unit's content is X1...X3Y1 and there are Y2Y3Y4 in rxfifo by experiment, we just push bytes in rx DMA buffer. BTW, the workaround works only for UART receive DMA channel use SINGLE DMA mode. Signed-off-by:
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Axel Lin authored
The implementation of cris_console_device() is exactly the same as uart_console_device(), so let's switch to use uart_console_device(). Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Niklas Cassel <nks@flawful.org> Acked-by:
Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by:
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Peter Hurley authored
OMAP h/w-assisted IXON flow control is borked. The transmitter becomes stuck if XON is never received; clearing the fifos or resetting the rx flow control bits has no effect. Remove auto-IXANY as well, since without auto-IXON, it has no purpose. Signed-off-by:
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Sekhar Nori authored
Due to Advisory 21 as documented in AM437x errata document, UART module cannot be disabled once DMA is used. The only workaround is to softreset the module before disabling it. DRA7x UARTs are compatible to AM437x UARTs in terms of this errata and prescribed workaround. Enable usage of workaround for this errata on DRA7x SoCs. Signed-off-by:
Sekhar Nori <nsekhar@ti.com> Acked-by:
Tony Lindgren <tony@atomide.com> Reviewed-by:
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Sekhar Nori authored
AM335x, AM437x and DRA7x SoCs have an errata[1] due to which UART cannot be idled after it has been used with DMA. OMAP3 has a similar sounding errata which has been worked around in a2fc3661 ("ARM: OMAP3: Use manual idle for UARTs because of DMA errata"). But the workaround used there does not apply to AM335x, AM437x SoCs. After using DMA, the UART module on these SoCs must be soft reset to go to idle. This patch implements that errata workaround. It is expected that UART will be used with DMA so no explicit check for DMA usage has been added for errata applicability. MDR1 register needs to be restored right after soft-reset because "UART mode" must be set in that register for module wake-up on AM335x to work. As a result, SCR register is now used to determine if context was lost during sleep. [1] See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. http://www.ti.com/lit/er/sprz408b/sprz408b.pdfSigned-off-by:
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Sekhar Nori authored
Use of of_machine_is_compatible() for handling AM335x specific "DMA kick" quirk in 8250_omap driver makes it ugly to extend the quirk for other platforms. Instead use a new compatible. The new compatible will also make it easier to take care of other quirks on AM335x and like SoCs. In order to not break backward DTB compatibility for users of 8250_omap driver on AM335x based boards, existing use of of_machine_is_compatible() has not been removed. Signed-off-by:
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Sekhar Nori authored
The silicon errata[1] workaround implemented in a follow-on patch, "serial: 8250_omap: workaround errata on disabling UART after using DMA", requires MDR1 register programming. Extract MDR1 register update into helper function, omap8250_update_mdr1() to help with that. [1] Advisory 21 in http://www.ti.com/lit/er/sprz408b/sprz408b.pdfSigned-off-by:
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Sekhar Nori authored
The compatible "ti,am4372-uart" is used in arch/arm/boot/dts/am4372.dtsi but not documented. Add necessary documentation. Signed-off-by:
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