- 28 Dec, 2019 5 commits
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Lucas De Marchi authored
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts haswell to hsw where appropriate. Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Acked-by:
Jani Nikula <jani.nikula@linux.intel.com> Acked-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224084012.24241-3-lucas.demarchi@intel.com
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Lucas De Marchi authored
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts pineview to pnv where appropriate. v2: Add missing conversions in intel_pm.c (Matt Roper). While at it, fix missing blank lines between structs that would otherwise trigger checkpatch errors (Lucas) Signed-off-by:
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Lucas De Marchi authored
Drop the intel prefix since all these structs are static and prefer using the 3-letter prefix for each platform. v2: also remove gen from the device info (Ville) Signed-off-by:
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Lukasz Fiedorowicz authored
Debugfs i915_gem_object is extended to enable the IGTs to detect the LMEM's availability and the total size of LMEM. v2: READ_ONCE is used [Chris] v3: %pa is used for printing the resource [Chris] v4: All regions' details added to debugfs [Chris] v5: Macro for_each_mem_region added name is initialized at region init [Chris] Signed-off-by:Lukasz Fiedorowicz <lukasz.fiedorowicz@intel.com> Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Signed-off-by:
Stuart Summers <stuart.summers@intel.com> Signed-off-by:
Ramalingam C <ramalingam.c@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Chris Wilson authored
In commit d03b224f ("drm/i915/gt: Apply sanitiization just before resume") the GT sanitization was pulled into the resume path as we need to know the backend in order to do a full reset prior to resume. However, it is still imperative that we scrub existing GPU state before clobbering in our early setup, so restore a minimal GPU reset at the start of our init sequence. Fixes: d03b224f ("drm/i915/gt: Apply sanitiization just before resume") Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191228111255.3086901-1-chris@chris-wilson.co.uk
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- 27 Dec, 2019 4 commits
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Matt Roper authored
Although the workaround number and description are the same, the vsunit clock gate disable bit has moved to a new register and location on gen12. Bspec: 52890 Bspec: 52758 Cc: stable@kernel.vger.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
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Matt Roper authored
Workaround database indicates we should disable clock gating of both the vsunit and hsunit. Bspec: 33450 Bspec: 33451 Cc: stable@kernel.vger.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
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Matt Roper authored
WaDisableDARBFClkGating, now known as Wa_14010480278, has been added to the workaround tables for ICL, EHL, and TGL so we need to extend our platform test accordingly. Bspec: 33450 Bspec: 33451 Bspec: 52890 Cc: stable@kernel.vger.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
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Chris Wilson authored
If gt initialisation failed, we are left with no engines to use for coherency testing. Currently we bug out, which makes the actual error, so fail more gracefully instead. Closes: https://gitlab.freedesktop.org/drm/intel/issues/896Signed-off-by:
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- 26 Dec, 2019 3 commits
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Chris Wilson authored
Do not expose incomplete engines to the user after we fail to setup the GT. Fixes: e6ba7648 ("drm/i915: Remove i915->kernel_context") Signed-off-by:
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Chris Wilson authored
Bring sanitization completely underneath the umbrella of intel_gt, and perform it exclusively after suspend and before the next resume. Signed-off-by:
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Chris Wilson authored
In record defaults, if we emit a request we expect a context switck on parking. We need take no further action, so don't even mess with the low level engine->serial where it is not warranted. Signed-off-by:
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- 25 Dec, 2019 1 commit
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Chris Wilson authored
Add a space between the prefixed format and the users format so that the join are not mistakenly combined into one long word. Fixes: 639f2f24 ("drm/i915: Introduce new macros for tracing") Signed-off-by:
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- 24 Dec, 2019 3 commits
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Tvrtko Ursulin authored
IDR internally uses xarray so we can use it directly which simplifies our code by removing the need to do external locking. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
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Chris Wilson authored
Our goal in wait_for_idle (intel_gt_retire_requests) is to the current workload *and* their idle barriers. This requires us to notice the late arrival of those, which is done by inspecting the list of active timelines. However, if a concurrent retirer is running that new timeline may not be added until after we drop the lock -- so flush concurrent retirers before we take the lock and inspect the list. Closes: https://gitlab.freedesktop.org/drm/intel/issues/878Signed-off-by:
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Pankaj Bharadiya authored
intel_bw_state allocated memory is not getting freed even after module removal. kmemleak reported backtrace: [<0000000079019739>] kmemdup+0x17/0x40 [<00000000d58c1b9d>] intel_bw_duplicate_state+0x1b/0x40 [i915] [<000000007423ed0c>] drm_atomic_get_private_obj_state+0xca/0x140 [<00000000100e3533>] intel_bw_atomic_check+0x133/0x350 [i915] [<00000000126d0e0c>] intel_atomic_check+0x1ab7/0x20d0 [i915] [<00000000d5dfc004>] drm_atomic_check_only+0x563/0x810 [<00000000c9379611>] drm_atomic_commit+0xe/0x50 [<00000000ec82b765>] drm_atomic_helper_disable_all+0x133/0x160 [<000000003c44760c>] drm_atomic_helper_shutdown+0x65/0xc0 [<00000000414e3e5c>] i915_driver_remove+0xcb/0x130 [i915] [<00000000f8544c2a>] i915_pci_remove+0x19/0x40 [i915] [<000000002dcbd148>] pci_device_remove+0x36/0xb0 [<000000003c8c6b0a>] device_release_driver_internal+0xe0/0x1c0 [<00000000580e9566>] unbind_store+0xc3/0x120 [<00000000869d0df5>] kernfs_fop_write+0x104/0x190 [<000000004dc1a355>] vfs_write+0xb9/0x1d0 Call the drm_atomic_private_obj_fini(), which inturn calls the intel_bw_destroy_state() to make sure the intel_bw_state memory is freed properly. Reviewed-by:Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com> Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191209143921.9240-1-pankaj.laxminarayan.bharadiya@intel.com
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- 23 Dec, 2019 24 commits
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Chris Wilson authored
Use the status of the timeline request list as we retire it to determine if the timeline is still active. Signed-off-by:
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José Roberto de Souza authored
This function is only called from port sync and it is identical to what will be executed again in intel_update_crtc() over port sync pipes. If it is really necessary at least it deserves a better name and a comment, leaving it to people working on port sync. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191223010654.67037-7-jose.souza@intel.com
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José Roberto de Souza authored
MST master can not be disabled while it have attached MST slaves, so it is necessary force a modeset in all of its slaves. v3: - moved handling to intel_atomic_check() this way is guarantee that all pipes will have its state computed v4: - added a function to return if MST master neeeds modeset to simply code in intel_atomic_check() v5: - fixed and moved code to check if MST master needs a modeset v6: - previons version of this patch was split into two patches Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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José Roberto de Souza authored
MST and port sync have master and slaves pipes and it brings dependencies between pipes to allow fastset. For example if only MST master needs a modeset all of its slaves also needs to do a modeset. This patch adds the base for external dependencies check, the MST and port sync bits will be added in another patches. v3: - moved handling to intel_atomic_check() this way is guarantee that all pipes will have its state computed v4: - added a function to return if MST master neeeds modeset to simply code in intel_atomic_check() v5: - fixed and moved code to check if MST master needs a modeset v6: - previons version of this patch was split into two patches Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
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José Roberto de Souza authored
The disable sequence after wait for transcoder off was not correctly implemented. The MST disable sequence is basically the same for HSW, SKL, ICL and TGL, with just minor changes for TGL. With this last patch we finally fixed the hotplugs triggered by MST sinks during the disable/enable sequence, those were causing source to try to do a link training while it was not ready causing CPU pipe FIFO underrrus on TGL. v2: Only unsetting TGL_TRANS_DDI_PORT_MASK for TGL on the post disable sequence v4: Rebased, moved MST sequences to intel_mst_post_disable_dp() BSpec: 4231 BSpec: 4163 BSpec: 22243 BSpec: 49190 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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José Roberto de Souza authored
Due to DDB overlaps the pipe enabling sequence is not always crescent. As the previous patch selects the smallest pipe/transcoder in the MST stream to be master and it needs to be enabled first, this changes were needed to guarantee that. So first lets enable all pipes that do not need a fullmodeset as those don't have any external dependency and those are the ones that can overlap with each other. Then on the second loop it will enable all the pipes that needs a modeset and don't depends on other pipes like MST master pipe/transcoder. Then finally all the pipes that needs a modeset and have dependency on other pipes, that at this point are alread enabled. v3: rebased v4: - added check for modeset_pipes too to decide if is necessary for a wait a vblank - added DDB allocation overlap check for pipes that needs a modeset Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
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José Roberto de Souza authored
On TGL the blending of all the streams have moved from DDI to transcoder, so now every transcoder working over the same MST port must send its stream to a master transcoder and master will send to DDI respecting the time slots. So here adding all the CRTCs that shares the same MST stream if needed and computing their state again, it will pick the lowest pipe/transcoder among the ones in the same stream to be master. Most of the time skl_commit_modeset_enables() enables pipes in a crescent order but due DDB overlapping it might not happen, this scenarios will be handled in the next patch. v2: - Using recently added intel_crtc_state_reset() to set mst_master_transcoder to invalid transcoder for all non gen12 & MST code paths - Setting lowest pipe/transcoder as master, previously it was the first one but setting a predictable one will help in future MST e port sync integration - Moving to intel type as much as we can v3: - Now intel_dp_mst_master_trans_compute() returns the MST master transcoder - Replaced stdbool.h by linux/types.h - Skip the connector being checked in intel_dp_mst_atomic_master_trans_check() - Using pipe instead of transcoder to compute MST master v4: - renamed connector_state to conn_state v5: - Improved the parameters of intel_dp_mst_master_trans_compute() to simply code - Added call drm_atomic_add_affected_planes() in intel_dp_mst_atomic_master_trans_check() as helper could not do it for us - Removed "if (ret)" left over from v3 changes v6: - handled ret == I915_MAX_PIPES case in compute BSpec: 50493 BSpec: 49190 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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José Roberto de Souza authored
intel_connector_needs_modeset() will be used outside of intel_display.c in a future patch so it would only be necessary to remove the state and add the prototype to the header file. But while at it, I simplified the arguments and moved it to a better place intel_atomic.c. No behavior changes intended here. v3: - removed digital from exported version of intel_connector_needs_modeset - rollback connector to drm type v4: - Renamed new_connector_state to new_conn_state - Going back to drm_connector_state in intel_encoders_update_prepare/complete as we also have intel_tv_connector_state Reviewed-by:
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Jani Nikula authored
Signed-off-by:Jani Nikula <jani.nikula@intel.com>
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Chris Wilson authored
The only protection for intel_context.gem_cotext is granted by RCU, so annotate it as a rcu protected pointer and carefully dereference it in the few occasions we need to use it. Fixes: 9f3ccd40 ("drm/i915: Drop GEM context as a direct link from i915_request") Signed-off-by:
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Chris Wilson authored
Start introducing a kref on i915_vma in order to protect the vma unbind (i915_gem_object_unbind) from a parallel destruction (i915_vma_parked). Later, we will use the refcount to manage all access and turn i915_vma into a first class container. Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191222210256.2066451-2-chris@chris-wilson.co.uk
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Chris Wilson authored
Only acquire the various atomic references required to unbind the vma if we do need to unbind the vma. Signed-off-by:
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Imre Deak authored
For CCS formats, the current DRM core check for YUV semiplanar formats doesn't work; use an i915 specific function for that. v2: Fix checkpatch warnings. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191221120543.22816-11-imre.deak@intel.com
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Imre Deak authored
Y planes program the offset and stride of the AUX plane, so make sure we copy the required info for this into their plane state. Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Dhinakaran Pandiyan authored
During framebuffer creation, we pre-compute offsets for 90/270 plane rotation. However, only Y and Yf modifiers support 90/270 rotation. So, skip the calculations for other modifiers. To keep the gem buffer size check still working for tiled planes, factor out the logic needed for rotation setup and skip only this part for tiled planes other than Y/Yf. v2: Add a bounds check WARN for the rotation info array. v3: Keep the gem buffer size check working for tiled planes. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by:
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Imre Deak authored
The CCS plane stride must be fixed on TGL, as it's not configurable for the display. Instead the HW has a hardwired logic to determine it from the main plane stride. Make sure userspace passes in the correct stride. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Dhinakaran Pandiyan authored
Gen-12 display decompression operates on Y-tiled compressed main surface. The CCS is linear and has 4 bits of metadata for each main surface cache line pair, a size ratio of 1:256. Gen-12 display decompression is incompatible with buffers compressed by earlier GPUs, so make use of a new modifier to identify gen-12 compression. Another notable change is that render decompression is supported on all planes except cursor and on all pipes. Start by adding render decompression support for [A,X]BGR888 pixel formats. v2: Fix checkpatch warnings (Lucas) v3: Rebase, disable color clear, styling changes and modify intel_tile_width_bytes and intel_tile_height to handle linear CCS v4: - Use format block descriptors and the i915 specific func to get the subsampling for each color plane. - Use helpers to convert between CCS and main planes. v5: - Fix subsampling returned by intel_fb_plane_get_subsampling() for the CCS plane of the first plane. v6: - Rebased on v2 of patch 4. v7: - Fix plane dimensions during FB check. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Nanley G Chery <nanley.g.chery@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
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Dhinakaran Pandiyan authored
Gen-12 has a new compression format, add a new modifier to indicate that. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Nanley G Chery <nanley.g.chery@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Mika Kahola <mika.kahola@intel.com> Cc: dri-devel@lists.freedesktop.org Signed-off-by:
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Imre Deak authored
Using helpers instead of open coding this to select a CCS plane for a main plane makes the code cleaner and less error-prone when the location of CCS plane can be different based on the format (packed vs. YUV semiplanar). The same applies to selecting an AUX plane which can be a UV plane (for an uncompressed YUV semiplanar format), or a CCS plane. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Dhinakaran Pandiyan authored
intel_fill_fb_info() has grown quite large and wrapping the offset checks into a separate function makes the loop a bit easier to follow. v2: Skip the check for non-CCS planes. (Mika) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Dhinakaran Pandiyan authored
Easier to read if all the alignment changes are in one place and contained within a function. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Dhinakaran Pandiyan authored
intel_tile_dims() computes tile height using size and width, when there is already a function to do just that - intel_tile_height() Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Jani Nikula authored
Needs i915_drv.h because i915 gets dereferenced. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by:
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Jani Nikula authored
Fix the forward declaration. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by:
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