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  1. 02 Apr, 2020 9 commits
    • Bjorn Helgaas's avatar
      Merge branch 'pci/virtualization' · 1ee57ad6
      Bjorn Helgaas authored 
        - Add ACS quirks for Zhaoxin Root Ports, Downstream Ports, and
    multi-function devices (Raymond Pang)

* pci/virtualization:
  PCI: Add ACS quirk for Zhaoxin Root/Downstream Ports
  PCI: Add ACS quirk for Zhaoxin multi-function devices
  PCI: Add Zhaoxin Vendor ID
      1ee57ad6
    • Bjorn Helgaas's avatar
      Merge branch 'pci/resource' · 86845e37
      Bjorn Helgaas authored 
        - Use ioremap(), not phys_to_virt() for platform ROM, to fix video ROM
    mapping with CONFIG_HIGHMEM (Mikel Rychliski)

  - Add support for root bus sizing so we don't have to assume host bridge
    windows are known a priori (Ivan Kokshaysky)

  - Fix alpha Nautilus PCI setup, which has been broken since we started
    enforcing window limits in resource allocation (Ivan Kokshaysky)

* pci/resource:
  alpha: Fix nautilus PCI setup
  PCI: Add support for root bus sizing
  PCI: Use ioremap(), not phys_to_virt() for platform ROM
      86845e37
    • Bjorn Helgaas's avatar
      Merge branch 'pci/p2pdma' · de71a000
      Bjorn Helgaas authored 
        - Add Intel Sky Lake-E Root Ports B, C, D to P2PDMA whitelist (Andrew
    Maier)

* pci/p2pdma:
  PCI/P2PDMA: Add Intel Sky Lake-E Root Ports B, C, D to the whitelist
      de71a000
    • Bjorn Helgaas's avatar
      Merge branch 'pci/misc' · 10e8141b
      Bjorn Helgaas authored 
        - Move _HPX type array from stack to static data (Colin Ian King)

  - Avoid an ASMedia XHCI USB PME# defect; apparently it doesn't assert
    PME# when USB3.0 devices are hotplugged in D0 (Kai-Heng Feng)

  - Revert sysfs "rescan" file renames that broke an application (Kelsey
    Skunberg)

* pci/misc:
  PCI: sysfs: Revert "rescan" file renames
  PCI: Avoid ASMedia XHCI USB PME# from D0 defect
  PCI/ACPI: Move pcie_to_hpx3_type[] from stack to static data
      10e8141b
    • Bjorn Helgaas's avatar
      Merge branch 'pci/interrupts' · 74f0862c
      Bjorn Helgaas authored 
        - Extend boot interrupt quirk to cover several Xeon chipsets (Sean V
    Kelley)

  - Add documentation about boot interrupts (Sean V Kelley)

* pci/interrupts:
  Documentation: PCI: Add background on Boot Interrupts
  PCI: Add boot interrupt quirk mechanism for Xeon chipsets
      74f0862c
    • Bjorn Helgaas's avatar
      Merge branch 'pci/hotplug' · 30386853
      Bjorn Helgaas authored 
        - Disable in-band presence detection when possible (Alexandru Gagniuc)

  - Poll for presence detect if in-band presence detection is disabled
    (Alexandru Gagniuc)

  - Add DMI table of systems that don't support in-band presence detection
    (Stuart Hayes)

  - Fix indefinite pciehp wait caused by race in handling sysfs requests
    (Lukas Wunner)

  - Fix pciehp MSI interrupt race that caused us to miss interrupts (Stuart
    Hayes)

* pci/hotplug:
  PCI: pciehp: Fix MSI interrupt race
  PCI: pciehp: Fix indefinite wait on sysfs requests
  PCI: pciehp: Add DMI table for in-band presence detection disabled
  PCI: pciehp: Wait for PDS if in-band presence is disabled
  PCI: pciehp: Disable in-band presence detect when possible
      30386853
    • Bjorn Helgaas's avatar
      Merge branch 'pci/enumeration' · eb81b249
      Bjorn Helgaas authored 
        - Add PCIe 32 GT/s speed decoding for sysfs "max_link_speed" and dmesg
    notes about available bandwidth (Yicong Yang)

  - Simplify and unify PCI bus/link speed reporting (Yicong Yang)

* pci/enumeration:
  PCI: Add PCIE_LNKCAP2_SLS2SPEED() macro
  PCI: Use pci_speed_string() for all PCI/PCI-X/PCIe strings
  PCI: Add pci_speed_string()
  PCI: Add 32 GT/s decoding in some macros
      eb81b249
    • Bjorn Helgaas's avatar
      Merge branch 'pci/edr' · 4ea40c38
      Bjorn Helgaas authored 
        - Update error status after reset_link() so we don't report "recovery
    failed" when it in fact succeeded (Kuppuswamy Sathyanarayanan)

  - Move DPC data into struct pci_dev instead of allocating a separate
    struct dpc_dev (Bjorn Helgaas)

  - Remove AER/DPC service dependency to simplify error recovery
    (Kuppuswamy Sathyanarayanan)

  - Return error recovery status for future use by EDR, which needs to tell
    firmware whether recovery was successful (Kuppuswamy Sathyanarayanan)

  - Cache DPC capability info in core since it's needed by EDR as well as
    DPC driver (Kuppuswamy Sathyanarayanan)

  - Add pci_aer_raw_clear_status() to allow EDR recovery path to clear AER
    status even when OS doesn't own the AER capability (Kuppuswamy
    Sathyanarayanan)

  - Add Error Disconnect Recover (EDR) support, so firmware can use ACPI
    notification to tell the OS that devices have been disconnected, e.g.,
    via DPC, and that OS should attempt recovery (Kuppuswamy
    Sathyanarayanan)

  - Rename AER error status clearing interfaces to be more consistent
    (Kuppuswamy Sathyanarayanan)

* pci/edr:
  PCI/AER: Rationalize error status register clearing
  PCI/DPC: Add Error Disconnect Recover (EDR) support
  PCI/DPC: Expose dpc_process_error(), dpc_reset_link() for use by EDR
  PCI/AER: Add pci_aer_raw_clear_status() to unconditionally clear Error Status
  PCI/DPC: Cache DPC capabilities in pci_init_capabilities()
  PCI/ERR: Return status of pcie_do_recovery()
  PCI/ERR: Remove service dependency in pcie_do_recovery()
  PCI/DPC: Move DPC data into struct pci_dev
  PCI/ERR: Update error status after reset_link()
  PCI/ERR: Combine pci_channel_io_frozen cases
      4ea40c38
    • Bjorn Helgaas's avatar
      Merge branch 'pci/aspm' · dd956a12
      Bjorn Helgaas authored 
        - Clear the correct bits when enabling ASPM L1 substates (Yicong Yang)

  - Reduce severity of ASPM common clock config message (Chris Packham)

* pci/aspm:
  PCI/ASPM: Reduce severity of common clock config message
  PCI/ASPM: Clear the correct bits when enabling L1 substates
      dd956a12
  3. 31 Mar, 2020 2 commits
    • Stuart Hayes's avatar
      PCI: pciehp: Fix MSI interrupt race · 8edf5332
      Stuart Hayes authored 
      Without this commit, a PCIe hotplug port can stop generating interrupts on
hotplug events, so device adds and removals will not be seen:

The pciehp interrupt handler pciehp_isr() reads the Slot Status register
and then writes back to it to clear the bits that caused the interrupt.  If
a different interrupt event bit gets set between the read and the write,
pciehp_isr() returns without having cleared all of the interrupt event
bits.  If this happens when the MSI isn't masked (which by default it isn't
in handle_edge_irq(), and which it will never be when MSI per-vector
masking is not supported), we won't get any more hotplug interrupts from
that device.

That is expected behavior, according to the PCIe Base Spec r5.0, section
6.7.3.4, "Software Notification of Hot-Plug Events".

Because the Presence Detect Changed and Data Link Layer State Changed event
bits can both get set at nearly the same time when a device is added or
removed, this is more likely to happen than it might seem.  The issue was
found (and can be reproduced rather easily) by connecting and disconnecting
an NVMe storage device on at least one system model where the NVMe devices
were being connected to an AMD PCIe port (PCI device 0x1022/0x1483).

Fix the issue by modifying pciehp_isr() to loop back and re-read the Slot
Status register immediately after writing to it, until it sees that all of
the event status bits have been cleared.

[lukas: drop loop count limitation, write "events" instead of "status",
don't loop back in INTx and poll modes, tweak code comment & commit msg]
Link: https://lore.kernel.org/r/78b4ced5072bfe6e369d20e8b47c279b8c7af12e.1582121613.git.lukas@wunner.deTested-by: default avatarStuart Hayes <stuart.w.hayes@gmail.com>
Signed-off-by: default avatarStuart Hayes <stuart.w.hayes@gmail.com>
Signed-off-by: default avatarLukas Wunner <lukas@wunner.de>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarJoerg Roedel <jroedel@suse.de>
      8edf5332
    • Lukas Wunner's avatar
      PCI: pciehp: Fix indefinite wait on sysfs requests · 3e487d2e
      Lukas Wunner authored 
      David Hoyer reports that powering pciehp slots up or down via sysfs may
hang:  The call to wait_event() in pciehp_sysfs_enable_slot() and
_disable_slot() does not return because ctrl->ist_running remains true.

This flag, which was introduced by commit 157c1062 ("PCI: pciehp: Avoid
returning prematurely from sysfs requests"), signifies that the IRQ thread
pciehp_ist() is running.  It is set to true at the top of pciehp_ist() and
reset to false at the end.  However there are two additional return
statements in pciehp_ist() before which the commit neglected to reset the
flag to false and wake up waiters for the flag.

That omission opens up the following race when powering up the slot:

* pciehp_ist() runs because a PCI_EXP_SLTSTA_PDC event was requested
  by pciehp_sysfs_enable_slot()

* pciehp_ist() turns on slot power via the following call stack:
  pciehp_handle_presence_or_link_change() -> pciehp_enable_slot() ->
  __pciehp_enable_slot() -> board_added() -> pciehp_power_on_slot()

* after slot power is turned on, the link comes up, resulting in a
  PCI_EXP_SLTSTA_DLLSC event

* the IRQ handler pciehp_isr() stores the event in ctrl->pending_events
  and returns IRQ_WAKE_THREAD

* the IRQ thread is already woken (it's bringing up the slot), but the
  genirq code remembers to re-run the IRQ thread after it has finished
  (such that it can deal with the new event) by setting IRQTF_RUNTHREAD
  via __handle_irq_event_percpu() -> __irq_wake_thread()

* the IRQ thread removes PCI_EXP_SLTSTA_DLLSC from ctrl->pending_events
  via board_added() -> pciehp_check_link_status() in order to deal with
  presence and link flaps per commit 6c35a1ac ("PCI: pciehp:
  Tolerate initially unstable link")

* after pciehp_ist() has successfully brought up the slot, it resets
  ctrl->ist_running to false and wakes up the sysfs requester

* the genirq code re-runs pciehp_ist(), which sets ctrl->ist_running
  to true but then returns with IRQ_NONE because ctrl->pending_events
  is empty

* pciehp_sysfs_enable_slot() is finally woken but notices that
  ctrl->ist_running is true, hence continues waiting

The only way to get the hung task going again is to trigger a hotplug
event which brings down the slot, e.g. by yanking out the card.

The same race exists when powering down the slot because remove_board()
likewise clears link or presence changes in ctrl->pending_events per commit
3943af9d ("PCI: pciehp: Ignore Link State Changes after powering off a
slot") and thereby may cause a re-run of pciehp_ist() which returns with
IRQ_NONE without resetting ctrl->ist_running to false.

Fix by adding a goto label before the teardown steps at the end of
pciehp_ist() and jumping to that label from the two return statements which
currently neglect to reset the ctrl->ist_running flag.

Fixes: 157c1062 ("PCI: pciehp: Avoid returning prematurely from sysfs requests")
Link: https://lore.kernel.org/r/cca1effa488065cb055120aa01b65719094bdcb5.1584530321.git.lukas@wunner.deReported-by: default avatarDavid Hoyer <David.Hoyer@netapp.com>
Signed-off-by: default avatarLukas Wunner <lukas@wunner.de>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarKeith Busch <kbusch@kernel.org>
Cc: stable@vger.kernel.org	# v4.19+
      3e487d2e
  5. 30 Mar, 2020 4 commits
  7. 28 Mar, 2020 14 commits
  9. 19 Mar, 2020 1 commit
  11. 18 Mar, 2020 2 commits
  13. 10 Mar, 2020 3 commits
    • Yicong Yang's avatar
      PCI: Add PCIE_LNKCAP2_SLS2SPEED() macro · 757bfaa2
      Yicong Yang authored 
      Add PCIE_LNKCAP2_SLS2SPEED macro for transforming raw Link Capabilities 2
values to the pci_bus_speed. This is next to PCIE_SPEED2MBS_ENC() to make
it easier to update both places when adding support for new speeds.

Link: https://lore.kernel.org/r/1581937984-40353-10-git-send-email-yangyicong@hisilicon.comSigned-off-by: default avatarYicong Yang <yangyicong@hisilicon.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      757bfaa2
    • Bjorn Helgaas's avatar
      PCI: Use pci_speed_string() for all PCI/PCI-X/PCIe strings · 6348a34d
      Bjorn Helgaas authored 
      Previously some PCI speed strings came from pci_speed_string(), some came
from the PCIe-specific PCIE_SPEED2STR(), and some came from a PCIe-specific
switch statement.  These methods were inconsistent:

  pci_speed_string()     PCIE_SPEED2STR()     switch
  ------------------     ----------------     ------
  33 MHz PCI
  ...
  2.5 GT/s PCIe          2.5 GT/s             2.5 GT/s
  5.0 GT/s PCIe          5 GT/s               5 GT/s
  8.0 GT/s PCIe          8 GT/s               8 GT/s
  16.0 GT/s PCIe         16 GT/s              16 GT/s
  32.0 GT/s PCIe         32 GT/s              32 GT/s

Standardize on pci_speed_string() as the single source of these strings.

Note that this adds ".0" and "PCIe" to some messages, including sysfs
"max_link_speed" files, a brcmstb "link up" message, and the link status
dmesg logging, e.g.,

  nvme 0000:01:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x4 link at 0000:00:01.1 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link)

I think it's better to standardize on a single version of the speed text.
Previously we had strings like this:

  /sys/bus/pci/slots/0/cur_bus_speed: 8.0 GT/s PCIe
  /sys/bus/pci/slots/0/max_bus_speed: 8.0 GT/s PCIe
  /sys/devices/pci0000:00/0000:00:1c.0/current_link_speed: 8 GT/s
  /sys/devices/pci0000:00/0000:00:1c.0/max_link_speed: 8 GT/s

This changes the latter two to match the slots files:

  /sys/devices/pci0000:00/0000:00:1c.0/current_link_speed: 8.0 GT/s PCIe
  /sys/devices/pci0000:00/0000:00:1c.0/max_link_speed: 8.0 GT/s PCIe

Based-on-patch by: Yicong Yang <yangyicong@hisilicon.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      6348a34d
    • Bjorn Helgaas's avatar
      PCI: Add pci_speed_string() · e56faff5
      Bjorn Helgaas authored 
      Add pci_speed_string() to return a text description of the supplied bus or
link speed.  The slot code previously used the private
pci_bus_speed_strings[] array for this purpose, but adding this interface
will enable us to consolidate similar code elsewhere.

Export pcie_link_speed[] and pci_speed_string() so they can be used by
modules.
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      e56faff5
  15. 09 Mar, 2020 1 commit
  17. 28 Feb, 2020 1 commit
  19. 27 Feb, 2020 1 commit
    • Sean V Kelley's avatar
      PCI: Add boot interrupt quirk mechanism for Xeon chipsets · b88bf6c3
      Sean V Kelley authored 
      The following was observed by Kar Hin Ong with RT patchset:

  Backtrace:
  irq 19: nobody cared (try booting with the "irqpoll" option)
  CPU: 0 PID: 3329 Comm: irq/34-nipalk Tainted:4.14.87-rt49 #1
  Hardware name: National Instruments NI PXIe-8880/NI PXIe-8880,
           BIOS 2.1.5f1 01/09/2020
  Call Trace:
  <IRQ>
    ? dump_stack+0x46/0x5e
    ? __report_bad_irq+0x2e/0xb0
    ? note_interrupt+0x242/0x290
    ? nNIKAL100_memoryRead16+0x8/0x10 [nikal]
    ? handle_irq_event_percpu+0x55/0x70
    ? handle_irq_event+0x4f/0x80
    ? handle_fasteoi_irq+0x81/0x180
    ? handle_irq+0x1c/0x30
    ? do_IRQ+0x41/0xd0
    ? common_interrupt+0x84/0x84
  </IRQ>
  ...
  handlers:
  [<ffffffffb3297200>] irq_default_primary_handler threaded
  [<ffffffffb3669180>] usb_hcd_irq
  Disabling IRQ #19

The problem being that this device is triggering boot interrupts
due to threaded interrupt handling and masking of the IO-APIC. These
boot interrupts are then forwarded on to the legacy PCH's PIRQ lines
where there is no handler present for the device.

Whenever a PCI device fires interrupt (INTx) to Pin 20 of IOAPIC 2
(GSI 44), the kernel receives two interrupts:

   1. Interrupt from Pin 20 of IOAPIC 2  -> Expected
   2. Interrupt from Pin 19 of IOAPIC 1  -> UNEXPECTED

Quirks for disabling boot interrupts (preferred) or rerouting the
handler exist but do not address these Xeon chipsets' mechanism:
https://lore.kernel.org/lkml/12131949181903-git-send-email-sassmann@suse.de/

Add a new mechanism via PCI CFG for those chipsets supporting CIPINTRC
register's dis_intx_rout2ich bit.

Link: https://lore.kernel.org/r/20200220192930.64820-2-sean.v.kelley@linux.intel.comReported-by: default avatarKar Hin Ong <kar.hin.ong@ni.com>
Tested-by: default avatarKar Hin Ong <kar.hin.ong@ni.com>
Signed-off-by: default avatarSean V Kelley <sean.v.kelley@linux.intel.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
      b88bf6c3
  21. 21 Feb, 2020 2 commits
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