- 22 Aug, 2016 9 commits
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Christian König authored
Adding a BO can make it the insertion point for larger sizes as well. v2: add a comment about the guard structure. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Tom St Denis authored
Clean up whitespace and formatting. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by:
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Marek Olšák authored
For profiling. v2: really bump the minor version Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Chunming Zhou authored
V2: 1. don't directly submit to many jobs at the same time. 2. delete unrelated printk. Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
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Chunming Zhou authored
V2: 1. use mutex instead of spinlock for shadow list, since its process could sleep. 2. move list_del to bo destroy phase. Signed-off-by:
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Chunming Zhou authored
V2: move shadow parameter to amdgpu_pte_update_params. Signed-off-by:
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Chunming Zhou authored
V2: Checking if shadow is valid. Signed-off-by:
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Chunming Zhou authored
Use shadow flag to judge which direction to sync. V2: Don't need bo pin, so remove it. V3: 1. Split to two functions, one is backup_to_shadow, another is restore_from_shadow. 2. Clean up previous shadow direction difinitions. Signed-off-by:
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Chunming Zhou authored
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- 19 Aug, 2016 7 commits
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Chunming Zhou authored
V2: add checking if need backup in amdgpu_bo_create. Signed-off-by:
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jimqu authored
Phenomenon: software hang when device resume back, read UVD fence is 0xffffffff and read pcie pid is 0xffff. The issue is caused by VCE reset when update cg setting. according to HW programming guide, adjust update VCE cg sequence. The patch apply to VCE2.0. Signed-off-by:
JimQu <Jim.Qu@amd.com> Reviewed-by:
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Flora Cui authored
Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
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Flora Cui authored
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Flora Cui authored
abort if the bo is pined to other domain already Signed-off-by:
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Flora Cui authored
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Rex Zhu authored
v2: fix build error introduced when fix code style problems. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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- 17 Aug, 2016 2 commits
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Tom St Denis authored
Adds family and external_rev_id to config data Signed-off-by:
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Emily Deng authored
For virtual display feature, by hardcoding 0 for the vblank counter and -EINVAL for the scanout position return value, we signal to the core DRM code that there are no hardware counters we can use for these. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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- 16 Aug, 2016 16 commits
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Tom St Denis authored
Adds rev_id as well as cg/pg flags to help debug runtime. Signed-off-by:
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Christian König authored
Just a few 80 chars problems. Signed-off-by:
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Christian König authored
Remember what function to call while planning the commands instead of figuring it our later on. Signed-off-by:
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Christian König authored
It doesn't make much sense to create bigger commands first which we then need to split into smaller one again. Just make sure the commands we create aren't to big in the first place. Signed-off-by:
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Christian König authored
Not used any more. Signed-off-by:
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Christian König authored
We don't need the gart mapping handling here any more. Signed-off-by:
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Christian König authored
Not needed any more. Signed-off-by:
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Christian König authored
Write the PTEs at the end of the IB instead of directly into the SDMA commands. This can save quite some CPU cycles building the entries. This doesn't change the DW estimation because PTEs where embedded into the IB before as well. It just moves them to the end of the IB. Signed-off-by:
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Chunming Zhou authored
Indicate if need to sync between bo and shadow, where sync to where. V2: Rename to backup_shadow Signed-off-by:
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Chunming Zhou authored
The pd/pt shadow bo will be used to backup page table, when gpu reset happens, we can restore the page table by them. V2: Free shadow bo. Signed-off-by:
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Chunming Zhou authored
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Chunming Zhou authored
shadow bo is the shadow of a bo, which is always in GTT, which can be used to backup the original bo. V2: reference shadow parent, shadow bo will be freed by who allocted him. Signed-off-by:
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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- 10 Aug, 2016 6 commits
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Alexandre Demers authored
Reviewed-by:
Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by:
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Michel Dänzer authored
These flags allow userspace to explicitly specify the target vertical blank period when a flip should take effect. v2: * Add new struct drm_mode_crtc_page_flip_target instead of modifying struct drm_mode_crtc_page_flip, to make sure all existing userspace code keeps compiling (Daniel Vetter) Acked-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Michel Dänzer authored
With the previous change, it's safe to let page flips take effect anytime during a vertical blank period. This can avoid delaying a flip by a frame in some cases where we get to radeon_flip_work_func -> adev->mode_info.funcs->page_flip during a vertical blank period. Acked-by:
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Michel Dänzer authored
Now we can program a flip during a vertical blank period, if it's the one targeted by the flip (or a later one). This allows simplifying radeon_flip_work_func considerably. Acked-by:
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Michel Dänzer authored
With the previous change, it's safe to let page flips take effect anytime during a vertical blank period. This can avoid delaying a flip by a frame in some cases where we get to amdgpu_flip_work_func -> adev->mode_info.funcs->page_flip during a vertical blank period. Acked-by:
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Michel Dänzer authored
Now we can program a flip during a vertical blank period, if it's the one targeted by the flip (or a later one). This allows simplifying amdgpu_flip_work_func considerably. agd: update dce_virtual.c as well. Acked-by:
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