- 24 May, 2017 40 commits
-
-
Monk Liu authored
Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Monk Liu authored
this is to prevent fence forever waiting if FLR occured during register accessing. v2: use define instead of hardcode for the timeout msec Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
-
Alex Deucher authored
We need to make sure the various init sequences submitted to KIQ complete before testing the rings. Reviewed-by:
-
Alex Deucher authored
Rather than magic numbers. Reviewed-by:
-
Alex Deucher authored
Will be used in subsequent commits rather rather than magic numbers. Reviewed-by:
-
Alex Deucher authored
To be consistent with gfx8. Reviewed-by:
-
Alex Deucher authored
And properly synchronize them with the master during queue init. Reviewed-by:
-
Shaoyun Liu authored
The usage of kiq should not depend on the virtualization. Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by:
Andres Rodriquez <andresx7@gmail.com> Signed-off-by:
-
Chunming Zhou authored
Interface to reserve a vmid for a specific process to add in shader debugging that requries a fixed vmid. Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
-
Chunming Zhou authored
Implement the vmid reservation. v2: move sync waiting only when flush needs v3: fix racy v4: peek fence instead of get fence, and fix potential context starved. Signed-off-by:
-
Chunming Zhou authored
Limit reserved vmids to 1 to avoid taking too many out of commission and starving the system. v2: move #define to amdgpu_vm.h v3: move reserved vmid counter to id_manager, and increase counter before allocating vmid v4: rename to reserved_vmid_num Signed-off-by:
-
Chunming Zhou authored
add reserve/unreserve vmid funtions. Used to reserve vmids for certain shader debugging functionality that required a fixed vmid for the life of the debug. v3: only reserve vmid from gfxhub v4: fix racy condition Signed-off-by:
-
Chunming Zhou authored
v2: rename dedicated_vmid to reserved_vmid Signed-off-by:
-
Chunming Zhou authored
It will be used for reserving vmid for shader debugging that requires a fixed vmid. v2: fix warning (Alex) Signed-off-by:
-
Trigger Huang authored
Support for MCBP/Virtualization in combination with chained IBs is formal released on firmware feature version #46. So enable it according to firmware feature version, otherwise, world switch will hang. Signed-off-by:
Trigger Huang <trigger.huang@amd.com> Reviewed-by:
-
Rex Zhu authored
Bug: SWDEV-117987: Always on CU mask broken for gfx7+ Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Acked-by:
-
Rex Zhu authored
Signed-off-by:
-
Xiangliang Yu authored
Change place of virt_init_setting function so that can cover the cg and pg flags configuration. Signed-off-by:
-
Xiangliang Yu authored
GPU hypervisor cover all settings of CG and PG, so guest doesn't need to do anything. Bypass it. Signed-off-by:
Frank Min <Frank.Min@amd.com> Signed-off-by:
-
Christian König authored
Only per family registers are still used. Signed-off-by:
-
Christian König authored
I couldn't figure out what this was original good for, but we don't use it any more. Signed-off-by:
-
Rex Zhu authored
Signed-off-by:
-
Rex Zhu authored
Signed-off-by:
-
Xiaojie Yuan authored
Signed-off-by:
Xiaojie Yuan <Xiaojie.Yuan@amd.com> Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by:
-
Xiaojie Yuan authored
v2: refine dce_v6_0_audio_endpt_wreg() and unify inconsistent method names v3: fix num_pins for tahiti, pitcairn, verde and oland Signed-off-by:
-
Alex Deucher authored
I'm not sure if the order matters, but it seems like it makes more sense to set this after the range is programmed. v2: rebase (Alex) Signed-off-by: -
Rex Zhu authored
add set_doorbell functions for mec and cpg. Signed-off-by:
-
Alex Deucher authored
This could be used in Andres' priority scheduling patch as well. Reviewed-by:
-
Alex Deucher authored
Even if we disable clockgating, we still need to make sure the cp/rlc interrupts are enabled for powergating which might still be enabled. Acked-by:
-
Alex Deucher authored
Even if we disable clockgating, we still need to make sure the cp/rlc interrupts are enabled for powergating which might still be enabled. Acked-by:
-
Alex Deucher authored
It's global, not queue specific, so move it out of the kiq register init function. Tested-and-Reviewed-by:
-
Alex Deucher authored
No need to reset the wptr and clear the rings. The UNMAP_QUEUES packet writes the current MQD state back the MQD on suspend, so there is no need to reset it as well. Signed-off-by: -
Alex Deucher authored
Use the UNMAP_QUEUES packet to have the KIQ properly disable them. Reviewed-by:
-
Alex Deucher authored
Rather than open coding them. Reviewed-by:
-
Alex Deucher authored
As the KCQ setup. This way we only have to wait once for the entire MEC. Reviewed-by:
-
Alex Deucher authored
Rather than waiting for each queue. Reviewed-by:
-
Alex Deucher authored
One for KIQ and one for the KCQ. This simplifies the logic and allows for future optimizations. Reviewed-by:
-
Alex Deucher authored
We need to make sure the various init sequences submitted to KIQ complete before testing the rings. Reviewed-by:
-
Alex Deucher authored
Re-enable GFX PG. It's working properly with MEC now that KIQ is enabled. Reviewed-by:Samuel Li <samuel.li@amd.com> This reverts commit e9ef19aa1bdeac380662a112f1d03a7c3477527f.
-
David Panariti authored
KIQ is the Kernel Interface Queue for managing the MEC. Rather than setting up rings via direct MMIO of ring registers, the rings are configured via special packets sent to the KIQ. The allows the MEC to better manage shared resources and certain power events. v2: squash in s3/s4 fix from Rex v3: further fixes from Rex Signed-off-by:
David Panariti <David.Panariti@amd.com> Reviewed-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
-
